Extend the FPGA Security Manager class driver to
include an update/status sysfs node that can be polled
and read to monitor the progress of an ongoing secure
update. Sysfs_notify() is used to signal transitions
between different phases of the update process.
Signed-off-by: Russ Weight
Reviewed
be signaled by sysfs_notify() on each
state change.
+What: /sys/class/fpga_sec_mgr/fpga_secX/update/remaining_size
+Date: April 2021
+KernelVersion: 5.13
+Contact: Russ Weight
+Description: Read-only. Returns the size of data that remains to
+ be wr
cause a secure update to occur.
The write of the filename will return immediately, and the
update will begin in the context of a kernel worker thread.
This tool utilizes the request_firmware framework, which
requires that the image file reside under /lib/firmware.
Signed-off-by: Russ Weight
images.
This patch creates the MAX10 BMC Secure Update driver and
provides sysfs files for displaying the current root entry hashes
for the FPGA static region, the FPGA PR region, and the MAX10
BMC.
Signed-off-by: Russ Weight
---
v9:
- Rebased to 5.12-rc2 next
- Updated Date and KernelVersion
Extend the MAX10 BMC Secure Update driver to include
a function that returns 64 bits of additional HW specific
data for errors that require additional information.
This callback function enables the hw_errinfo sysfs
node in the Intel Security Manager class driver.
Signed-off-by: Russ Weight
stride variable in calls to m10bmc_raw_bulk_read().
- Added m10bmc_ prefix to functions in m10bmc_iops structure
- Implemented HW_ERRINFO_POISON for m10bmc_sec_hw_errinfo() to
ensure that corresponding bits are set to 1 if we are unable
to read the doorbell or auth_result registers.
Extend the MAX10 BMC Secure Update driver to provide a
sysfs file to expose the flash update count for the FPGA
user image.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v9:
- Rebased to 5.12-rc2 next
- Updated Date and KernelVersion in ABI documentation
v8:
- Previously patch 3/6
Extend the MAX10 BMC Secure Update driver to provide sysfs
files to expose the canceled code signing key (CSK) bit
vectors. These use the standard bitmap list format
(e.g. 1,2-6,9).
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v9:
- Rebased to 5.12-rc2 next
- Updated Date and
Extend the MAX10 BMC Secure Update driver to include
the functions that enable secure updates of BMC images,
FPGA images, etc.
Signed-off-by: Russ Weight
---
v9:
- No change
v8:
- Previously patch 5/6, otherwise no change
v7:
- No change
v6:
- Changed (size / stride) calculation to
On 1/19/21 12:49 PM, Tom Rix wrote:
> On 1/5/21 3:08 PM, Russ Weight wrote:
>
> ...
>
>> .../testing/sysfs-driver-intel-m10-bmc-secure | 61 ++
>> MAINTAINERS | 2 +
>> drivers/fpga/Kconfig |
Add macros and definitions required by the MAX10 BMC
Secure Update driver.
Signed-off-by: Russ Weight
Acked-by: Lee Jones
---
v8:
- Previously patch 1/6 in "Intel MAX10 BMC Secure Update Driver"
- Rebased on next-20210121
v7:
- No change
v6:
- No change
v5:
- Renamed USER_F
prefix to some definitions
- Some address definitions were moved here from the .c files that
use them.
Russ Weight (1):
mfd: intel-m10-bmc: support for MAX10 BMC Secure Updates
include/linux/mfd/intel-m10-bmc.h | 85 +++
1 file changed, 85 insertions(+)
--
2.25.1
prefix to some definitions
- Some address definitions were moved here from the .c files that
use them.
Russ Weight (1):
mfd: intel-m10-bmc: support for MAX10 BMC Secure Updates
include/linux/mfd/intel-m10-bmc.h | 85 +++
1 file changed, 85 insertions(+)
--
2.25.1
tructure
- Implemented HW_ERRINFO_POISON for m10bmc_sec_hw_errinfo() to
ensure that corresponding bits are set to 1 if we are unable
to read the doorbell or auth_result registers.
- Added comments and additional code cleanup per V1 review.
Russ Weight (5):
fpga: m10bmc-sec: create max
images.
This patch creates the MAX10 BMC Secure Update driver and
provides sysfs files for displaying the current root entry hashes
for the FPGA static region, the FPGA PR region, and the MAX10
BMC.
Signed-off-by: Russ Weight
---
v8:
- Previously patch 2/6, otherwise no change
v7:
- Updated
Extend the MAX10 BMC Secure Update driver to include
a function that returns 64 bits of additional HW specific
data for errors that require additional information.
This callback function enables the hw_errinfo sysfs
node in the Intel Security Manager class driver.
Signed-off-by: Russ Weight
Extend the MAX10 BMC Secure Update driver to provide sysfs
files to expose the canceled code signing key (CSK) bit
vectors. These use the standard bitmap list format
(e.g. 1,2-6,9).
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v8:
- Previously patch 4/6, otherwise no change
v7
Extend the MAX10 BMC Secure Update driver to include
the functions that enable secure updates of BMC images,
FPGA images, etc.
Signed-off-by: Russ Weight
---
v8:
- Previously patch 5/6, otherwise no change
v7:
- No change
v6:
- Changed (size / stride) calculation to ((size + stride - 1
Extend the MAX10 BMC Secure Update driver to provide a
sysfs file to expose the flash update count for the FPGA
user image.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v8:
- Previously patch 3/6, otherwise no change
v7:
- Updated Date and KernelVersion in ABI documentation
v6
On 1/21/21 2:55 PM, Russ Weight wrote:
> This patch was previously patch 1 of 6 in the patch-series entitled
> "Intel MAX10 BMC Secure Update Driver". This is the only patch in
> the series that is subject to conflicts with other ongoing changes
> and is separated here t
On 1/21/21 3:29 PM, Russ Weight wrote:
> The Intel MAX10 BMC Secure Update driver instantiates the FPGA
> Security Manager class driver and provides the callback functions
> required to support secure updates on Intel n3000 PAC devices.
> This driver is implemented as a sub-driver
On 1/1/21 7:13 PM, Xu Yilun wrote:
> This patch adds description for UIO support for dfl devices on DFL
> bus.
>
> Signed-off-by: Xu Yilun
> ---
> v2: no doc in v1, add it for v2.
> v3: some documentation fixes.
> v4: documentation change since the driver matching is changed.
> v5: no change.
>
and KernelVersion in ABI documentation
Changelog v1 -> v2:
- Updated the documentation for the mac_address and mac_count
sysfs nodes to clearify their usage.
- Changed sysfs _show() functions to use sysfs_emit() instead
of sprintf.
Russ Weight (1):
mfd: intel-m10-bmc: expose mac addre
Create two sysfs entries for exposing the MAC address
and count from the MAX10 BMC register space. The MAC
address is the first in a sequential block of MAC addresses
reserved for the FPGA card. The MAC count is the number
of MAC addresses in the reserved block.
Signed-off-by: Russ Weight
Signed
edefs for imgr ops
- Removed explicit value assignments in enums
- Other minor code cleanup per review comments
Russ Weight (7):
fpga: sec-mgr: fpga security manager class driver
fpga: sec-mgr: enable secure updates
fpga: sec-mgr: expose sec-mgr update status
fpga: sec-mgr: expose sec-m
file
and is decoded by the HW/FW secure update engine.
Signed-off-by: Russ Weight
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v9:
- Updated Date and KernelVersion in ABI documentation
v8:
- Fixed grammatical error in Documentation/fpga/fpga-sec-mgr.rst
v7:
- Changed Date in documentation
cause a secure update to occur.
The write of the filename will return immediately, and the
update will begin in the context of a kernel worker thread.
This tool utilizes the request_firmware framework, which
requires that the image file reside under /lib/firmware.
Signed-off-by: Russ Weight
Extend the FPGA Security Manager class driver to
include an update/status sysfs node that can be polled
and read to monitor the progress of an ongoing secure
update. Sysfs_notify() is used to signal transitions
between different phases of the update process.
Signed-off-by: Russ Weight
Reviewed
ec_mgr/fpga_secX/update/remaining_size
+Date: January 2021
+KernelVersion: 5.12
+Contact: Russ Weight
+Description: Read-only. Returns the size of data that remains to
+ be written to the secure update engine. The size
+ value is in
feature. This data is treated as
opaque by the class driver. It is left to user-space software
or support personnel to interpret this data.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v9:
- Updated Date and KernelVersion in ABI documentation
v8:
- No change
v7:
- Changed Date in
.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v9:
- Updated Date and KernelVersion in ABI documentation
v8:
- No change
v7:
- Changed Date in documentation file to December 2020
v6:
- No change
v5:
- No change
v4:
- Changed from "Intel FPGA Security Manager" to FPG
Extend the FPGA Security Manager class driver to include
an update/error sysfs node that can be read for error
information when a secure update fails.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v9:
- Updated Date and KernelVersion in ABI documentation
v8:
- No change
v7
to 1 if we are unable
to read the doorbell or auth_result registers.
- Added comments and additional code cleanup per V1 review.
Russ Weight (6):
mfd: intel-m10-bmc: support for MAX10 BMC Secure Updates
fpga: m10bmc-sec: create max10 bmc secure update driver
fpga: m10bmc-sec: expose m
images.
This patch creates the MAX10 BMC Secure Update driver and
provides sysfs files for displaying the current root entry hashes
for the FPGA static region, the FPGA PR region, and the MAX10
BMC.
Signed-off-by: Russ Weight
---
v7:
- Updated Date and KernelVersion in ABI documentation
v6
Extend the MAX10 BMC Secure Update driver to provide a
sysfs file to expose the flash update count for the FPGA
user image.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v7:
- Updated Date and KernelVersion in ABI documentation
v6:
- Changed flash_count_show() parameter list to
Extend the MAX10 BMC Secure Update driver to include
a function that returns 64 bits of additional HW specific
data for errors that require additional information.
This callback function enables the hw_errinfo sysfs
node in the Intel Security Manager class driver.
Signed-off-by: Russ Weight
Extend the MAX10 BMC Secure Update driver to provide sysfs
files to expose the canceled code signing key (CSK) bit
vectors. These use the standard bitmap list format
(e.g. 1,2-6,9).
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v7:
- Updated Date and KernelVersion in ABI documentation
Extend the MAX10 BMC Secure Update driver to include
the functions that enable secure updates of BMC images,
FPGA images, etc.
Signed-off-by: Russ Weight
---
v7:
- No change
v6:
- Changed (size / stride) calculation to ((size + stride - 1) / stride)
to ensure that the proper count is
Add macros and definitions required by the MAX10 BMC
Secure Update driver.
Signed-off-by: Russ Weight
Acked-by: Lee Jones
---
v7:
- No change
v6:
- No change
v5:
- Renamed USER_FLASH_COUNT to STAGING_FLASH_COUNT
v4:
- No change
v3:
- Changed "MAX10 BMC Secure Engine driver"
GA and BMC images that are stored in FLASH. The driver can
>> also be used to update root entry hashes and to cancel code
>> signing keys.
>>
>> This patch creates the class driver and provides sysfs
>> interfaces for displaying root entry hashes, canceled code
On 10/5/20 5:05 PM, Russ Weight wrote:
>
> On 10/5/20 12:38 AM, Wu, Hao wrote:
>>> Subject: [PATCH v2 1/7] fpga: sec-mgr: intel fpga security manager class
>>> driver
>>>
>>> Create the Intel Security Manager class driver. The security
>>> m
On 10/5/20 1:19 AM, Wu, Hao wrote:
>> -Original Message-
>> From: Russ Weight
>> Sent: Saturday, October 3, 2020 6:37 AM
>> To: m...@kernel.org; linux-f...@vger.kernel.org; linux-
>> ker...@vger.kernel.org
>> Cc: t...@redhat.com; lgonc...@redhat.c
of an ongoing secure
>> update. Sysfs_notify() is used to signal transitions
>> between different phases of the update process.
>>
>> Signed-off-by: Russ Weight
>> ---
>> v2:
>> - Bumped documentation date and version
>> - Changed progress state "re
On 10/5/20 1:55 AM, Wu, Hao wrote:
>> Subject: [PATCH v2 4/7] fpga: sec-mgr: expose sec-mgr update errors
>>
>> Extend Intel Security Manager class driver to include
>> an update/error sysfs node that can be read for error
>> information when a secure update fa
Read-only. Returns a string describing the
current
as it will be signaled by sysfs_notify() on each
state change.
+What: /sys/class/ifpga_sec_mgr/ifpga_secX/update/remaining_size
+Date: Oct 2020
+KernelVersion: 5.11
+Contact: Russ Weight
+D
Extend the Intel Security Manager class driver to
include an update/status sysfs node that can be polled
and read to monitor the progress of an ongoing secure
update. Sysfs_notify() is used to signal transitions
between different phases of the update process.
Signed-off-by: Russ Weight
Reviewed
.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v3:
- No change
v2:
- Bumped documentation date and version
- Minor code cleanup per review comments
---
.../ABI/testing/sysfs-class-ifpga-sec-mgr | 10
drivers/fpga/ifpga-sec-mgr.c | 59
Extend Intel Security Manager class driver to include
an update/error sysfs node that can be read for error
information when a secure update fails.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v3:
- Use dev_err() for invalid error code in sec_error()
v2:
- Bumped documentation date
feature. This data is treated as
opaque by the class driver. It is left to user-space software
or support personnel to interpret this data.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v3:
- No change
v2:
- Bumped documentation date and version
---
.../ABI/testing/sysfs-class-ifpga-sec
ount & smbus_flash_count (not supported)
- Removed typedefs for imgr ops
- Removed explicit value assignments in enums
- Other minor code cleanup per review comments
Russ Weight (7):
fpga: sec-mgr: intel fpga security manager class driver
fpga: sec-mgr: enable secure updates
fpga: sec-mg
provides sysfs
interfaces for displaying root entry hashes, canceled code
signing keys and flash counts.
Signed-off-by: Russ Weight
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v3:
- Modified sysfs handler check in check_sysfs_handler() to make
it more readable.
---
v2:
- Bumped
entry to cause a secure update to occur.
The write of the filename will return immediately, and the
update will begin in the context of a kernel worker thread.
This tool utilizes the request_firmware framework, which
requires that the image file reside under /lib/firmware.
Signed-off-by: Russ Weight
On 9/16/20 1:16 PM, Moritz Fischer wrote:
> Hi Russ,
>
> On Fri, Sep 04, 2020 at 04:52:54PM -0700, Russ Weight wrote:
>> Create the Intel Security Manager class driver. The security
>> manager provides interfaces to manage secure updates for the
>> FPGA and BMC imag
Hi Moritz,
On 9/16/20 1:33 PM, Moritz Fischer wrote:
> Russ,
>
> On Fri, Sep 04, 2020 at 04:52:55PM -0700, Russ Weight wrote:
>> Create a platform driver that can be invoked as a sub
>> driver for the Intel MAX10 BMC in order to support
>> secure updates. Thi
On 9/5/20 10:16 AM, Tom Rix wrote:
> resending.
> sorry for blowing past 80 chars.
>
> On 9/4/20 4:52 PM, Russ Weight wrote:
>> These patches depend on the patchset: "add regmap-spi-avmm & Intel
>> Max10 BMC chip support" which is currently under review.
Hi Moritz,
On 9/30/20 5:31 PM, Moritz Fischer wrote:
> I think providing the devm_ managed APIs is nicer, and makes it easier
> for the consumer of the API to do the right thing.
I see that the fpga_mgr code has support for two versions of the create()
and register() functions, one uses the dev
class driver not just some internal code in max10 driver? This class
> driver will be reused in different cases? And why adding a new class
> driver not just reuse or extend fpga manager (existing fpga mgr is used
> to update fpga too).
Yes - I'll so that in the next patch set.
plicit value assignments in enums
- Other minor code cleanup per review comments
Russ Weight (7):
fpga: sec-mgr: intel fpga security manager class driver
fpga: sec-mgr: enable secure updates
fpga: sec-mgr: expose sec-mgr update status
fpga: sec-mgr: expose sec-mgr update errors
fp
s a string describing the
current
as it will be signaled by sysfs_notify() on each
state change.
+What: /sys/class/ifpga_sec_mgr/ifpga_secX/update/remaining_size
+Date: Oct 2020
+KernelVersion: 5.11
+Contact: Russ Weight
+Description: Read-onl
feature. This data is treated as
opaque by the class driver. It is left to user-space software
or support personnel to interpret this data.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v2:
- Bumped documentation date and version
---
.../ABI/testing/sysfs-class-ifpga-sec-mgr | 14
Extend the Intel Security Manager class driver to
include an update/status sysfs node that can be polled
and read to monitor the progress of an ongoing secure
update. Sysfs_notify() is used to signal transitions
between different phases of the update process.
Signed-off-by: Russ Weight
---
v2
provides sysfs
interfaces for displaying root entry hashes, canceled code
signing keys and flash counts.
Signed-off-by: Russ Weight
Signed-off-by: Xu Yilun
---
v2:
- Bumped documentation dates and versions
- Added Documentation/fpga/ifpga-sec-mgr.rst
- Removed references to bmc_flash_count
.
Signed-off-by: Russ Weight
---
v2:
- Bumped documentation date and version
- Minor code cleanup per review comments
---
.../ABI/testing/sysfs-class-ifpga-sec-mgr | 10
drivers/fpga/ifpga-sec-mgr.c | 59 +--
include/linux/fpga/ifpga-sec-mgr.h
Extend Intel Security Manager class driver to include
an update/error sysfs node that can be read for error
information when a secure update fails.
Signed-off-by: Russ Weight
---
v2:
- Bumped documentation date and version
- Added warning to sec_progress() for invalid progress status
entry to cause a secure update to occur.
The write of the filename will return immediately, and the
update will begin in the context of a kernel worker thread.
This tool utilizes the request_firmware framework, which
requires that the image file reside under /lib/firmware.
Signed-off-by: Russ Weight
Hi Moritz,
This patch aligns with FPGA Manager implementation as you requested by
splitting up the create() and register() functions and adding a devm_
version of the create() function. I have a question (below) regarding the
device_add() function call.
On 10/2/20 3:36 PM, Russ Weight wrote
onding bits are set to 1 if we are unable
to read the doorbell or auth_result registers.
- Added comments and additional code cleanup per V1 review.
Russ Weight (6):
mfd: intel-m10-bmc: support for MAX10 BMC Security Engine
fpga: m10bmc-sec: create max10 bmc security engine
fpga: m10bmc
Extend the MAX10 BMC Security Engine driver to provide a
handler to expose the flash update count for the FPGA user
image in sysfs.
Signed-off-by: Russ Weight
---
v2:
- Renamed get_qspi_flash_count() to m10bmc_user_flash_count()
- Minor code cleanup per review comments
- Added m10bmc_
Add macros and definitions required by the MAX10 BMC
Security Engine driver.
Signed-off-by: Russ Weight
---
v2:
- These functions and macros were previously distributed among
the patches that needed them. They are now grouped together
in a single patch containing changes to the Intel
Extend the MAX10 BMC Security Engine driver to provide a
handler to expose the canceled code signing key (CSK) bit
vectors in sysfs. These use the standard bitmap list format
(e.g. 1,2-6,9).
Signed-off-by: Russ Weight
---
v2:
- Replaced small function-creation macros for explicit function
Extend the MAX10 BMC Security Engine driver to include
the functions that enable secure updates of BMC images,
FPGA images, etc.
Signed-off-by: Russ Weight
---
v2:
- Reworked the rsu_start_done() function to make it more readable
- Reworked while-loop condition/content in rsu_prog_ready
Extend the MAX10 BMC Security Engine driver to include
a function that returns 64 bits of additional HW specific
data for errors that require additional information.
This callback function enables the hw_errinfo sysfs
node in the Intel Security Manager class driver.
Signed-off-by: Russ Weight
and BMC images.
This patch creates the MAX10 BMC Security Engine driver and
provides support for displaying the current root entry hashes
for the FPGA static region, the FPGA PR region, and the MAX10
BMC.
Signed-off-by: Russ Weight
---
v2:
- Added drivers/fpga/intel-m10-bmc-secure.c file to
On 10/2/20 8:15 PM, Randy Dunlap wrote:
> On 10/2/20 6:24 PM, Russ Weight wrote:
>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
>> index c534cc80f398..2380d36b08c7 100644
>> --- a/drivers/fpga/Kconfig
>> +++ b/drivers/fpga/Kconfig
>> @@ -235,
On 10/7/20 7:44 AM, Moritz Fischer wrote:
> Hi Russ,
>
> On Tue, Oct 06, 2020 at 05:09:58PM -0700, Russ Weight wrote:
>> Create the Intel Security Manager class driver. The security
>> manager provides interfaces to manage secure updates for the
>> FPGA and BMC imag
On 10/7/20 10:06 AM, Moritz Fischer wrote:
> On Wed, Oct 07, 2020 at 09:43:24AM -0700, Russ Weight wrote:
>>
>> On 10/7/20 7:44 AM, Moritz Fischer wrote:
>>> Hi Russ,
>>>
>>> On Tue, Oct 06, 2020 at 05:09:58PM -0700, Russ Weight wrote:
>>>&g
- Removed references to bmc_flash_count & smbus_flash_count (not supported)
- Removed typedefs for imgr ops
- Removed explicit value assignments in enums
- Other minor code cleanup per review comments
Russ Weight (7):
fpga: sec-mgr: intel fpga security manager class driver
fpga: sec
Extend the FPGA Security Manager class driver to
include an update/status sysfs node that can be polled
and read to monitor the progress of an ongoing secure
update. Sysfs_notify() is used to signal transitions
between different phases of the update process.
Signed-off-by: Russ Weight
Reviewed
Extend the FPGA Security Manager class driver to include
an update/error sysfs node that can be read for error
information when a secure update fails.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v4:
- Changed from "Intel FPGA Security Manager" to FPGA Security Manager"
provides sysfs
interfaces for displaying root entry hashes, canceled code
signing keys and flash counts.
Signed-off-by: Russ Weight
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v4:
- Changed from "Intel FPGA Security Manager" to FPGA Security Manager"
and removed unneces
.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v4:
- Changed from "Intel FPGA Security Manager" to FPGA Security Manager"
and removed unnecessary references to "Intel".
- Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga
cause a secure update to occur.
The write of the filename will return immediately, and the
update will begin in the context of a kernel worker thread.
This tool utilizes the request_firmware framework, which
requires that the image file reside under /lib/firmware.
Signed-off-by: Russ Weight
) on each
state change.
+What: /sys/class/fpga_sec_mgr/fpga_secX/update/remaining_size
+Date: Oct 2020
+KernelVersion: 5.11
+Contact: Russ Weight
+Description: Read-only. Returns the size of data that remains to
+ be written to the secure update
feature. This data is treated as
opaque by the class driver. It is left to user-space software
or support personnel to interpret this data.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v4:
- Changed from "Intel FPGA Security Manager" to FPGA Security Manager"
and remo
On 10/7/20 12:00 AM, Lee Jones wrote:
> On Fri, 02 Oct 2020, Russ Weight wrote:
>
>> Add macros and definitions required by the MAX10 BMC
>> Security Engine driver.
>>
>> Signed-off-by: Russ Weight
>> ---
>> v2:
>> - These functions and mac
On 10/6/20 9:34 AM, Tom Rix wrote:
> On 10/2/20 6:24 PM, Russ Weight wrote:
>> Add macros and definitions required by the MAX10 BMC
>> Security Engine driver.
>>
>> Signed-off-by: Russ Weight
>> ---
>> v2:
>> - These functions and macros were pr
On 10/6/20 10:31 AM, Tom Rix wrote:
> On 10/2/20 6:24 PM, Russ Weight wrote:
>> Create a platform driver that can be invoked as a sub
>> driver for the Intel MAX10 BMC in order to support
>> secure updates. This sub-driver will invoke an
>> instance of the Intel
I just realized that I missed a few questions on my first reply.
Please see my responses below.
On 10/7/20 5:52 PM, Russ Weight wrote:
>
> On 10/6/20 9:34 AM, Tom Rix wrote:
>> On 10/2/20 6:24 PM, Russ Weight wrote:
>>> Add macros and definitions required by the MAX10 BM
On 10/6/20 12:08 PM, Tom Rix wrote:
> On 10/2/20 6:24 PM, Russ Weight wrote:
>> Extend the MAX10 BMC Security Engine driver to include
>> the functions that enable secure updates of BMC images,
>> FPGA images, etc.
>>
>> Signed-off-by: Russ Weight
images.
This patch creates the MAX10 BMC Secure Update driver and
provides support for displaying the current root entry hashes
for the FPGA static region, the FPGA PR region, and the MAX10
BMC.
Signed-off-by: Russ Weight
---
v3:
- Changed from "Intel FPGA Security Manager" to FPG
Extend the MAX10 BMC Secure Update driver to include
a function that returns 64 bits of additional HW specific
data for errors that require additional information.
This callback function enables the hw_errinfo sysfs
node in the Intel Security Manager class driver.
Signed-off-by: Russ Weight
Extend the MAX10 BMC Secure Update driver to provide a
handler to expose the canceled code signing key (CSK) bit
vectors in sysfs. These use the standard bitmap list format
(e.g. 1,2-6,9).
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v3:
- Changed: iops -> sops, imgr -> smgr,
Extend the MAX10 BMC Secure Update driver to include
the functions that enable secure updates of BMC images,
FPGA images, etc.
Signed-off-by: Russ Weight
---
v3:
- Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_
- Changed "MAX10 BMC Secure Engine driver&
Extend the MAX10 BMC Secure Update driver to provide a
handler to expose the flash update count for the FPGA user
image in sysfs.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v3:
- Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_
- Changed "MA
ix for the get_csk_vector() function to properly apply the
stride variable in calls to m10bmc_raw_bulk_read().
- Added m10bmc_ prefix to functions in m10bmc_iops structure
- Implemented HW_ERRINFO_POISON for m10bmc_sec_hw_errinfo() to
ensure that corresponding bits are set to 1 if we are u
Add macros and definitions required by the MAX10 BMC
Secure Update driver.
Signed-off-by: Russ Weight
---
v3:
- Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure
Update driver"
- Removed wrapper functions (m10bmc_raw_*, m10bmc_sys_*). The
underlyi
Minor comment below.
- Russ
On 5/29/20 6:15 AM, Richard Gong wrote:
Hi Moritz,
Sorry for asking.
When you get chance, can you review my version 2 patch submitted on
05/15/20?
Regards,
Richard
On 5/15/20 9:35 AM, richard.g...@linux.intel.com wrote:
From: Richard Gong
The reconfiguration
secure update and for
retrieving error information in the event of a failure.
The n3000bmc-secure driver instantiates the Intel Security Manager
class driver and provides the callback functions required to support
secure updates on Intel n3000 PAC devices.
Russ Weight (12):
fpga: fpga security
and BMC images.
This patch creates the MAX10 BMC Security Engine driver and
provides support for displaying the current root entry hashes
for the FPGA static region, the FPGA PR region, and the MAX10
BMC.
Signed-off-by: Russ Weight
Reviewed-by: Wu Hao
---
drivers/fpga/Kconfig| 11
entry to cause a secure update to occur.
The write of the filename will return immediately, and the
update will begin in the context of a kernel worker thread.
This tool utilizes the request_firmware framework, which
requires that the image file reside under /lib/firmware.
Signed-off-by: Russ Weight
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