Hi Max, Sergei,
Thanks for your work on this.
> Add support for HPB-DMAC found in Renesas R-Car SoCs, using 'shdma-base'
DMA
> driver framework.
>
> Based on the original patch by Phil Edworthy
.
>
> Signed-off-by: Max Filippov
> [Sergei: removed useless #in
Hi Bjorn,
Thanks for the review.
On 16 October 2015 22:34, Bjorn wrote:
> On Fri, Oct 02, 2015 at 11:25:05AM +0100, Phil Edworthy wrote:
> > The R-Car PCIe host controller driver uses pci_common_init_dev(),
> > which is ARM-specific and requires the ARM struct hw_p
Hi Geert,
On 20 October 2015 08:37, Geert wrote:
> On Tue, Oct 20, 2015 at 3:36 AM, Simon Horman wrote:
> > On Mon, Oct 19, 2015 at 06:16:34PM -0500, Bjorn Helgaas wrote:
> >> [+cc Geert]
> >>
> >> On Fri, Oct 02, 2015 at 11:25:03AM +0100, Phil Edworthy wr
Hi Bjorn,
On 20 October 2015 13:50, Bjorn wrote:
> On Tue, Oct 20, 2015 at 08:00:10AM +0000, Phil Edworthy wrote:
> > Hi Geert,
> >
> > On 20 October 2015 08:37, Geert wrote:
> > > On Tue, Oct 20, 2015 at 3:36 AM, Simon Horman
> wrote:
> > > > On
re
related.
Phil Edworthy (4):
PCI: rcar-pcie: Make PCI aware of the IO resources
PCI: rcar-pcie: Remove dependency on ARM-specific struct hw_pci
PCI: rcar-pcie: Set root bus nr to that provided in DT
PCI: rcar-pcie: Fix IO offset for multiple instances
drivers/pci/host/pcie-r
Signed-off-by: Phil Edworthy
---
drivers/pci/host/pcie-rcar.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index 7678fe0..27e2c20 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
is based on commit <499733e0cc1a00523c5056a690f65dea7b9da140>
"PCI: generic: Remove dependency on ARM-specific struct hw_pci".
Signed-off-by: Phil Edworthy
---
drivers/pci/host/pcie-rcar.c | 76
1 file changed, 48 insertions(+), 28 de
On ARM64, setting the root bus number to -1 causes probe failure.
Moreover, we should use the bus number specified in the DT as we
could have multiple PCIe controllers with different bus ranges.
Signed-off-by: Phil Edworthy
---
drivers/pci/host/pcie-rcar.c | 2 +-
1 file changed, 1 insertion
Signed-off-by: Phil Edworthy
---
drivers/pci/host/pcie-rcar.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index 8e583c2..f4fa6c5 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie
Hi Andy,
On 29 August 2018 18:11 Andy Shevchenko wrote:
> On Tue, Jul 31, 2018 at 01:10:59PM +0100, Phil Edworthy wrote:
> > Quite a few drivers get an optional clock, e.g. a clock required
> > to access peripheral's registers that is always enabled on some
> > devi
Hi Stephen,
On 25 July 2018 23:37, Stephen Boyd wrote:
> Quoting Phil Edworthy (2018-07-18 06:56:26)
> > On 18 July 2018 14:19, Geert Uytterhoeven wrote:
> > > On Wed, Jul 18, 2018 at 3:02 PM Russell King - ARM Linux wrote:
> > > > On Wed, Jul 18, 2018 at 01:57:3
Quite a few drivers get an optional clock, e.g. a clock required
to access peripheral's registers that is always enabled on some
devices.
Phil Edworthy (2):
clk: Add of_clk_get_by_name_optional() function
clk: Add functions to get optional clocks
drivers/clk/clk-devres.c
: Phil Edworthy
---
drivers/clk/clk-devres.c | 18 --
drivers/clk/clkdev.c | 17 +++--
include/linux/clk.h | 29 +
3 files changed, 60 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c
r and allows clk_prepare_enable, etc to be called
on the returned reference without additional checks.
Signed-off-by: Phil Edworthy
---
drivers/clk/clkdev.c | 34 ++
include/linux/clk.h | 1 +
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/driver
Hi Geert,
On 30 July 2018 09:56, Geert Uytterhoeven wrote:
> On Mon, Jul 30, 2018 at 10:36 AM Phil Edworthy wrote:
> > Quite a few drivers get an optional clock, e.g. a clock required to
> > access peripheral's registers that is always enabled on some devices.
> >
>
Quite a few drivers get an optional clock, e.g. a clock required
to access peripheral's registers that is always enabled on some
devices.
This function behaves the same as of_clk_get_by_name() except that
it will return NULL instead of -EINVAL.
Signed-off-by: Phil Edworthy
---
v3:
- Fix
Quite a few drivers get an optional clock, e.g. a bus clock required to
access peripheral's registers that is always enabled on some devices.
Phil Edworthy (2):
clk: Add of_clk_get_by_name_optional() function
clk: Add functions to get optional clocks
drivers/clk/clk-devres.c
: Phil Edworthy
---
v3:
- No changes.
---
drivers/clk/clk-devres.c | 18 --
drivers/clk/clkdev.c | 17 +++--
include/linux/clk.h | 29 +
3 files changed, 60 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-devres.c b
Hi Andy,
On 30 July 2018 17:04, Andy Shevchenko wrote:
> On Mon, 2018-07-30 at 14:31 +0100, Phil Edworthy wrote:
> > Quite a few drivers get an optional clock, e.g. a clock required to
> > access peripheral's registers that is always enabled on some devices.
> >
> >
Hi Geert,
On 20 July 2018 13:12, Geert Uytterhoeven wrote:
> On Fri, Jul 20, 2018 at 2:06 PM Phil Edworthy wrote:
> > On 20 July 2018 12:21, Geert Uytterhoeven wrote:
> > > On Wed, Jul 18, 2018 at 4:34 PM Phil Edworthy wrote:
> > > > To avoid all SoC peripheral
Quite a few drivers get an optional clock, e.g. a bus clock required to
access peripheral's registers that is always enabled on some devices.
Phil Edworthy (2):
clk: Add of_clk_get_by_name_optional() function
clk: Add functions to get optional clocks
drivers/clk/clk-devres.c
Quite a few drivers get an optional clock, e.g. a clock required
to access peripheral's registers that is always enabled on some
devices.
This function behaves the same as of_clk_get_by_name() except that
it will return NULL instead of -ENOENT.
Signed-off-by: Phil Edworthy
---
v4:
: Phil Edworthy
---
v4:
- No changes.
v3:
- No changes.
---
drivers/clk/clk-devres.c | 18 --
drivers/clk/clkdev.c | 17 +++--
include/linux/clk.h | 29 +
3 files changed, 60 insertions(+), 4 deletions(-)
diff --git a/drivers/clk
Enable an optional bus clock provided by DT.
Signed-off-by: Phil Edworthy
---
v2:
- Fix include order.
- Use a clock name.
- Check errors from clk_prepare_enable()
- Add calls to enable/disable the clock in PM
---
drivers/gpio/gpio-dwapb.c | 20 +++-
1 file changed, 19
Hi Shawn,
On 28 February 2018 01:53, Shawn Lin wrote:
> On 2018/2/27 23:05, Phil Edworthy wrote:
> > On 27 February 2018 14:42, Shawn Lin wrote:
> >> On 2018/2/27 22:31, Phil Edworthy wrote:
> >>> On 27 February 2018 14:28, Shawn Lin wrote:
> >>
Hi Geert,
On 06 April 2018 10:57 Geert Uytterhoeven wrote:
> On Thu, Apr 5, 2018 at 11:42 AM, Phil Edworthy wrote:
> > On 30 March 2018 22:26 Andy Shevchenko wrote:
> >> On Wed, Mar 28, 2018 at 5:22 PM, Phil Edworthy wrote:
> >> > The DesignWare GPIO IP can be
Hi Andy,
On 05 April 2018 10:43, Phil Edworthy wrote:
> On 30 March 2018 22:26 Andy Shevchenko wrote:
> > On Wed, Mar 28, 2018 at 5:22 PM, Phil Edworthy wrote:
> > > The DesignWare GPIO IP can be configured for either 1 or 32
> > > interrupts,
> >
> > 1 to 3
s, it will
get as many interrupts as specified in the DT 'interrupts' property.
It doesn't do anything clever with the different interrupts, it just calls
the same handler used for single interrupt hardware.
Signed-off-by: Phil Edworthy
---
v2:
- Replaced interrupt-mask DT
interrupts-extended DT prop.
However, I have no use for this and had to hack some test case for this.
Perhaps the driver should support 1 interrupt or all GPIOa as interrupts?
Phil Edworthy (2):
gpio: dwapb: Add support for 1 interrupt per port A GPIO
mfd: intel_quark_i2c_gpio: Update Syn
Since the way the Synopsys GPIO interrupts are stored has changed, this
driver needs to be updated in line with the changes.
Signed-off-by: Phil Edworthy
---
v2:
- New patch in v2 to fix the only other user of struct dwapb_port_property.
---
drivers/mfd/intel_quark_i2c_gpio.c | 3 ++-
1 file
Hi Geert,
On 13 April 2018 09:20 Geert Uytterhoeven wrote:
> On Fri, Apr 13, 2018 at 10:08 AM, Phil Edworthy wrote:
> > Since the way the Synopsys GPIO interrupts are stored has changed,
> > this driver needs to be updated in line with the changes.
> >
> > S
s, it will
get as many interrupts as specified in the DT 'interrupts' property.
It doesn't do anything clever with the different interrupts, it just calls
the same handler used for single interrupt hardware.
Signed-off-by: Phil Edworthy
---
One point to mention is that I have made
Hi Rob,
On 09 April 2018 20:20 Rob Herring wrote:
> On Wed, Mar 28, 2018 at 03:22:30PM +0100, Phil Edworthy wrote:
> > The DesignWare GPIO IP can be configured for either 1 or 32
> > interrupts, but the driver currently only supports 1 interrupt. See
> > the DesignWare
Hi Rob,
On 10 April 2018 07:24 Phil Edworthy wrote:
> On 09 April 2018 20:20 Rob Herring wrote:
> > On Wed, Mar 28, 2018 at 03:22:30PM +0100, Phil Edworthy wrote:
[...]
> > > +- interrupt-mask : a 32-bit bit mask that specifies which interrupts
> > > +in the list
>
Hi Geert,
On 10 April 2018 15:29 Geert Uytterhoeven wrote:
> On Tue, Apr 10, 2018 at 4:23 PM, Phil Edworthy wrote:
> > On 10 April 2018 07:24 Phil Edworthy wrote:
> >> On 09 April 2018 20:20 Rob Herring wrote:
> >> > On Wed, Mar 28, 2018 at 03:22:3
From: Michel Pollet
Enable specified clocks from DTS, if any.
Signed-off-by: Michel Pollet
---
drivers/gpio/gpio-dwapb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
index b0704a8..56c58b5 100644
--- a/drivers/gpio/gpio-dwapb.c
en tested on the Renesas RZ/ND-DB board with the RZ/N1 SoC. The
Arasan IP in this device is version 1.39a and uses a max SD clock of 50MHz and
does not support DDR modes.
Signed-off-by: Phil Edworthy
---
v2:
- Changed commit msg to detail the cards that fail.
- Provided the IP version and further
Hi Andy,
On 13 March 2018 16:36, Andy Shevchenko wrote:
> On Mon, Mar 12, 2018 at 8:30 PM, Phil Edworthy
> wrote:
> > Enable an optional bus clock provided by DT.
>
> FWIW,
> Reviewed-by: Andy Shevchenko
Thanks!
> (Assuming it has been tested on clock-less cases)
mple.
- Change the way the functions are defined so it is easy to check
against the hardware numbering.
v2:
- Change to generic rzn1 family driver, instead of device specific.
- Review comments fixed.
- Fix error handling during probe
Phil Edworthy (3):
dt-bindings: pinctrl: renes
The Renesas RZ/N1 device family PINCTRL node description.
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy
Reviewed-by: Jacopo Mondi
---
v6:
- Instead of combining the pin nr and func into a single element, use
a pair of 8-bit elements.
v5
This provides a pinctrl driver for the Renesas RZ/N1 device family.
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy
Reviewed-by: Jacopo Mondi
---
v6:
- Instead of combining the pin nr and func into a single element, use
a pair of 8-bit elements
This provides a pinctrl driver for the Renesas R9A06G032 SoC
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy
---
v6:
- No changes.
v5:
- No changes.
v4:
- No changes.
v3:
- No changes.
v2:
- Add "renesas,rzn1-pinctrl" compatibl
Hi Geert,
On 23 November 2018 09:41 Geert Uytterhoeven wrote:
> Subject: Re: [PATCH] pinctrl: rzn1: Fix check for used MDIO bus
> On Mon, Nov 19, 2018 at 5:18 PM Phil Edworthy wrote:
> > This fixes the check for unused mdio bus setting and the following
> > static checker war
interrupt-controller"
Signed-off-by: Phil Edworthy
---
arch/arm/boot/dts/ox820.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi
index 085bbd33eadc..3a17ab4e7c2f 100644
--- a/arch/arm/boot/dts/ox820.dtsi
+++
interrupt-controller"
Signed-off-by: Phil Edworthy
---
arch/arm/boot/dts/alpine.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index 731df7a8c4e6..533c876497ff 100644
--- a/arch/arm/boot/dts/alpine.dtsi
interrupt-controller"
Signed-off-by: Phil Edworthy
---
arch/arm64/boot/dts/al/alpine-v2.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/al/alpine-v2.dtsi
b/arch/arm64/boot/dts/al/alpine-v2.dtsi
index 5b7bef684256..6f35bab10e9d 100644
--- a/arch
Hi Andy,
On 20 November 2018 10:39 Andy Shevchenko wrote:
> On Mon, Nov 19, 2018 at 02:12:59PM +0000, Phil Edworthy wrote:
> > This adds clk_get_optional() and devm_clk_get_optional() functions to
> > get optional clocks.
> > They behave the same as (devm_)clk_get except wh
The sub-nodes should not be called gpio-controller, but simply gpio.
Signed-off-by: Phil Edworthy
---
Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
b
clk_prepare_enable, etc to be called on the returned reference
without additional checks.
Signed-off-by: Phil Edworthy
Reviewed-by: Andy Shevchenko
---
v8:
- Remove else clause
v7:
- Instead of messing with the core functions, simply wrap them for the
_optional() versions. By putting clk_get_optional
Hi Simon,
On 22 November 2018 14:09 Simon Horman wrote:
> On Mon, Nov 19, 2018 at 04:18:38PM +0000, Phil Edworthy wrote:
> > This fixes the check for unused mdio bus setting and the following
> > static checker warning:
> > drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_md
Hi Stephen,
On 30 November 2018 09:09 Stephen Boyd wrote:
> Quoting Phil Edworthy (2018-11-20 06:14:45)
> > This adds clk_get_optional() and devm_clk_get_optional() functions to
> > get optional clocks.
> > They behave the same as (devm_)clk_get except where there is no c
Hi Rob,
On 17 November 2018 14:33 Rob Herring wrote:
> On Tue, Nov 13, 2018 at 01:09:09PM +0000, Phil Edworthy wrote:
> > Add device binding documentation for the Renesas RZ/N1 GPIO interrupt
> > multiplexer.
> >
> > Signed-off-by: Phil Edworthy
> > ---
>
Hi Uwe,
On 16 November 2018 16:11 Uwe Kleine-König wrote:
> On Fri, Nov 16, 2018 at 05:01:28PM +0100, Uwe Kleine-König wrote:
> > Other than that I think the patch is fine
>
> Thinking again, I wonder why not just do:
>
> static inline struct clk *clk_get_optional(struct device *dev, const char
Hi Uwe,
On 19 November 2018 10:46 Uwe Kleine-König wrote:
> On Mon, Nov 19, 2018 at 10:41:42AM +0000, Phil Edworthy wrote:
> > On 16 November 2018 16:11 Uwe Kleine-König wrote:
> > > On Fri, Nov 16, 2018 at 05:01:28PM +0100, Uwe Kleine-König wrote:
> > > > Other
Hi Uwe,
On 19 November 2018 12:58 Uwe Kleine-König wrote:
> On Mon, Nov 19, 2018 at 12:53:46PM +0000, Phil Edworthy wrote:
> > On 19 November 2018 10:46 Uwe Kleine-König wrote:
> > > On Mon, Nov 19, 2018 at 10:41:42AM +0000, Phil Edworthy wrote:
> > &g
clk_prepare_enable, etc to be called on the returned reference
without additional checks.
Signed-off-by: Phil Edworthy
---
v7:
- Instead of messing with the core functions, simply wrap them for the
_optional() versions. By putting clk_get_optional() inline in the header
file, we can get rid of the
ing of_get_child_count()
Reported-by: Dan Carpenter
Signed-off-by: Phil Edworthy
---
v2:
- Don't rely on rely on the implicit typecast from -1 to uint
---
drivers/pinctrl/pinctrl-rzn1.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rzn1.c b/d
Hi Andy,
On 03 December 2018 13:31 Andy Shevchenko wrote:
> On Mon, Dec 03, 2018 at 11:13:08AM +0000, Phil Edworthy wrote:
> > It's not immediately obvious from the code that failure to get a clock
> > provider can return either -ENOENT or -EINVAL. Therefore, add a
> >
clk_prepare_enable, etc to be called on the returned reference
without additional checks.
Signed-off-by: Phil Edworthy
Reviewed-by: Andy Shevchenko
---
v9:
- Add brackets after devm_clk_get so people know it's a function.
- Add kernel doc for clk_get_optional().
v8:
- Remove else clause
v7:
- In
t's a function.
- Add kernel doc for clk_get_optional().
Phil Edworthy (2):
clk: Add comment about __of_clk_get_by_name() error values
clk: Add (devm_)clk_get_optional() functions
drivers/clk/clk-devres.c | 11 +++
drivers/clk/clkdev.c | 6 ++
include/linux/clk.h
It's not immediately obvious from the code that failure to get a
clock provider can return either -ENOENT or -EINVAL. Therefore, add
a comment to highlight this.
Signed-off-by: Phil Edworthy
---
drivers/clk/clkdev.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/clk
r feedback came afterwards.
However, in my haste I managed to drop the changes made to dwapb_port_property
struct. This patch includes those missing changes.
Signed-off-by: Phil Edworthy
---
include/linux/platform_data/gpio-dwapb.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Dan,
On 31 May 2018 07:24 Dan Carpenter wrote:
> Smatch flags a couple bugs here:
>
> drivers/gpio/gpio-dwapb.c:447 dwapb_configure_irqs() warn: always true
> condition '(pp->irq[i] >= 0) => (0-u32max >= 0)'
> drivers/gpio/gpio-dwapb.c:627 dwapb_gpio_get_pdata() warn: always true
> condition '
d, so there is nothing to do in this driver when an interrupt
is received, other than tell the corresponding GPIO block.
Signed-off-by: Phil Edworthy
---
v2:
- Use interrupt-map to allow the GPIO controller info to be specified
as part of the irq.
- Renamed struct and funcs from 'girq&
The driver requires an undocumented clock property, so detail it.
Add documentation for a separate bus clock.
Signed-off-by: Phil Edworthy
---
Documentation/devicetree/bindings/i2c/i2c-designware.txt | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation
The Synopsys I2C Controller has a bus clock, but typically SoCs hide this away.
However, on some SoCs you need to explicity enable the bus clock in order to
access the registers.
Therefore, enable an optional bus clock specified by DT.
Signed-off-by: Phil Edworthy
---
drivers/i2c/busses/i2c
: Phil Edworthy
---
drivers/clk/clk-devres.c | 11 +++
drivers/clk/clkdev.c | 11 +++
include/linux/clk.h | 27 +++
3 files changed, 49 insertions(+)
diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c
index d854e26..63295d9 100644
--- a
Hi Russell,
On 18 July 2018 14:19, Geert Uytterhoeven wrote:
> On Wed, Jul 18, 2018 at 3:02 PM Russell King - ARM Linux wrote:
> > On Wed, Jul 18, 2018 at 01:57:38PM +0100, Phil Edworthy wrote:
> > > Behaves the same as (devm_)clk_get except where there is no clock
> >
These changes allow a PHY driver to trigger a VBUS interrupt and
to provide the value of VBUS.
Signed-off-by: Phil Edworthy
---
drivers/usb/renesas_usbhs/common.h | 2 ++
drivers/usb/renesas_usbhs/mod.c| 3 +++
drivers/usb/renesas_usbhs/mod_gadget.c | 38
.
Note: the R-Car USB PHY only allows this Host/Function switching
on channel 0.
This has been tested on a r8a7791 based Koelsch board, which uses
a MAX3355 device to supply vbus power when needed.
Signed-off-by: Phil Edworthy
---
drivers/phy/phy-rcar-gen2.c | 269
Both USB Host (pci0) and Function (USBHS) drivers are enabled.
The USB PHY driver determines which IP block should be connected
based on vbus and id signals read via gpios.
Signed-off-by: Phil Edworthy
---
arch/arm/boot/dts/r8a7791-koelsch.dts | 7 ---
1 file changed, 4 insertions(+), 3
This patch set adds support for USB Host/Function switching using external
gpios to get the vbus and id signals.
I am aware that the dt binding for the USB phy will need updating, but wanted
to get this patch set out first to see whether this is the best way to
implement this.
Phil
Phil
Hi Linus,
On 23 May 2018 09:29, Linus Walleij wrote:
> On Fri, May 11, 2018 at 10:31 AM, Phil Edworthy wrote:
>
> > The DesignWare GPIO IP can be configured for either 1 interrupt or 1
> > per GPIO in port A, but the driver currently only supports 1 interrupt.
> > See th
t_irq().
Signed-off-by: Phil Edworthy
---
drivers/gpio/gpio-dwapb.c | 53 ---
1 file changed, 22 insertions(+), 31 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
index 7dcd06b..15b4154 100644
--- a/drivers/gpio/gpio-dwapb.c
Hi Simon,
On 23 May 2018 10:12 Simon Horman wrote:
> On Wed, May 23, 2018 at 09:52:44AM +0100, Phil Edworthy wrote:
> > Treat DT and ACPI the same as much as possible. Note that we can't use
> > platform_get_irq() to get the DT interrupts as they are in the port
> > sub-
Hi Andy,
On 30 March 2018 22:26 Andy Shevchenko wrote:
> On Wed, Mar 28, 2018 at 5:22 PM, Phil Edworthy wrote:
> > The DesignWare GPIO IP can be configured for either 1 or 32
> > interrupts,
>
> 1 to 32, or just a choice between two?
Just a choice of 1 or 32.
Note that
et as many interrupts as specified in the DT 'interrupts' property.
It doesn't do anything clever with the different interrupts, it just calls
the same handler used for single interrupt hardware.
Signed-off-by: Phil Edworthy
---
Note: There are a few lines over 80 chars, but thi
Hi,
On 28 March 2018 15:23, Phil Edworthy wrote:
> The DesignWare GPIO IP can be configured for either 1 or 32 interrupts,
> but the driver currently only supports 1 interrupt. See the DesignWare
> DW_apb_gpio Databook description of the 'GPIO_INTR_IO' parameter.
>
&g
s, it will
get as many interrupts as specified in the DT 'interrupts' property.
It doesn't do anything clever with the different interrupts, it just calls
the same handler used for single interrupt hardware.
ACPI companion code provided by Hoan Tran . This was tested
on X-Gene by H
Hi Rob,
On 01 May 2018 14:29 Rob Herring wrote:
> On Mon, Apr 23, 2018 at 02:33:06PM +0100, Phil Edworthy wrote:
> > On RZ/N1 devices, there are 3 Synopsys DesignWare GPIO blocks each
> > configured to have 32 interrupt outputs, so we have a total of 96 GPIO
> > interru
From: Guido Piasenza
The extra entry in the table makes SCIFA0_B, and all peripherals after it, fail.
Signed-off-by: Phil Edworthy
---
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
b/drivers
There is a missing 0 entry from the MOD_SEL3 table.
Signed-off-by: Phil Edworthy
---
drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 56f62dc..a823b5b
Hi,
On 10 September 2014 19:20, Arnd wrote:
> On Tuesday 09 September 2014 12:20:54 Catalin Marinas wrote:
> >
> > We can assume that if a domain is not specified and there is a single
> > top level PCIe node, the domain defaults to 0. Are there any arm32
> > platforms that require multiple domain
Hi Tanmay,
On: 19/03/2014 23:15, Tanmay wrote:
> Subject: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver
> Sent by: linux-pci-ow...@vger.kernel.org
>
> This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
> X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed
Hi Laurent,
On 08 July 2015 00:08, Laurent wrote:
> Hi Phil,
>
> Thank you for the patch.
>
> On Tuesday 07 July 2015 12:52:43 Phil Edworthy wrote:
> > These changes allow a PHY driver to trigger a VBUS interrupt and
> > to provide the value of VBUS.
> >
Hi Geert,
On 11 August 2015 13:43, Geert wrote:
> On arm64/shmobile:
>
> drivers/pci/host/pci-rcar-gen2.c: In function 'rcar_pci_cfg_base':
> drivers/pci/host/pci-rcar-gen2.c:112:34: error: dereferencing pointer to
> incomplete type
> struct rcar_pci_priv *priv = sys->private_data;
>
Hi Marc,
On 11 November 2015 16:38, Marc Zyngier wrote:
> On Tue, 10 Nov 2015 16:52:33 +0100
> Thierry Reding wrote:
>
> > On Mon, Nov 09, 2015 at 06:01:49PM +, Phil Edworthy wrote:
> > > Hi Thierry,
> > >
> > > On 09 November 2015 17:24, Phi
Hi Liviu, Arnd,
On 11 November 2015 18:25, LIviu wrote:
> On Mon, Nov 09, 2015 at 12:32:13PM +0000, Phil Edworthy wrote:
> > Hi Liviu, Will,
> >
> > On 04 November 2015 15:19, Phil wrote:
> > > On 04 November 2015 15:02, Liviu wrote:
> > > > On Wed, Nov 0
Hi Arnd,
On 12 November 2015 09:49, Arnd Bergmann wrote:
> On Thursday 12 November 2015 09:26:33 Phil Edworthy wrote:
> > On 11 November 2015 18:25, LIviu wrote:
> > > On Mon, Nov 09, 2015 at 12:32:13PM +0000, Phil Edworthy wrote:
>
> > > I think you're mixing
Hi Marc,
On 12 November 2015 20:31, Marc Zyngier wrote:
> Phil Edworthy wrote:
> > On 11 November 2015 16:38, Marc Zyngier wrote:
> > > On Tue, 10 Nov 2015 16:52:33 +0100
> > > Thierry Reding wrote:
> > >
> > > > On Mon, Nov 09, 2015 at 06:
Hi Arnd,
On 12 November 2015 16:17, Arnd Bergmann wrote:
> On Thursday 12 November 2015 15:33:41 Phil Edworthy wrote:
> > On 12 November 2015 09:49, Arnd Bergmann wrote:
> > > On Thursday 12 November 2015 09:26:33 Phil Edworthy wrote:
> > > > On 11 November 2015 18
On 13 November 2015 14:00, Arnd Bergmann wrote:
> On Friday 13 November 2015 13:03:11 Phil Edworthy wrote:
> >
> > > > Then pci_device_add() sets the devices coherent_dma_mask to 4GiB
> before
> > > > calling of_pci_dma_configure(). I assume it does this on
file in the comments.
> >
> > Cc: Simon Horman
> > Cc: Bjorn Helgaas
> > Cc: linux-...@vger.kernel.org
> > Cc: linux...@vger.kernel.org
> > Signed-off-by: Paul Gortmaker
It doesn't apply, would you mind rebasing onto:
https://git.kernel.org/cgit/linux/kerne
The first patch removes code that is no longer used. The next two allow us to
use runtim PM. The last patch is for PHY setup in order to get PCIe compliance
apparently. For that last patch, I've been told that this is what I must set.
Phil Edworthy (4):
PCI: rcar: remove unused pci_sys
Commit b3a72384fe29 ("ARM/PCI: Replace pci_sys_data->align_resource
with global function pointer") removed the struct pci_sys_data
dependency from the ARM pcibios functions, so remove it from this
driver.
Signed-off-by: Phil Edworthy
---
drivers/pci/host/pcie-rcar.c | 9
If runtime PM is enabled in the kernel config, simply enable the
clocks once during probe.
Signed-off-by: Phil Edworthy
---
drivers/pci/host/pcie-rcar.c | 44
1 file changed, 32 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/host/pcie
For PCIe compliance, the PHY registers need setting as per the
manual.
Signed-off-by: Phil Edworthy
---
drivers/pci/host/pcie-rcar.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index
as long as it has also been transitioned to L1 link state.
So, when attempting a config access, check to see if the card has gone
into L1, and if so, do the same for the host controller.
This is based on a patch by Hien Dang
Signed-off-by: Phil Edworthy
---
drivers/pci/host/pcie-r
Hi Wolfram,
On 17 December 2015 13:31, Wolfram Sang wrote:
> Hi Phil,
>
> > + /* Wait until we are in L1 */
> > + while (!(val & L1FAEG))
> > + val = rcar_pci_read_reg(pcie, PMSR);
>
> No timeout?
Since the hardware doesn't support hot plug, I believe this l
Hi Wolfram,
On 17 December 2015 13:33, Wolfram Sang wrote:
> > + rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
> > + rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
> > + rcar_pci_write_reg(pcie, 0x0001, GEN2_PCIEPHYCTRL);
> > + rcar_pci_write_reg(pcie, 0x0006, GE
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