Add driver for the Socionext UniPhier Pro5 SoC endpoint controller.
This controller is based on the DesignWare PCIe core.
And add "host" to existing controller descriontions for the host controller
in Kconfig.
Signed-off-by: Kunihiko Hayashi
---
M
Even if phy driver doesn't probe, the error message can't be
distinguished from other errors. This displays error message
caused by the phy driver explicitly.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 4 +++-
1 file changed, 3 insertions(+),
detects PME and AER interrupts with the status register,
and invoke PME and AER drivers related to INTx or MSI.
And this sets the mask for misc interrupts from INTx if MSI is enabled
and sets the mask for misc interrupts from MSI if MSI is disabled.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci
are PCIe framework,
that invokes PME and AER funcions to detect the factor from SoC-dependent
registers.
---
Kunihiko Hayashi (5):
PCI: dwc: Add msi_host_isr() callback
PCI: uniphier: Add misc interrupt handler to invoke PME and AER
dt-bindings: PCI: uniphier: Add iATU register description
This gets iATU register area from reg property. In Synopsis DWC version
4.80 or later, since iATU register area is separated from core register
area, this area is necessary to get from DT independently.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 5 +
1
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsis DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
---
Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/
.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-designware-host.c | 8
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
b/drivers/pci/controller/dwc
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Kunihiko-Hayashi/PCI-uniphier-Add-features-for-UniPhier-PCIe-host-controller/20200
This gets iATU register area from reg property. In Synopsis DWC version
4.80 or later, since iATU register area is separated from core register
area, this area is necessary to get from DT independently.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 7
.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-designware-host.c | 8
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
b/drivers/pci/controller/dwc
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsis DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
---
Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/
detects PME and AER interrupts with the status register,
and invoke PME and AER drivers related to INTx or MSI.
And this sets the mask for misc interrupts from INTx if MSI is enabled
and sets the mask for misc interrupts from MSI if MSI is disabled.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci
are PCIe framework,
that invokes PME and AER funcions to detect the factor from SoC-dependent
registers.
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Kunihiko Hayashi (5):
PCI: dwc: Add msi_host_isr() callback
PCI: uniphier: Add m
Even if phy driver doesn't probe, the error message can't be distinguished
from other errors. This displays error message caused by the phy driver
explicitly.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 7 +--
1 file changed, 5 insertions(+), 2
Hi Rob,
On 2020/09/04 7:12, Rob Herring wrote:
On Fri, Aug 21, 2020 at 1:05 AM Kunihiko Hayashi
wrote:
On 2020/08/18 1:48, Rob Herring wrote:
On Fri, Aug 7, 2020 at 4:25 AM Kunihiko Hayashi
wrote:
This gets iATU register area from reg property. In Synopsys DWC version
4.80 or later
Hi Rob,
On 2020/09/04 7:25, Rob Herring wrote:
On Fri, Aug 21, 2020 at 1:05 AM Kunihiko Hayashi
wrote:
On 2020/08/18 1:39, Rob Herring wrote:
On Fri, Aug 7, 2020 at 4:25 AM Kunihiko Hayashi
wrote:
Even if phy driver doesn't probe, the error message can't be distinguished
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
2 files changed
stavo Pimentel
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-uniphier.c | 77 +-
1 file changed, 66 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
b/driver
d printing phy error message in case of EPROBE_DEFER
- Fix iATU register mapping method
- dt-bindings: Add Acked-by: line
- Fix typos in commit messages
- Use devm_platform_ioremap_resource_byname()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
inline int init_new_context(struct task_struct *tsk,
| ^~~~
Cc: Nicholas Piggin
Fixes: 4c792ad103f3 ("arm64: use asm-generic/mmu_context.h for no-op
implementations")
Signed-off-by: Kunihiko Hayashi
---
arch/arm64/include/asm/mmu_context.h | 1
On 2020/08/18 1:39, Rob Herring wrote:
On Fri, Aug 7, 2020 at 4:25 AM Kunihiko Hayashi
wrote:
Even if phy driver doesn't probe, the error message can't be distinguished
from other errors. This displays error message caused by the phy driver
explicitly.
Signed-off-by: Kunihi
On 2020/08/18 1:48, Rob Herring wrote:
On Fri, Aug 7, 2020 at 4:25 AM Kunihiko Hayashi
wrote:
This gets iATU register area from reg property. In Synopsys DWC version
4.80 or later, since iATU register area is separated from core register
area, this area is necessary to get from DT
On 2020/08/01 4:38, John Stultz wrote:
On Fri, Jul 31, 2020 at 2:32 AM Kunihiko Hayashi
wrote:
On 2020/07/29 4:17, John Stultz wrote:
Do you have a upstream driver that you plan to make use this new call?
Unfortunately I don't have an upstream driver using this call.
This call is c
Gentle ping.
Are there any comments in this series?
Thank you,
On 2020/07/16 17:32, Kunihiko Hayashi wrote:
This series adds support for AHCI PHY interface implemented in Socionext
UniPhier SoCs. This driver supports PXs2 and PXs3 SoCs.
Changes since v3:
- Eliminate a meaningless blank line
ebase to pci/dwc and resend this series without 6/6?
Thank you,
On 2020/06/18 17:38, Kunihiko Hayashi wrote:
Use devm_platform_ioremap_resource_byname() to simplify the code a bit.
Signed-off-by: Kunihiko Hayashi f
---
drivers/pci/controller/dwc/pcie-uniphier.c | 3 +--
1 file changed, 1 inse
Hi Lorenzo,
On 2020/07/14 22:27, Lorenzo Pieralisi wrote:
On Thu, Jun 18, 2020 at 05:38:09PM +0900, Kunihiko Hayashi wrote:
The misc interrupts consisting of PME, AER, and Link event, is handled
by INTx handler, however, these interrupts should be also handled by
MSI handler.
Define what you
Add a driver for PHY interface built into ahci controller implemented
in UniPhier SoCs. This supports PXs2 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi
---
drivers/phy/socionext/Kconfig | 10 +
drivers/phy/socionext/Makefile| 1 +
drivers/phy/socionext/phy-uniphier
Add DT bindings for PHY interface built into ahci controller implemented
in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
.../bindings/phy/socionext,uniphier-ahci-phy.yaml | 76 ++
1 file changed, 76 insertions(+)
create mode 100644
- Fix return value in uniphier_ahciphy_init
- dt-bindings: Add Reviewed-by line
Changes since v1:
- dt-bindings: Fix items in reset-names
Kunihiko Hayashi (2):
dt-bindings: phy: Add UniPhier AHCI PHY description
phy: socionext: Add UniPhier AHCI PHY driver support
.../bindings/phy/socionext
Hi Vinod,
On 2020/07/16 15:37, Vinod Koul wrote:
On 16-07-20, 11:43, Kunihiko Hayashi wrote:
+static int uniphier_ahciphy_pxs3_init(struct uniphier_ahciphy_priv *priv)
+{
+ int i;
+ u32 val;
+
+ /* setup port parameter */
+ val = readl(priv->base + TXCT
Add DT bindings for PHY interface built into ahci controller implemented
in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
.../bindings/phy/socionext,uniphier-ahci-phy.yaml | 76 ++
1 file changed, 76 insertions(+)
create mode 100644
Add a driver for PHY interface built into ahci controller implemented
in UniPhier SoCs. This supports PXs2 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi
---
drivers/phy/socionext/Kconfig | 10 +
drivers/phy/socionext/Makefile| 1 +
drivers/phy/socionext/phy-uniphier
controller
- Remove redundant .init in uniphier_pxs2_data
- Add comments for dummy read accesses
- Fix return value in uniphier_ahciphy_init
- dt-bindings: Add Reviewed-by line
Changes since v1:
- dt-bindings: Fix items in reset-names
Kunihiko Hayashi (2):
dt-bindings: phy: Add UniPhier AHCI PHY
ociated with the CMA become available as dma-buf heaps.
Signed-off-by: Kunihiko Hayashi
---
drivers/dma-buf/heaps/cma_heap.c | 12
include/linux/dma-heap.h | 9 +
2 files changed, 21 insertions(+)
diff --git a/drivers/dma-buf/heaps/cma_heap.c b/drivers/dma-buf/he
nmode_mask, priv->pinmode_val);
if (ret)
- return ret;
+ goto out_reset_assert;
ave_global_reset(ndev);
Thank you for pointing out.
Reviewed-by: Kunihiko Hayashi
---
Best Regards
Kunihiko Hayashi
Suggested-by: Rob Herring
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-designware.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pci/controller/dwc/pcie-designware.c
index 4d105ef..4a36
After applying "PCI: dwc: Add common iATU register support",
there is no need to set own iATU in the Keystone driver itself.
Cc: Murali Karicheri
Cc: Jingoo Han
Cc: Gustavo Pimentel
Suggested-by: Rob Herring
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pci-keyst
;iatu" property description to the dt-bindings
for UniPhier PCIe host controller.
This has been confirmed with PCIe version 4.80 controller on UniPhier platform.
Please test this series on Keystone platform.
Kunihiko Hayashi (3):
dt-bindings: PCI: uniphier: Add iATU register description
PCI:
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsys DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
1 file changed, 1 insertion(+)
di
stavo Pimentel
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 77 +-
1 file changed, 66 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
b/drivers/pci/controller/dwc/pcie-uniph
method
- dt-bindings: Add Acked-by: line
- Fix typos in commit messages
- Use devm_platform_ioremap_resource_byname()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Kunihiko Hayashi (3):
PCI: portdrv: Add pcie_port_service_get_irq() func
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
2 files changed, 17 insertions(+)
diff
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff
Hi Marc,
On 2020/06/30 22:23, Marc Zyngier wrote:
On 2020-06-29 10:49, Kunihiko Hayashi wrote:
Hi Marc,
On 2020/06/27 18:48, Marc Zyngier wrote:
On Thu, 18 Jun 2020 09:38:09 +0100,
Kunihiko Hayashi wrote:
The misc interrupts consisting of PME, AER, and Link event, is handled
by INTx
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/pci
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 57 --
1 file changed, 46 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
b/drivers/pci/controller/dwc/pcie-uniphier.c
index a5401a0..5ce2479 100644
This gets iATU register area from reg property. In Synopsys DWC version
4.80 or later, since iATU register area is separated from core register
area, this area is necessary to get from DT independently.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 5 +
1
mit messages
- Use devm_platform_ioremap_resource_byname()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Kunihiko Hayashi (6):
PCI: dwc: Add msi_host_isr() callback
PCI: uniphier: Add misc interrupt handler to invoke PME and AER
Use devm_platform_ioremap_resource_byname() to simplify the code a bit.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
b/drivers/pci/controller/dwc
Even if phy driver doesn't probe, the error message can't be distinguished
from other errors. This displays error message caused by the phy driver
explicitly.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 8 ++--
1 file changed, 6 insert
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsys DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
1 file changed, 1 insertion(+)
di
Hi Marc,
On 2020/06/27 18:48, Marc Zyngier wrote:
On Thu, 18 Jun 2020 09:38:09 +0100,
Kunihiko Hayashi wrote:
The misc interrupts consisting of PME, AER, and Link event, is handled
by INTx handler, however, these interrupts should be also handled by
MSI handler.
This adds the function
Hi Rob,
On 2020/05/12 11:01, Rob Herring wrote:
On Tue, Apr 28, 2020 at 03:31:22PM +0900, Kunihiko Hayashi wrote:
Convert the UniPhier AVE4 controller binding to DT schema format.
This changes phy-handle property to required.
Signed-off-by: Kunihiko Hayashi
---
(snip)
+ phy-mode
Convert the UniPhier AVE4 controller binding to DT schema format.
Signed-off-by: Kunihiko Hayashi
---
Changes since v1:
- Set true to phy-mode and phy-handle instead of $ref
- Add mac-address and local-mac-address for existing dts warning
.../bindings/net/socionext,uniphier-ave4.txt
Convert UniPhier watchdog timer binding to DT schema format.
Cc: Keiji Hayashibara
Signed-off-by: Kunihiko Hayashi
---
.../bindings/watchdog/socionext,uniphier-wdt.yaml | 36 ++
.../devicetree/bindings/watchdog/uniphier-wdt.txt | 20
2 files changed, 36
Hi Rob,
Thank you for your comment.
On 2020/05/08 4:33, Rob Herring wrote:
On Mon, Mar 23, 2020 at 06:40:54PM +0900, Kunihiko Hayashi wrote:
Add driver for the Socionext UniPhier Pro5 SoC endpoint controller.
This controller is based on the DesignWare PCIe core.
Signed-off-by: Kunihiko
On 2020/03/23 18:40, Kunihiko Hayashi wrote:
Add DT bindings for PCIe controller implemented in UniPhier SoCs
when configured in endpoint mode. This controller is based on
the DesignWare PCIe core.
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci
Hi David, Rob,
On 2020/05/02 7:21, David Miller wrote:
From: Kunihiko Hayashi
Date: Tue, 28 Apr 2020 15:31:22 +0900
Convert the UniPhier AVE4 controller binding to DT schema format.
This changes phy-handle property to required.
Signed-off-by: Kunihiko Hayashi
DT folks, is it ok if I take
Hi Gustavo,
On 2020/05/15 22:16, Gustavo Pimentel wrote:
Hi Kunihiko,
On Fri, May 15, 2020 at 10:59:2, Kunihiko Hayashi
wrote:
This gets iATU register area from reg property. In Synopsis DWC version
s/Synopsis/Synopsys
in all patches
Thank you for pointing out.
I'll fix and be ca
Add devicetree binding documentation for thermal monitor implemented on
Socionext UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
.../bindings/thermal/uniphier-thermal.txt | 64 ++
1 file changed, 64 insertions(+)
create mode 100644
Add a thermal driver for on-chip PVT (Process, Voltage and Temperature)
monitoring unit implemented on UniPhier SoCs. This driver supports
temperature monitoring and alert function.
Signed-off-by: Kunihiko Hayashi
---
drivers/thermal/Kconfig| 8 +
drivers/thermal/Makefile
pt handler
- add dependency to Kconfig
- set 120C to CRITICAL_TEMP_LIMIT as maximum temperature
- shrink each line of parameters to save the number of lines
- improve some comments and copyright description
Kunihiko Hayashi (2):
dt-bindings: thermal: add binding documentation for UniPhier thermal
Add nodes of thermal monitor and thermal zone for UniPhier PXs2 SoC.
The thermal monitor is included in sysctrl.
Furthermore, add cpuN labels for reference in cooling-device property.
Signed-off-by: Kunihiko Hayashi
---
arch/arm/boot/dts/uniphier-pxs2.dtsi | 43
Add nodes of thermal monitor and thermal zone for UniPhier LD20 SoC.
The thermal monitor is included in sysctrl.
Signed-off-by: Kunihiko Hayashi
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts
rature for LD20 according to the spec sheet
- add cpuN labels for reference in cooling-device property on PXs2 dts
[1] https://lkml.org/lkml/2017/6/28/170
Kunihiko Hayashi (2):
ARM: dts: uniphier: add nodes of thermal monitor and thermal zone for
PXs2
arm64: dts: uniphier: add nodes of ther
Add initial device tree support for LD20 Global board.
Signed-off-by: Kunihiko Hayashi
---
arch/arm64/boot/dts/socionext/Makefile | 1 +
.../boot/dts/socionext/uniphier-ld20-global.dts| 87 ++
2 files changed, 88 insertions(+)
create mode 100644 arch/arm64
Add initial device tree support for LD11 Global board.
Signed-off-by: Kunihiko Hayashi
---
arch/arm64/boot/dts/socionext/Makefile | 1 +
.../boot/dts/socionext/uniphier-ld11-global.dts| 105 +
2 files changed, 106 insertions(+)
create mode 100644 arch
Initial version of device tree for LD20/11 Global boards.
Kunihiko Hayashi (2):
arm64: dts: uniphier: add support for LD11 Global board
arm64: dts: uniphier: add support for LD20 Global board
arch/arm64/boot/dts/socionext/Makefile | 2 +
.../boot/dts/socionext/uniphier-ld11
copyright description
Kunihiko Hayashi (2):
dt-bindings: thermal: add binding documentation for UniPhier thermal
monitor
thermal: uniphier: add UniPhier thermal driver
.../bindings/thermal/uniphier-thermal.txt | 64
drivers/thermal/Kconfig| 8
Add devicetree binding documentation for thermal monitor implemented on
Socionext UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
.../bindings/thermal/uniphier-thermal.txt | 64 ++
1 file changed, 64 insertions(+)
create mode 100644
Add a thermal driver for on-chip PVT (Process, Voltage and Temperature)
monitoring unit implemented on UniPhier SoCs. This driver supports
temperature monitoring and alert function.
Signed-off-by: Kunihiko Hayashi
---
drivers/thermal/Kconfig| 8 +
drivers/thermal/Makefile
-triggered' according to
hardware specification
- bring up threshold temperature for LD20 according to the spec sheet
- add cpuN labels for reference in cooling-device property on PXs2 dts
[1] https://lkml.org/lkml/2017/6/28/170
Kunihiko Hayashi (2):
ARM: dts: uniphier: add nodes of ther
Add nodes of thermal monitor and thermal zone for UniPhier PXs2 SoC.
The thermal monitor is included in sysctrl.
Furthermore, add cpuN labels for reference in cooling-device property.
Signed-off-by: Kunihiko Hayashi
---
arch/arm/boot/dts/uniphier-pxs2.dtsi | 43
Add nodes of thermal monitor and thermal zone for UniPhier LD20 SoC.
The thermal monitor is included in sysctrl.
Furthermore, since the reference board doesn't have a calibrated value of
thermal monitor, this patch gives the default value for LD20 reference
board.
Signed-off-by: Kunihiko Ha
On Wed, 5 Jul 2017 21:27:57 +0900 wrote:
> 2017-07-05 21:20 GMT+09:00 Masahiro Yamada :
> > 2017-07-05 20:50 GMT+09:00 Kunihiko Hayashi
> > :
> >
> >> +
> >> +#define TMOD 0x0928
> >> +#define TMOD_MASK
Add a thermal driver for on-chip PVT (Process, Voltage and Temperature)
monitoring unit implemented on UniPhier SoCs. This driver supports
temperature monitoring and alert function.
Signed-off-by: Kunihiko Hayashi
---
drivers/thermal/Kconfig| 8 +
drivers/thermal/Makefile
Add devicetree binding documentation for thermal monitor implemented on
Socionext UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
.../bindings/thermal/uniphier-thermal.txt | 64 ++
1 file changed, 64 insertions(+)
create mode 100644
e
- shrink each line of parameters to save the number of lines
- improve some comments and copyright description
Kunihiko Hayashi (2):
dt-bindings: thermal: add binding documentation for UniPhier thermal
monitor
thermal: uniphier: add UniPhier thermal driver
.../bindings/thermal/uniphier-t
On Fri, 21 Jul 2017 02:09:18 +0900 wrote:
> 2017-07-21 1:53 GMT+09:00 Masahiro Yamada :
> > 2017-07-21 1:08 GMT+09:00 Masahiro Yamada :
> >> 2017-07-07 10:54 GMT+09:00 Kunihiko Hayashi
> >> :
> >>> Add a thermal driver for on-chip PVT (Process, Voltage
Add devicetree binding documentation for thermal monitor implemented on
Socionext UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
.../bindings/thermal/uniphier-thermal.txt | 64 ++
1 file changed, 64 insertions(+)
create mode 100644
endency to Kconfig
- set 120C to CRITICAL_TEMP_LIMIT as maximum temperature
- shrink each line of parameters to save the number of lines
- improve some comments and copyright description
Kunihiko Hayashi (2):
dt-bindings: thermal: add binding documentation for UniPhier thermal
monitor
thermal
Add a thermal driver for on-chip PVT (Process, Voltage and Temperature)
monitoring unit implemented on UniPhier SoCs. This driver supports
temperature monitoring and alert function.
Signed-off-by: Kunihiko Hayashi
---
drivers/thermal/Kconfig| 8 +
drivers/thermal/Makefile
Hi Bartlomiej, Rob, Mark,
On Thu, 1 Feb 2018 16:56:08 +0100 wrote:
>
> Hi,
>
> On Tuesday, January 23, 2018 08:34:56 PM Kunihiko Hayashi wrote:
> > Enables 'memory-region' property referring to the memory description on
> > the reserved-memory node in case of
Hi Andy,
On Thu, 1 Feb 2018 21:03:30 +0200 wrote:
> On Thu, Feb 1, 2018 at 5:56 PM, Bartlomiej Zolnierkiewicz
> wrote:
> > On Tuesday, January 23, 2018 08:34:56 PM Kunihiko Hayashi wrote:
> >> Enables 'memory-region' property referring to the memory description o
Hi Rob,
On Mon, 5 Feb 2018 00:09:14 -0600 wrote:
> On Thu, Feb 01, 2018 at 04:56:08PM +0100, Bartlomiej Zolnierkiewicz wrote:
> >
> > Hi,
> >
> > On Tuesday, January 23, 2018 08:34:56 PM Kunihiko Hayashi wrote:
> > > Enables 'memory-region' p
The UniPhier platform from Socionext provides the AVE ethernet
controller that includes MAC and MDIO bus supporting RGMII/RMII
modes. The controller is named AVE.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Jassi Brar
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/Kconfig
initions, and remove unused codes
Kunihiko Hayashi (2):
dt-bindings: net: add DT bindings for Socionext UniPhier AVE
net: ethernet: socionext: add AVE ethernet driver
.../bindings/net/socionext,uniphier-ave4.txt | 45 +
drivers/net/ethernet/Kconfig |1
DT bindings for the AVE ethernet controller found on Socionext's
UniPhier platforms.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Jassi Brar
Acked-by: Rob Herring
---
.../bindings/net/socionext,uniphier-ave4.txt | 45 ++
1 file changed, 45 insertions(+)
c
; > + mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + ethphy: ethphy@1 {
> > + reg = <1>;
> > + };
> > + };
> > + };
>
> Andrew
Thank you,
---
Best Regards,
Kunihiko Hayashi
Hi Andrew,
On Fri, 1 Dec 2017 14:49:00 +0100 Andrew Lunn wrote:
> On Fri, Dec 01, 2017 at 10:03:50AM +0900, Kunihiko Hayashi wrote:
> > The UniPhier platform from Socionext provides the AVE ethernet
> > controller that includes MAC and MDIO bus supporting RGMII/RMII
> > mod
The efuse on UniPhier allows 8bit access according to the specification.
Since bit offset of nvmem is limited to 0-7, it is desiable to change
access unit of nvmem to 8bit.
Signed-off-by: Kunihiko Hayashi
---
drivers/nvmem/uniphier-efuse.c | 10 +-
1 file changed, 5 insertions(+), 5
ase_addr,irq} with the members of ave_private
- rename goto labels and mask definitions, and remove unused codes
Kunihiko Hayashi (2):
dt-bindings: net: add DT bindings for Socionext UniPhier AVE
net: ethernet: socionext: add AVE ethernet driver
.../bindings/net/socionext,uniphier-ave4.txt
The UniPhier platform from Socionext provides the AVE ethernet
controller that includes MAC and MDIO bus supporting RGMII/RMII
modes. The controller is named AVE.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Jassi Brar
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/Kconfig
DT bindings for the AVE ethernet controller found on Socionext's
UniPhier platforms.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Jassi Brar
Acked-by: Rob Herring
---
.../bindings/net/socionext,uniphier-ave4.txt | 48 ++
1 file changed, 48 insertions(+)
c
Hello Florian,
On Thu, 14 Dec 2017 15:24:17 -0800 wrote:
>
>
> On 12/14/2017 02:05 AM, Kunihiko Hayashi wrote:
> > DT bindings for the AVE ethernet controller found on Socionext's
> > UniPhier platforms.
> >
> > Signed-off-by: Kunihiko Hayashi
> >
DT bindings for the AVE ethernet controller found on Socionext's
UniPhier platforms.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Jassi Brar
Acked-by: Rob Herring
---
.../bindings/net/socionext,uniphier-ave4.txt | 47 ++
1 file changed, 47 insertions(+)
c
The UniPhier platform from Socionext provides the AVE ethernet
controller that includes MAC and MDIO bus supporting RGMII/RMII
modes. The controller is named AVE.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Jassi Brar
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/Kconfig
e members of ave_private
- rename goto labels and mask definitions, and remove unused codes
Kunihiko Hayashi (2):
dt-bindings: net: add DT bindings for Socionext UniPhier AVE
net: ethernet: socionext: add AVE ethernet driver
.../bindings/net/socionext,uniphier-ave4.txt | 4
ave_{get,set}_wol()
- remove netif_carrier functions, phydev initializer, and Tx budget check
- change obsolate codes
- replace ndev->{base_addr,irq} with the members of ave_private
- rename goto labels and mask definitions, and remove unused codes
Kunihiko Hayashi (2):
dt-bindings: net: add DT bi
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