Add DT bindings for reset control of USB3 core implemented in UniPhier SoCs.
The reset control belongs to USB3 glue layer.
Signed-off-by: Kunihiko Hayashi
---
.../devicetree/bindings/reset/uniphier-reset.txt | 56 ++
1 file changed, 56 insertions(+)
diff --git a
ld20 and pxs3
- put reset_simple_data into uniphier_usb3_reset_priv
- replace clk operations with clk_bulk
- move nclks and nrsts to soc_data
- rewrite a header with C++ comment style
- change the subject 'USB3 controller reset' to 'USB3 core reset'
Kunihiko Hayashi (2):
dt-bindin
++ comment style
- reuse soc_data for pxs2, ld20 and pxs3
- replace clk operations with clk_bulk
- move nclks and nrsts to soc_data
Kunihiko Hayashi (2):
dt-bindings: regulator: add DT bindings for UniPhier regulator
regulator: uniphier: add regulator driver for UniPhier SoC
.../bindings
Initial commit to add support for regulators implemented in UniPhier SoCs.
This supports USB VBUS only.
Signed-off-by: Kunihiko Hayashi
---
drivers/regulator/Kconfig | 8 ++
drivers/regulator/Makefile | 1 +
drivers/regulator/uniphier-regulator.c | 247
Add DT bindings for regulators implemented in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
---
.../bindings/regulator/uniphier-regulator.txt | 57 ++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/uniphier
Hi Mark,
On Tue, 10 Jul 2018 18:44:51 +0100 wrote:
> On Tue, Jul 10, 2018 at 10:27:17AM +0900, Kunihiko Hayashi wrote:
>
> > +static int uniphier_regulator_enable(struct regulator_dev *rdev)
> > +{
> > + struct uniphier_regulator_priv *priv = rdev_get_drvdata(rde
Initial commit to add support for regulators implemented in UniPhier SoCs.
This supports USB VBUS only.
Signed-off-by: Kunihiko Hayashi
---
drivers/regulator/Kconfig | 8 ++
drivers/regulator/Makefile | 1 +
drivers/regulator/uniphier-regulator.c | 213
- replace read/write accesses with regmap_mmio
- rewrite a header with C++ comment style
- reuse soc_data for pxs2, ld20 and pxs3
- replace clk operations with clk_bulk
- move nclks and nrsts to soc_data
Kunihiko Hayashi (2):
dt-bindings: regulator: add DT bindings for UniPhier regulator
Add DT bindings for regulators implemented in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
---
.../bindings/regulator/uniphier-regulator.txt | 57 ++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/uniphier
On Mon, 9 Jul 2018 20:23:19 +0900 wrote:
> Hi Kishon,
> Thank you for your comments.
>
> On Mon, 9 Jul 2018 10:49:50 +0530 wrote:
>
> > Hi,
> >
> > On Friday 29 June 2018 02:08 PM, Kunihiko Hayashi wrote:
> > > Add a driver for PHY interface built
Add DT bindings for reset control of USB3 controller implemented in
UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
---
.../devicetree/bindings/reset/uniphier-reset.txt | 45 ++
1 file changed, 45 insertions(+)
diff --git a/Documentation/devicetree/bindings/reset/uniphier
This series add new USB3 reset control support for UniPhier SoCs.
This reset lines is included in USB3 glue layer.
Kunihiko Hayashi (2):
dt-bindings: reset: uniphier: add USB3 controller reset support
reset: uniphier: add USB3 controller reset control
.../devicetree/bindings/reset/uniphier
clocks and deassert resets of the layer before using this
reset lines.
Signed-off-by: Kunihiko Hayashi
---
drivers/reset/Kconfig | 10 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-uniphier-usb3.c | 183
3 files changed, 194
This series add new regulator controller support for UniPhier SoCs.
Currently this supports USB3 VBUS controller only.
This USB3 VBUS is included in USB3 glue layer.
Kunihiko Hayashi (2):
dt-bindings: regulator: add DT bindings for UniPhier regulator
regulator: uniphier: add regulator driver
Add DT bindings for regulators implemented in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
---
.../bindings/regulator/uniphier-regulator.txt | 54 ++
1 file changed, 54 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/uniphier
Initial commit to add support for regulators implemented in UniPhier SoCs.
This supports USB VBUS only.
Signed-off-by: Kunihiko Hayashi
---
drivers/regulator/Kconfig | 8 ++
drivers/regulator/Makefile | 1 +
drivers/regulator/uniphier-regulator.c | 251
.
Kunihiko Hayashi (4):
dt-bindings: phy: add DT bindings for UniPhier USB3 PHY driver
phy: socionext: add USB3 PHY driver for UniPhier SoC
dt-bindings: phy: add DT bindings for UniPhier USB2 PHY driver
phy: socionext: add USB2 PHY driver for UniPhier SoC
.../devicetree/bindings/phy/uniphier-usb2
Add DT bindings for PHY interface built into USB2 controller
implemented on Socionext UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
---
.../devicetree/bindings/phy/uniphier-usb2-phy.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree
Add DT bindings for PHY interface built into USB3 controller
implemented in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
---
.../devicetree/bindings/phy/uniphier-usb3-phy.txt | 118 +
1 file changed, 118 insertions(+)
create mode 100644 Documentation/devicetree/bindings
Add a driver for PHY interface built into USB2 controller implemented on
UniPhier SoCs. This driver supports HS-PHY for Pro4 and LD11.
Signed-off-by: Kunihiko Hayashi
---
drivers/phy/socionext/Kconfig | 13 ++
drivers/phy/socionext/Makefile| 1 +
drivers/phy/socionext
Add a driver for PHY interface built into USB3 controller
implemented in UniPhier SoCs.
This driver supports High-Speed PHY and Super-Speed PHY.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Motoya Tanigawa
Signed-off-by: Masami Hiramatsu
---
drivers/phy/Kconfig | 1
Hi Philipp,
Thank you for your comments.
On Fri, 29 Jun 2018 11:55:24 +0200 wrote:
> Hi Kunihiko,
>
> thank you for the patch. I just have a few small comments below:
>
> On Fri, 2018-06-29 at 17:11 +0900, Kunihiko Hayashi wrote:
> > Add reset lines for USB3 controller im
Hi Rob,
On Tue, 3 Jul 2018 17:37:47 -0600 wrote:
> On Fri, Jun 29, 2018 at 05:11:30PM +0900, Kunihiko Hayashi wrote:
> > Add DT bindings for reset control of USB3 controller implemented in
> > UniPhier SoCs.
> >
> > Signed-off-by: Kunihiko Hayashi
> > ---
&
Allow reset_simple_ops to be referred from modules that use reset-simple
framework by adding EXPORT_SYMBOL_GPL.
Suggested-by: Masahiro Yamada
Signed-off-by: Kunihiko Hayashi
---
drivers/reset/reset-simple.c | 1 +
1 file changed, 1 insertion(+)
This patch is due to the building issue as
'd be glad if I could hear something about this issue from you.
Thank you,
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi#n348
---
Best Regards,
Kunihiko Hayashi
> > [1 ]
> > On Thu, Dec 13, 2018 at 04:24:28PM +, Mark Brown wrote:
> > > On Thu, Dec 13, 2018 at 07:39:45PM +0900, Kunihiko Hayashi wrote:
> > >
> > > > Maybe I think that we'd better add 'reg' properties to each port,
> > >
Hi Heiner,
On Mon, 17 Dec 2018 19:43:31 +0100 wrote:
> On 17.12.2018 19:41, Heiner Kallweit wrote:
> > On 17.12.2018 07:41, Kunihiko Hayashi wrote:
> >> Hi,
> >>
> >> Gentle ping...
> >> Are there any comments about changes since v2?
> >>
&
Hi Heiner,
On Tue, 18 Dec 2018 07:44:33 +0100 wrote:
> On 18.12.2018 07:25, Kunihiko Hayashi wrote:
> > Hi Heiner,
> >
> > On Mon, 17 Dec 2018 19:43:31 +0100 wrote:
> >
> >> On 17.12.2018 19:41, Heiner Kallweit wrote:
> >>> On 17.
tate has been preserved.
This patch fixes the issue by calling phy_start_machine() in
mdio_bus_phy_restore() in the same way as mdio_bus_phy_resume().
Suggested-by: Heiner Kallweit
Signed-off-by: Kunihiko Hayashi
---
drivers/net/phy/phy_device.c | 7 ++-
1 file changed, 2 insertions(+), 5 d
Hi Heiner,
On Tue, 18 Dec 2018 19:15:39 +0100 wrote:
> On 18.12.2018 08:57, Kunihiko Hayashi wrote:
> > Even though the link is down before entering hibernation,
> > there is an issue that the network interface always links up after resuming
> > from hibernation.
> >
tate has been preserved.
This patch fixes the issue by calling phy_start_machine() in
mdio_bus_phy_restore() in the same way as mdio_bus_phy_resume().
Fixes: bc87922ff59d ("phy: Move PHY PM operations into phy_device")
Suggested-by: Heiner Kallweit
Signed-off-by: Kunihiko Hayashi
--
>
> This patch adds a new convenient function to check whether the PHY is in
> a started state, and expects to solve the issue by changing phydev->state
> to PHY_UP and calling phy_start_machine() only when the PHY is started.
>
> Suggested-by: Heiner Kallweit
> Signed-of
This converts license boilerplate to SPDX identifier, and removes
unnecessary lines.
Reviewed-by: Daniel Lezcano
Signed-off-by: Kunihiko Hayashi
---
drivers/thermal/uniphier_thermal.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
Changes since v1:
- Add Reviewd-by line
.xlate function
Changes since v1:
- follow capitalization conventions in the descriptions
- use C style comments except for the SPDX line
Kunihiko Hayashi (2):
dt-bindings: PCI: Add UniPhier PCIe host controller description
PCI: uniphier: Add UniPhier PCIe host controller support
.../devicetr
This introduces specific glue layer for UniPhier platform to support
PCIe host controller that is based on the DesignWare PCIe core, and
this driver supports Root Complex (host) mode.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/Kconfig | 9 +
drivers/pci/controller
Add DT bindings for PCIe controller implemented in UniPhier SoCs when
configured in Root Complex (host) mode. This controller is based on
the DesignWare PCIe core.
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/uniphier-pcie.txt | 81
and
> this driver supports Root Complex (host) mode.
>
> Signed-off-by: Kunihiko Hayashi
> ---
> drivers/pci/controller/dwc/Kconfig | 9 +
> drivers/pci/controller/dwc/Makefile| 1 +
> drivers/pci/controller/dwc/pcie-uniphier.c | 432
> ++
.xlate function
Changes since v1:
- follow capitalization conventions in the descriptions
- use C style comments except for the SPDX line
Kunihiko Hayashi (2):
dt-bindings: PCI: Add UniPhier PCIe host controller description
PCI: uniphier: Add UniPhier PCIe host controller support
.../devicetr
Add DT bindings for PCIe controller implemented in UniPhier SoCs when
configured in Root Complex (host) mode. This controller is based on
the DesignWare PCIe core.
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/uniphier-pcie.txt | 81
This introduces specific glue layer for UniPhier platform to support
PCIe host controller that is based on the DesignWare PCIe core, and
this driver supports Root Complex (host) mode.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/Kconfig | 9 +
drivers/pci/controller
16PM +0100, Marc Zyngier wrote:
> > >> On 28/09/18 12:06, Lorenzo Pieralisi wrote:
> > >>> [+Murali, Marc]
> > >>>
> > >>> On Thu, Sep 27, 2018 at 04:44:26PM +0900, Kunihiko Hayashi wrote:
> > >>>> Hi Lorenzo, Gustavo,
>
The driver uses devm_ioremap_resource() which is only available when
CONFIG_HAS_IOMEM is set, so the driver depends on this option.
Signed-off-by: Kunihiko Hayashi
---
drivers/phy/socionext/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/socionext
Hi Rob,
Thank you for your comments.
On Mon, 16 Jul 2018 14:50:49 -0600 wrote:
> On Fri, Jun 29, 2018 at 05:38:58PM +0900, Kunihiko Hayashi wrote:
> > Add DT bindings for PHY interface built into USB3 controller
> > implemented in UniPhier SoCs.
> >
> > Sign
Hi Kishon,
On Fri, 13 Jul 2018 12:45:06 +0530 wrote:
> Hi,
>
> On Wednesday 11 July 2018 05:35 PM, Kunihiko Hayashi wrote:
> > On Mon, 9 Jul 2018 20:23:19 +0900 wrote:
> >
> >> Hi Kishon,
> >> Thank you for your comments.
> >>
> >>
Hi Thierry,
On Thu, 5 Apr 2018 11:54:29 +0200
Thierry Reding wrote:
> On Fri, Mar 23, 2018 at 10:30:53AM +0900, Kunihiko Hayashi wrote:
> > Add support to get and control a list of resets for the device
> > as optional and shared. These resets must be kept de-asserted until
&g
Hello Tejun,
On Tue, 27 Mar 2018 07:00:39 -0700
Tejun Heo wrote:
> On Tue, Mar 27, 2018 at 04:04:12PM +0900, Kunihiko Hayashi wrote:
> > Sorry, please ignore this patch because of adding unneed lines.
> > I'll resend it.
>
> Already applied. Can you please send a
On Wed, 28 Mar 2018 10:16:24 +0900
Kunihiko Hayashi wrote:
> there are no delta between v1 and v2 in the content. No problem to apply it!
Nitpick, no delta between "PATCH v2" and "RESEND PATCH v2".
Thanks,
---
Best Regards,
Kunihiko Hayashi
ng 'netdev_tx_t' in this driver too.
>
> Signed-off-by: Luc Van Oostenryck
Thanks for fixing.
I think it's preferable to add 'Fixes'.
Fixes: 4c270b55a5af ("net: ethernet: socionext: add AVE ethernet driver")
Acked-by: Kunihiko Hayashi
Thank you,
&
,
[1]
https://patchwork.kernel.org/project/linux-pci/patch/20210125044803.4310-1-zhiqiang@nxp.com/
On 2021/01/21 0:20, Rob Herring wrote:
On Mon, Jan 18, 2021 at 5:10 PM Kunihiko Hayashi
wrote:
The commit 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows") gets
the values of pci-
Hi Kishon,
Thank you for your comment.
On 2021/01/28 23:29, Kishon Vijay Abraham I wrote:
Hi Kunihiko,
On 24/01/21 8:39 pm, Kunihiko Hayashi wrote:
Set the polling function and call the init function to enable EPC restart
management. The polling function detects that the bus-reset signal is a
Hi Kishon,
On 2021/01/28 23:11, Kishon Vijay Abraham I wrote:
Hi Kunihiko,
On 24/01/21 8:39 pm, Kunihiko Hayashi wrote:
This adds a member 'started' as a boolean value to struct pci_epc to set
whether the controller is started, and also adds a function to get the
value.
Sig
Hi John,
Thank you for your comment.
On 2020/07/29 4:17, John Stultz wrote:
On Thu, Jul 16, 2020 at 6:10 PM Kunihiko Hayashi
wrote:
Current dma-buf heaps can handle only default CMA. This introduces
dma_heap_add_cma() function to attach CMA heaps that belongs to a device.
At first, the
On 2020/07/15 19:04, Kunihiko Hayashi wrote:
Hi Lorenzo,
On 2020/07/14 22:27, Lorenzo Pieralisi wrote:
On Thu, Jun 18, 2020 at 05:38:09PM +0900, Kunihiko Hayashi wrote:
The misc interrupts consisting of PME, AER, and Link event, is handled
by INTx handler, however, these interrupts should be
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsys DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
1 file changed, 1 insertion(+)
di
Even if phy driver doesn't probe, the error message can't be distinguished
from other errors. This displays error message caused by the phy driver
explicitly.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 8 ++--
1 file changed, 6 insert
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/pci
Use devm_platform_ioremap_resource_byname()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Kunihiko Hayashi (6):
PCI: portdrv: Add pcie_port_service_get_irq() function
PCI: dwc: Add msi_host_isr() callback
PCI: uniphier: Add misc interrupt handler to inv
stavo Pimentel
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 77 +-
1 file changed, 66 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
b/drivers/pci/controller/dwc/pcie-uniph
This gets iATU register area from reg property. In Synopsys DWC version
4.80 or later, since iATU register area is separated from core register
area, this area is necessary to get from DT independently.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 5 +
1
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
2 files changed, 17 insertions(+)
diff
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
Acked-by: Bjorn Helgaas
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
OBE_DEFER
- Fix iATU register mapping method
- dt-bindings: Add Acked-by: line
- Fix typos in commit messages
- Use devm_platform_ioremap_resource_byname()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Kunihiko Hayashi (3):
vices associated
with Root Port, and returns its vIRQ number.
Cc: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-uniphier.c | 101 +
1 file change
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff
hould be referenced after they are set by
dw_pcie_iatu_detect_regions*() called from dw_pcie_setup().
Cc: Rob Herring
Fixes: 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows")
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 41
On Tue, 2 Mar 2021 15:20:08 -0500
Konrad Rzeszutek Wilk wrote:
> On 3/2/21 12:21 PM, Kunihiko Hayashi wrote:
> > After the refactoring phase, the type of max_slot has changed from unsigned
> > long to unsigned int. The return type of the function get_max_slots() and
> > the
Hi Jonathan,
On 2021/04/12 17:42, Jonathan Cameron wrote:
On Sat, 10 Apr 2021 01:22:16 +0900
Kunihiko Hayashi wrote:
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Trivial comment inline.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko
()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Kunihiko Hayashi (3):
PCI: portdrv: Add pcie_port_service_get_irq() function
PCI: dwc: Add msi_host_isr() callback
PCI: uniphier: Add misc interrupt handler to invoke PME and AER
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
Acked-by: Bjorn Helgaas
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
vices associated
with Root Port, and returns its vIRQ number.
Cc: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-uniphier.c | 101 +
1 file change
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff
Gentle Ping.
Are there any comments about these two patches?
Thank you,
On Tue, 9 Mar 2021 09:37:15 +0900
Kunihiko Hayashi wrote:
> After applying the commit bbc4d71d6354
> ("net: phy: realtek: fix rtl8211e rx/tx delay config"), the configuration
> register for TXDLY and RXD
: Christoph Hellwig
Fixes: 567d877f9a7d ("swiotlb: refactor swiotlb_tbl_map_single")
Signed-off-by: Kunihiko Hayashi
---
kernel/dma/swiotlb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index 369e4c3..c10e855 100644
--
anges 'phy-mode' property
to 'rgmii-id' as default.
Signed-off-by: Kunihiko Hayashi
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm
anges 'phy-mode' property
to 'rgmii-id' as default.
Signed-off-by: Kunihiko Hayashi
---
arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi
b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index
etup(struct dw_pcie *pci);
+void dw_pcie_iatu_detect(struct dw_pcie *pci);
static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
{
---
Best Regards
Kunihiko Hayashi
endpoint controller.
This series is only for UniPhier PCIe endpoint controller at this point.
Changes since v1:
- Update the patches to rebase onto the latest tree
Kunihiko Hayashi (3):
PCI: endpoint: Add 'started' to pci_epc to set whether the controller
is started
PCI: end
configuration
paremters are restored to the user's values.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/endpoint/Kconfig | 9 +++
drivers/pci/endpoint/Makefile | 1 +
drivers/pci/endpoint/pci-epc-restart.c | 114 +
include/linux/pci-
This adds a member 'started' as a boolean value to struct pci_epc to set
whether the controller is started, and also adds a function to get the
value.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/endpoint/pci-epc-core.c | 2 ++
include/linux/pci-epc.h | 7 +++
2 fil
Set the polling function and call the init function to enable EPC restart
management. The polling function detects that the bus-reset signal is a
rising edge.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/Kconfig| 1 +
drivers/pci/controller/dwc/pcie-uniphier-ep.c
hoice that your patch move
some of the software perspective initializations into hardware ones.
Ok, I checked your patch fixed this issue on my board with or without
my patch. I'll follow the maintainers for handling my patch.
Tested-by: Kunihiko Hayashi
Thank you,
Thanks
Zhiqiang
Hi Bjorn Lorenzo,
On 2020/11/25 19:23, Lorenzo Pieralisi wrote:
On Tue, Nov 24, 2020 at 05:20:37PM -0600, Bjorn Helgaas wrote:
On Wed, Oct 28, 2020 at 10:31:43AM +0900, Kunihiko Hayashi wrote:
This patch adds misc interrupt handler to detect and invoke PME/AER event.
In UniPhier PCIe
es of window_map. It's necessary to refer
the values after they are set in dw_pcie_setup().
Cc: Rob Herring
Fixes: 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows")
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 41 --
This patch fixes condition whether the specified address ranges
overlap each other.
Fixes: 4b7f48d395a7 ("bus: uniphier-system-bus: add UniPhier System Bus driver")
Signed-off-by: Kunihiko Hayashi
---
drivers/bus/uniphier-system-bus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Pro5 SoC has same scheme of USB3 VBUS as Pro4, so the data for Pro5 is
equivalent to Pro4.
Signed-off-by: Kunihiko Hayashi
---
Documentation/devicetree/bindings/regulator/uniphier-regulator.txt | 5 +++--
drivers/regulator/uniphier-regulator.c | 4
2 files
Pro5 SoC has same scheme of USB3 reset as Pro4, so the data for Pro5 is
equivalent to Pro4.
Signed-off-by: Kunihiko Hayashi
---
Documentation/devicetree/bindings/reset/uniphier-reset.txt | 5 +++--
drivers/reset/reset-uniphier-glue.c| 4
2 files changed, 7
Hi Philipp,
On Tue, 10 Sep 2019 09:48:15 +0200 wrote:
> Hi Kunihiko,
>
> On Tue, 2019-09-10 at 10:55 +0900, Kunihiko Hayashi wrote:
> > Pro5 SoC has same scheme of USB3 reset as Pro4, so the data for Pro5 is
> > equivalent to Pro4.
> >
> > Signed-off-by
The value of 'start' entry is no change whenever writing 0 to configfs.
So the endpoint that stopped once can't restart.
Fixes: d74679911610 ("PCI: endpoint: Introduce configfs entry for configuring
EP functions")
Cc: Kishon Vijay Abraham I
Signed-off-by: Kunihiko
netdev_err() with dev_err() before calling register_netdev().
Signed-off-by: Kunihiko Hayashi
---
drivers/net/ethernet/socionext/sni_ave.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/socionext/sni_ave.c
b/drivers/net/ethernet/socionext/sni_a
enabling clocks.
Fixes: 139a34200233 ("ASoC: uniphier: add support for UniPhier AIO CPU DAI
driver")
Signed-off-by: Kunihiko Hayashi
---
sound/soc/uniphier/aio-cpu.c | 31 +--
sound/soc/uniphier/aio.h | 1 +
2 files changed, 22 insertions(+), 10 deletion
Hi Rob,
On 2020/04/29 1:20, Rob Herring wrote:
On Thu, Apr 16, 2020 at 02:12:15PM +0900, Kunihiko Hayashi wrote:
Convert the UniPhier thermal monitor binding to DT schema format.
Signed-off-by: Kunihiko Hayashi
---
.../thermal/socionext,uniphier-thermal.yaml| 57
Convert the UniPhier thermal monitor binding to DT schema format.
Signed-off-by: Kunihiko Hayashi
---
Changes since v1:
- Add maxItems to "socionext,tmod-calibration" property
- Fix indents in examples
.../thermal/socionext,uniphier-thermal.yaml| 59
..
Need to set the update bit in UNIPHIER_CLK_CPUGEAR_UPD to update
the CPU-gear value.
Fixes: d08f1f0d596c ("clk: uniphier: add CPU-gear change (cpufreq) support")
Cc: linux-sta...@vger.kernel.org
Signed-off-by: Kunihiko Hayashi
---
drivers/clk/uniphier/clk-uniphier-cpugear.c | 2
t;
> + }
Surely this return without asserting resets is wrong. This looks good to me.
Reviewed-by: Kunihiko Hayashi
Thank you,
---
Best Regards,
Kunihiko Hayashi
ator_ops uniphier_regulator_ops = {
> +static const struct regulator_ops uniphier_regulator_ops = {
> .enable = regulator_enable_regmap,
> .disable= regulator_disable_regmap,
> .is_enabled = regulator_is_enabled_regmap,
Reviewed-by: Kunihiko Hayashi
Thank you,
---
Best Regards,
Kunihiko Hayashi
Hi,
This looks good to me.
Reviewed-by: Kunihiko Hayashi
Thanks,
On Sat, 30 Mar 2019 17:11:37 +0800
Chunfeng Yun wrote:
> Use devm_clk_get_optional() to get optional clock
>
> Cc: Kunihiko Hayashi
> Signed-off-by: Chunfeng Yun
> ---
> drivers/phy/socionext/phy-unip
Hello,
On Mon, 29 Jul 2019 22:45:01 +0900 wrote:
> On Tue, Jul 9, 2019 at 7:29 PM Kunihiko Hayashi
> wrote:
> >
> > It depends on the board implementation whether to have each pins of
> > CTS/RTS, and others for modem. So it is necessary to divide current
> > uart
Hello,
On Mon, 29 Jul 2019 22:46:02 +0900 wrote:
> On Tue, Jul 9, 2019 at 7:29 PM Kunihiko Hayashi
> wrote:
> >
> > Pro5 PCIe interface uses the following pins:
> > XPERST, XPEWAKE, XPECLKRQ
> >
> > Signed-off-by: Kunihiko Hayashi
> > ---
>
Hello,
On Mon, 29 Jul 2019 22:44:27 +0900 wrote:
> On Tue, Jul 9, 2019 at 7:29 PM Kunihiko Hayashi
> wrote:
> >
> > This adds support for pinmux settings of aout1b groups. This group includes
> > aout1 signals derived from xirq pins.
> >
>
a different number of pins.
Signed-off-by: Kunihiko Hayashi
---
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 10 +++---
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 10 +++---
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 10 +++---
drivers/pinctrl/uniphier/pinctrl
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