ropped, as they are already applied
- added helper function and updated comment and patch description as
requested by David Vrabel
Juergen Gross (1):
xen: eliminate scalability issues from initial mapping setup
arch/x86/xen/mmu.c | 119 +---
ar
r
being able to boot a Dom0 on a system with more than 512 GB memory.
Signed-off-by: Juergen Gross
Signed-off-by: Jan Beulich
---
arch/x86/xen/mmu.c | 119 +---
arch/x86/xen/setup.c| 65 ++
arch/x86/xen/xen-head.S |
On 09/17/2014 04:59 PM, Juergen Gross wrote:
Direct Xen to place the initial P->M table outside of the initial
mapping, as otherwise the 1G (implementation) / 2G (theoretical)
restriction on the size of the initial mapping limits the amount
of memory a domain can be handed initially.
As
Hi,
any chance to have this in 3.18?
Juergen
On 09/12/2014 12:35 PM, Juergen Gross wrote:
The x86 architecture offers via the PAT (Page Attribute Table) a way to
specify different caching modes in page table entries. The PAT MSR contains
8 entries each specifying one of 6 possible cache modes
is redirected to UC- per the
default setup in __cachemode2pte_tbl[].
Signed-off-by: Toshi Kani
Reviewed-by: Juergen Gross
---
arch/x86/mm/pat.c | 64 +
1 file changed, 49 insertions(+), 15 deletions(-)
diff --git a/arch/x86/mm/pat.c b
also the same as
the BIOS default setup in case the system has PAT but "nopat" boot
option is specified.
As a result of this change, cache aliasing is checked for all cases
including !pat_enabled.
Signed-off-by: Toshi Kani
Reviewed-by: Juergen Gross
---
arch/x86/mm/init.c
On 09/24/2014 03:20 PM, David Vrabel wrote:
On 17/09/14 15:59, Juergen Gross wrote:
Direct Xen to place the initial P->M table outside of the initial
mapping, as otherwise the 1G (implementation) / 2G (theoretical)
restriction on the size of the initial mapping limits the amount
of memor
On 09/24/2014 03:20 PM, David Vrabel wrote:
On 17/09/14 15:59, Juergen Gross wrote:
Direct Xen to place the initial P->M table outside of the initial
mapping, as otherwise the 1G (implementation) / 2G (theoretical)
restriction on the size of the initial mapping limits the amount
of memor
e mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggested by Jan Beulich
Juergen Gross (3):
x86: Make page cache mode a real type
x86: Enable PAT to use cache mode translation tables
Support Xen pv-domains using PAT
arch/x86/include/asm/cacheflush.h | 38
: Juergen Gross
Reviewed-by: Toshi Kani
---
arch/x86/include/asm/cacheflush.h | 38 +
arch/x86/include/asm/fb.h | 6 +-
arch/x86/include/asm/io.h | 2 +-
arch/x86/include/asm/pat.h| 6 +-
arch/x86/include/asm/pgtable.h
With the dynamical mapping between cache modes and pgprot values it is
now possible to use all cache modes via the Xen hypervisor PAT settings
in a pv domain.
All to be done is to read the PAT configuration MSR and set up the
translation tables accordingly.
Signed-off-by: Juergen Gross
Reviewed
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross
Reviewed-by: Toshi Kani
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/include/asm/pgtable_types.h | 4 +++
arch/x86/mm/init.c | 8 ++
arch/x86/mm/mm_internal.h| 2 ++
arch/x86/mm/pat.c
ilure was on purpose. Advertising this feature
is just for tuning purposes, not mandatory.
OTOH it would really be a strange error if this xenbus_printf() fails
but all other operations are working, and signaling an error at the
time when it first shows up is a good thing. So:
Acked-by: Juergen G
callers which check the return value must let
'err' be 0.
And also need change the related comments for xenbus_switch_state().
Signed-off-by: Chen Gang
Acked-by: Juergen Gross
---
drivers/block/xen-blkback/xenbus.c | 9 ++---
drivers/net/xen-netback/xenbus.c | 5 +---
On 09/29/2014 11:31 AM, Chen Gang wrote:
On 9/29/14 16:41, Jan Beulich wrote:
On 29.09.14 at 06:32, wrote:
On 09/26/2014 06:38 PM, Chen Gang wrote:
When failure occurs, after xenbus_dev_error(), need go to fail to let
upper caller know about it.
Signed-off-by: Chen Gang
---
drivers/xen/x
On 09/30/2014 08:32 AM, Chen Gang wrote:
On 9/29/14 21:57, David Vrabel wrote:
On 29/09/14 10:59, Chen Gang wrote:
If no any additional reply within 2 days, I shall send patch v2 for it:
"use dev_warn() instead of xenbus_dev_error() and remove 'fail' code block"
I think this driver is f
The pvscsi frontend driver requires the xenbus frontend driver. Reflect
this in Kconfig.
Signed-off-by: Juergen Gross
---
drivers/scsi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 9130df1..ff62dc1 100644
--- a/drivers/scsi/Kconfig
o use more than 512 GB in a pv
domain, but this would require a reorganization of the p2m tree built
by the kernel at boot time. As this reorganization would affect the
Xen tools and kexec, too, it is not included in this patch set. This
topic can be addressed later.
Juergen Gross (3):
xen: sync so
elfnote.h.
Signed-off-by: Juergen Gross
---
include/xen/interface/elfnote.h | 48 ++-
include/xen/interface/xen.h | 272
2 files changed, 294 insertions(+), 26 deletions(-)
diff --git a/include/xen/interface/elfnote.h b/include/xen/interface
tables of the initial mapping after the copy
without having to care about address invalidation.
Signed-off-by: Juergen Gross
Signed-off-by: Jan Beulich
---
arch/x86/xen/mmu.c | 115 +---
arch/x86/xen/setup.c| 65 +++
ar
Size restrictions native kernels wouldn't have resulted from the initrd
getting mapped into the initial mapping. The kernel doesn't really need
the initrd to be mapped, so use infrastructure available in Xen to avoid
the mapping and hence the restriction.
Signed-off-by: Juergen Gross
On 06/16/2014 01:43 PM, Stefano Stabellini wrote:
On Fri, 13 Jun 2014, Daniel Kiper wrote:
efi_set_rtc_mmss() is never used to set RTC due to bugs found
on many EFI platforms. It is set directly by mach_set_rtc_mmss().
Signed-off-by: Daniel Kiper
---
arch/x86/platform/efi/efi.c |6 ++
On 08/22/2014 12:09 AM, Toshi Kani wrote:
On Tue, 2014-08-19 at 15:25 +0200, jgr...@suse.com wrote:
From: Juergen Gross
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true because
On 08/22/2014 11:32 AM, Jan Beulich wrote:
On 19.08.14 at 15:25, wrote:
@@ -118,8 +167,14 @@ void pat_init(void)
PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
/* Boot CPU check */
- if (!boot_pat_state)
+ if (!boot_pat_state) {
rdmsr
n of Xen special handling regarding cache mode
Changes since RFC:
- renamed functions and variables as suggested by Toshi Kani
- corrected cache mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggested by Jan Beulich
Juergen Gross (3):
x86: Make page cache mode a real type
: Juergen Gross
---
arch/x86/include/asm/cacheflush.h | 38 +
arch/x86/include/asm/fb.h | 6 +-
arch/x86/include/asm/io.h | 2 +-
arch/x86/include/asm/pat.h| 6 +-
arch/x86/include/asm/pgtable.h| 19 ++---
arch/x86
With the dynamical mapping between cache modes and pgprot values it is now
possible to use all cache modes via the Xen hypervisor PAT settings in a
pv domain.
All to be done is to read the PAT configuration MSR and set up the translation
tables accordingly.
Signed-off-by: Juergen Gross
n of Xen special handling regarding cache mode
Changes since RFC:
- renamed functions and variables as suggested by Toshi Kani
- corrected cache mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggested by Jan Beulich
Juergen Gross (3):
x86: Make page cache mode a real type
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/include/asm/pgtable_types.h | 4 +++
arch/x86/mm/init.c | 8 ++
arch/x86/mm/pat.c| 54 ++--
include/linux
On 08/26/2014 12:59 PM, David Vrabel wrote:
On 26/08/14 07:16, Juergen Gross wrote:
With the dynamical mapping between cache modes and pgprot values it is now
possible to use all cache modes via the Xen hypervisor PAT settings in a
pv domain.
All to be done is to read the PAT configuration MSR
On 08/26/2014 09:44 PM, Toshi Kani wrote:
On Tue, 2014-08-26 at 08:16 +0200, Juergen Gross wrote:
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true because there are a lot of
On 08/29/2014 01:21 AM, Toshi Kani wrote:
On Tue, 2014-08-26 at 08:16 +0200, Juergen Gross wrote:
Update the translation tables from cache mode to pgprot values according to
the PAT settings. This enables changing the cache attributes of a PAT index in
just one place without having to change at
re)
- correct build error on non-x86 arch by moving definition of
update_cache_mode_entry() to x86 specific header
Changes since RFC:
- renamed functions and variables as suggested by Toshi Kani
- corrected cache mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggeste
With the dynamical mapping between cache modes and pgprot values it is
now possible to use all cache modes via the Xen hypervisor PAT settings
in a pv domain.
All to be done is to read the PAT configuration MSR and set up the
translation tables accordingly.
Signed-off-by: Juergen Gross
: Juergen Gross
---
arch/x86/include/asm/cacheflush.h | 38 +
arch/x86/include/asm/fb.h | 6 +-
arch/x86/include/asm/io.h | 2 +-
arch/x86/include/asm/pat.h| 6 +-
arch/x86/include/asm/pgtable.h| 19 ++---
arch/x86
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross
Reviewed-by: Toshi Kani
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/include/asm/pgtable_types.h | 4 +++
arch/x86/mm/init.c | 8 ++
arch/x86/mm/mm_internal.h| 2 ++
arch/x86/mm/pat.c
On 09/09/2014 07:24 PM, Toshi Kani wrote:
On Mon, 2014-09-08 at 10:01 +0200, Juergen Gross wrote:
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true because there are a lot of
On 08/20/2014 02:05 PM, One Thousand Gnomes wrote:
The Linux kernel currently supports only 4 different cache modes. The PAT MSR
is set up in a way that the setting of _PAGE_PAT in a pte doesn't matter: the
top 4 entries in the PAT MSR are the same as the 4 lower entries.
This results in the ker
On 08/20/2014 09:26 PM, Toshi Kani wrote:
On Tue, 2014-08-19 at 15:25 +0200, jgr...@suse.com wrote:
From: Juergen Gross
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true because
elfnote.h.
Signed-off-by: Juergen Gross
---
include/xen/interface/elfnote.h | 102 ++-
include/xen/interface/xen.h | 272
2 files changed, 348 insertions(+), 26 deletions(-)
diff --git a/include/xen/interface/elfnote.h b/include/xen/interface
without mapping it and the
initial p2m list can be mapped by Xen to an arbitrary selected virtual
address. The following patches activate those options and thus remove
the limitations.
Juergen Gross (3):
xen: sync some headers with xen tree
xen: eliminate scalability issues from initrd handling
Size restrictions native kernels wouldn't have resulted from the initrd
getting mapped into the initial mapping. The kernel doesn't really need
the initrd to be mapped, so use infrastructure available in Xen to avoid
the mapping and hence the restriction.
Signed-off-by: Juergen Gross
tables of the initial mapping after the copy
without having to care about address invalidation.
Signed-off-by: Juergen Gross
Signed-off-by: Jan Beulich
---
arch/x86/xen/mmu.c | 116 +---
arch/x86/xen/setup.c| 65 +++
ar
On 09/04/2014 04:43 PM, Andrew Cooper wrote:
On 04/09/14 15:31, Jan Beulich wrote:
On 04.09.14 at 15:02, wrote:
On 04/09/14 13:59, David Vrabel wrote:
On 04/09/14 13:38, Juergen Gross wrote:
Direct Xen to place the initial P->M table outside of the initial
mapping, as otherwise the
On 09/04/2014 02:59 PM, David Vrabel wrote:
On 04/09/14 13:38, Juergen Gross wrote:
Direct Xen to place the initial P->M table outside of the initial
mapping, as otherwise the 1G (implementation) / 2G (theoretical)
restriction on the size of the initial mapping limits the amount
of memor
On 09/04/2014 04:53 PM, David Vrabel wrote:
On 04/09/14 15:29, Jan Beulich wrote:
On 04.09.14 at 14:52, wrote:
On 04/09/14 13:38, Juergen Gross wrote:
--- a/arch/x86/xen/xen-head.S
+++ b/arch/x86/xen/xen-head.S
@@ -124,6 +124,9 @@ NEXT_HYPERCALL(arch_6)
ELFNOTE(Xen
On 09/04/2014 02:52 PM, Jan Beulich wrote:
On 04.09.14 at 14:38, <"jgr...@suse.com".non-mime.internet> wrote:
As the KEXEC and DUMPCORE related ELFNOTES are not relevant for the
kernel they are omitted from elfnote.h.
But the defines are still in the patch:
Oops, old header version. I'll cor
On 09/05/2014 11:05 AM, Andrew Cooper wrote:
On 05/09/14 08:55, Juergen Gross wrote:
On 09/04/2014 04:43 PM, Andrew Cooper wrote:
On 04/09/14 15:31, Jan Beulich wrote:
On 04.09.14 at 15:02, wrote:
On 04/09/14 13:59, David Vrabel wrote:
On 04/09/14 13:38, Juergen Gross wrote:
Direct Xen to
On 08/29/2014 04:55 PM, Konrad Rzeszutek Wilk wrote:
On Fri, Aug 29, 2014 at 03:44:06PM +0100, Jan Beulich wrote:
On 29.08.14 at 16:27, wrote:
Sure. Btw, someone also contacted me saying they have the same problem
without
changing the layout but having really big initrd (500M). While that feel
On 09/02/2014 09:22 PM, Konrad Rzeszutek Wilk wrote:
On Mon, Sep 01, 2014 at 06:03:06AM +0200, Juergen Gross wrote:
On 08/29/2014 04:55 PM, Konrad Rzeszutek Wilk wrote:
On Fri, Aug 29, 2014 at 03:44:06PM +0100, Jan Beulich wrote:
On 29.08.14 at 16:27, wrote:
Sure. Btw, someone also
Hi,
I'm just about to create a patch for full PAT support in the Linux
kernel, including Xen. For this purpose I introduce a translation
between cache modes and pte bits.
Scanning the kernel sources for usage of the cache mode bits in the
pte I discovered drivers/gpu/drm/i915/i915_gem_gtt.h is
On 08/13/2014 11:29 AM, David Vrabel wrote:
On 12/08/14 14:43, jgr...@suse.com wrote:
From: Juergen Gross
bind_interdomain_evtchn_to_irq() is currently a private function. It is used
only by bind_interdomain_evtchn_to_irqhandler() to register an irq-handler for
an event channel.
By making it
On 08/13/2014 11:53 AM, David Vrabel wrote:
On 12/08/14 14:43, jgr...@suse.com wrote:
From: Juergen Gross
bind_interdomain_evtchn_to_irq() is currently a private function. It is used
only by bind_interdomain_evtchn_to_irqhandler() to register an irq-handler for
an event channel.
By making it
On 08/13/2014 11:54 AM, David Vrabel wrote:
On 13/08/14 10:43, Juergen Gross wrote:
static int scsiback_init_sring(struct vscsibk_info *info, grant_ref_t
ring_ref,
evtchn_port_t evtchn)
{
...
irq = bind_interdomain_evtchn_to_irq(info->domid, evt
On 08/13/2014 05:07 PM, Jesse Barnes wrote:
On Fri, 8 Aug 2014 15:14:15 +0200
Daniel Vetter wrote:
Adding relevant mailing lists.
On Fri, Aug 8, 2014 at 1:23 PM, Juergen Gross wrote:
I'm just about to create a patch for full PAT support in the Linux
kernel, including Xen. For this pu
On 08/15/2014 12:21 PM, Ville Syrjälä wrote:
On Thu, Aug 14, 2014 at 05:55:11AM +0200, Juergen Gross wrote:
On 08/13/2014 05:07 PM, Jesse Barnes wrote:
On Fri, 8 Aug 2014 15:14:15 +0200
Daniel Vetter wrote:
Adding relevant mailing lists.
On Fri, Aug 8, 2014 at 1:23 PM, Juergen Gross wrote
On 08/18/2014 12:21 PM, Ville Syrjälä wrote:
On Mon, Aug 18, 2014 at 07:31:58AM +0200, Juergen Gross wrote:
On 08/15/2014 12:21 PM, Ville Syrjälä wrote:
On Thu, Aug 14, 2014 at 05:55:11AM +0200, Juergen Gross wrote:
On 08/13/2014 05:07 PM, Jesse Barnes wrote:
On Fri, 8 Aug 2014 15:14:15
On 08/01/2014 10:24 PM, James Bottomley wrote:
On Fri, 2014-08-01 at 05:03 -0700, Christoph Hellwig wrote:
On Fri, Aug 01, 2014 at 08:27:05AM +0200, jgr...@suse.com wrote:
From: Juergen Gross
If a scsi host driver specifies .cmd_len in it's scsi_host_template, a driver's
private co
On 08/04/2014 01:08 PM, Christoph Hellwig wrote:
On Mon, Aug 04, 2014 at 06:26:09AM +0200, jgr...@suse.com wrote:
From: Juergen Gross
If a scsi host driver specifies .cmd_len in it's scsi_host_template, a driver's
private command pool is needed. scsi_find_host_cmd_pool() will loca
On 08/04/2014 01:24 PM, jgr...@suse.com wrote:
From: Juergen Gross
If a scsi host driver specifies .cmd_len in it's scsi_host_template, a driver's
private command pool is needed. scsi_find_host_cmd_pool() will locate it, but
scsi_alloc_host_cmd_pool() isn't saving the pool addr
On 08/04/2014 01:49 PM, Boaz Harrosh wrote:
On 08/04/2014 02:30 PM, jgr...@suse.com wrote:
From: Juergen Gross
If a scsi host driver specifies .cmd_len in it's scsi_host_template, a driver's
private command pool is needed. scsi_find_host_cmd_pool() will locate it, but
scsi_alloc_hos
an be done
later without doing any harm, removing the need for allocating memory
via extend_brk().
While at it make some m2p override functions static as they are only
used internally.
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/xen/page.h | 6 --
arch/x86/xen/p2m.c
Introduces lookup_pmd_address() to get the address of the pmd entry
related to a virtual address in the current address space. This
function is needed for support of a virtual mapped sparse p2m list
in xen pv domains.
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/pgtable_types.h | 1
in 4 smaller ones as requested by David Vrabel
- added highmem check when remapping kernel memory as requested by
David Vrabel
Juergen Gross (5):
Xen: Delay remapping memory of pv-domain
xen: Delay m2p_override initialization
xen: Delay invalidating extra memory
x86: Introduce function to
g the boot process until some more basic memory management
functions are callable. This removes the need to create new p2m
entries until virtual memory management is available.
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/xen/page.h | 3 +
arch/x86/xen/p2m.c
sical memory
initialization time due to it's fixed structure.
A further advantage is the reduction in complexity and code volume as
we don't have to be careful regarding memory restrictions during p2m
updates.
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/xen/page.h | 1 -
arc
-> 32:35
System: 18:07 -> 17:47
User:104:00 -> 103:30
Tested on 64 bit dom0 and 32 bit domU.
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/xen/page.h | 27 +-
arch/x86/xen/mmu.c | 34 +-
arch/x86/xen/p2m.c
With the dynamical mapping between cache modes and pgprot values it is
now possible to use all cache modes via the Xen hypervisor PAT settings
in a pv domain.
All to be done is to read the PAT configuration MSR and set up the
translation tables accordingly.
Signed-off-by: Juergen Gross
Reviewed
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
drivers/video/fbdev/vermilion/vermilion.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev
The PAT bit in the ptes is not moved to the correct position when
copying page protection attributes between entries of different sized
pages. Translate the ptes according to their page size.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/mm/pageattr.c | 33
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross
Reviewed-by: Toshi Kani
Reviewed-by: Konrad Rzeszutek Wilk
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/include/asm/pgtable_types.h | 4 +++
arch/x86/mm/init.c | 8 ++
arch/x86/mm/mm_internal.h
Instead of directly using cache mode bits in the pte switch to usage of
the new cache mode type.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/fb.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/fb.h b/arch/x86
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/cacheflush.h | 38 --
arch/x86/include/asm/pat.h| 2 +-
arch/x86/mm/ioremap.c | 5
Remove no longer used defines from pgtable_types.h as they are not
used any longer.
Switch __PAGE_KERNEL_NOCACHE to use cache mode type instead of pte
bits.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/pgtable_types.h | 21 +
1 file
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type. This requires to change
io_reserve_memtype() as well.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/pat.h | 2 +-
arch/x86/mm/iomap_32.c | 12
Dumping page table protection bits is not correct for entries on levels
2 and 3 regarding the PAT bit, which is at a different position as on
level 4.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/mm/dump_pagetables.c | 24 +++-
1 file changed, 11
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type. This requires changing some callers of
is_new_memtype_allowed() to be changed as well.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/pgtable.h | 19
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type in the functiuons for modifying page
attributes.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/mm/pageattr.c | 54 +++---
1 file
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/io.h | 2 +-
arch/x86/include/asm/pat.h | 2 +-
arch/x86/mm/ioremap.c | 65
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type. As those are the main callers of
lookup_memtype(), change this as well.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/mm/pat.c | 32
1 file
ct build error on non-x86 arch by moving definition of
update_cache_mode_entry() to x86 specific header
Changes since RFC:
- renamed functions and variables as suggested by Toshi Kani
- corrected cache mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggested by Jan B
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/mm/init_64.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
drivers/video/fbdev/gbefb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/video/fbdev/gbefb.c b/drivers
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader
Signed-off-by: Juergen Gross
---
arch/x86/pci/i386.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index
: Juergen Gross
---
arch/x86/include/asm/pgtable_types.h | 73 +++-
arch/x86/mm/init.c | 29 ++
2 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/pgtable_types.h
b/arch/x86/include/asm/pgtable_types.h
On 10/31/2014 03:06 PM, Ingo Molnar wrote:
* Juergen Gross wrote:
Changes in V5:
- split up first patch as requested by Ingo Molnar and Thomas Gleixner
- add a helper function in pat_init_cache_modes() as requested by Ingo Molnar
The structure of this series looks great to me now.
Just to
On 10/27/2014 04:16 PM, David Vrabel wrote:
On 27/10/14 14:52, Juergen Gross wrote:
Paravirtualized kernels running on Xen use a three level tree for
translation of guest specific physical addresses to machine global
addresses. This p2m tree is used for construction of page table
entries, so
On 10/28/2014 12:53 PM, Andrew Cooper wrote:
On 28/10/14 09:51, Ian Campbell wrote:
On Tue, 2014-10-28 at 06:00 +0100, Juergen Gross wrote:
On 10/27/2014 04:16 PM, David Vrabel wrote:
On 27/10/14 14:52, Juergen Gross wrote:
Paravirtualized kernels running on Xen use a three level tree for
On 10/28/2014 01:46 PM, Andrew Cooper wrote:
On 28/10/14 12:44, David Vrabel wrote:
On 28/10/14 12:42, Andrew Cooper wrote:
On 28/10/14 12:39, David Vrabel wrote:
On 28/10/14 12:07, Juergen Gross wrote:
Okay, back to the original question: is the (up to) 64 MB virtual
mapping of the p2m list
On 10/28/2014 01:39 PM, David Vrabel wrote:
On 28/10/14 12:07, Juergen Gross wrote:
Okay, back to the original question: is the (up to) 64 MB virtual
mapping of the p2m list on 32-bit pv domains a problem or not?
I think up-to 64 MiB of vmalloc area is fine. The vmalloc space can be
On 10/28/2014 06:34 PM, David Vrabel wrote:
Can these patches be split up? They're hard to review as-is. e.g., the
changes to page allocation look they could be split out.
On 27/10/14 14:52, Juergen Gross wrote:
Early in the boot process the memory layout of a pv-domain is changed
to
On 10/29/2014 06:30 AM, Juergen Gross wrote:
On 10/28/2014 06:34 PM, David Vrabel wrote:
Can these patches be split up? They're hard to review as-is. e.g., the
changes to page allocation look they could be split out.
On 27/10/14 14:52, Juergen Gross wrote:
Early in the boot proces
On 10/29/2014 11:28 AM, Ingo Molnar wrote:
* Thomas Gleixner wrote:
On Mon, 27 Oct 2014, Juergen Gross wrote:
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true because there are a
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross
Reviewed-by: Toshi Kani
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/include/asm/pgtable_types.h | 4 +++
arch/x86/mm/init.c | 8 ++
arch/x86/mm/mm_internal.h| 2 ++
arch/x86/mm/pat.c
e mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggested by Jan Beulich
Juergen Gross (3):
x86: Make page cache mode a real type
x86: Enable PAT to use cache mode translation tables
Support Xen pv-domains using PAT
arch/x86/include/asm/cacheflush.h | 38
With the dynamical mapping between cache modes and pgprot values it is
now possible to use all cache modes via the Xen hypervisor PAT settings
in a pv domain.
All to be done is to read the PAT configuration MSR and set up the
translation tables accordingly.
Signed-off-by: Juergen Gross
Reviewed
: Juergen Gross
Reviewed-by: Toshi Kani
---
arch/x86/include/asm/cacheflush.h | 38 +
arch/x86/include/asm/fb.h | 6 +-
arch/x86/include/asm/io.h | 2 +-
arch/x86/include/asm/pat.h| 6 +-
arch/x86/include/asm/pgtable.h
In case a race was detected during allocation of a new p2m tree
element in alloc_p2m() the new allocated mid_mfn page is freed without
updating the pointer to the found value in the tree. This will result
in overwriting the just freed page with the mfn of the p2m leaf.
Signed-off-by: Juergen
On 10/14/2014 11:30 AM, David Vrabel wrote:
On 14/10/14 10:00, Juergen Gross wrote:
In case a race was detected during allocation of a new p2m tree
element in alloc_p2m() the new allocated mid_mfn page is freed without
updating the pointer to the found value in the tree. This will result
in
;t have to bother with two parallel trees now. The same applies
for some other internal functions.
While simplifying code, make early_can_reuse_p2m_middle() static and
drop the unused second parameter. p2m_mid_identity_mfn can be removed
as well, it isn't used either.
Signed-off-by: Juergen G
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