hat the LX's MSR_PADSEL has the wrong value
> in the data sheet. That's, uh, good to note.
>
> Signed-off-by: Andres Salomon <[EMAIL PROTECTED]>
Acked-by: Jordan Crouse <[EMAIL PROTECTED]>
Thanks for doing this - I'm always happy when stuff gets scratched off
Please CC back to me, as I am not subscribed to the list (but I soon
will be!)
I am writing a new framebuffer driver for a PCI based Chips and
Technologies 69000 HiQVideo chipset in the 2.4.2 code base on an i386
machine. (They are custom cards, but they use the standard BIOS and
setup provided
hen somebody else gets it wrong. The second one might seem more
fun, but I hope we can agree its far less productive.. :)
Jordan
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Senior Linux Engineer
AMD - Personal Connectivity Solutions Group
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Todd - do you have a ChangeLog from Take 1? :)
Jordan
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More majordomo inf
that shouldn't affect
too many people.
So, anyway, enjoy the watchdog timer - I hope it meets everybody's
expectations for the 2.6.25 kernel.
Jordan
--
Jordan Crouse
Systems Software Development Engineer
Advanced Micro Devices, Inc.
[GEODE] Add a watchdog driver based on the CS5535/CS5536 MFGP
On 20/01/08 14:22 +0100, Arnd Hannemann wrote:
> Hi,
>
> Jordan Crouse wrote:
> > On 17/01/08 23:52 +0100, Arnd Hannemann wrote:
> >>>> Watchdog for the new API would be great :-)
> >>> Coming soon.
> >
> > As promised, a watchdog dr
On 20/01/08 14:22 +0100, Arnd Hannemann wrote:
> Hi,
>
> Jordan Crouse wrote:
> > On 17/01/08 23:52 +0100, Arnd Hannemann wrote:
> >>>> Watchdog for the new API would be great :-)
> >>> Coming soon.
> >
> > As promised, a watchdog dr
the timer tick disabled
if you want.
Thanks,
Jordan
--
Jordan Crouse
Systems Software Development Engineer
Advanced Micro Devices, Inc.
diff --git a/arch/x86/kernel/mfgpt_32.c b/arch/x86/kernel/mfgpt_32.c
index 0ab680f..5b4fa24 100644
--- a/arch/x86/kernel/mfgpt_32.c
+++ b/arch/x86/ker
On 22/01/08 12:18 +0100, Arnd Hannemann wrote:
> Hi Lars,
>
> Lars Heete schrieb:
> > Hello,
> >
> > On Tuesday 22 January 2008 10:03:08 am Arnd Hannemann wrote:
> >> Jordan Crouse wrote:
> >>> Okay - I've been exploring a little bit mo
ts already being enabled on the other
vectors. Anyway, please try this test patch and let me know what happens.
Jordan
--
Jordan Crouse
Systems Software Development Engineer
Advanced Micro Devices, Inc.
[GEODE] fix a race condition in the MFGPT timer tick
From: Jordan Crouse <[EMAIL PROTECTED
ffects of the workaround ?
I'm not sure if we can - all we can tell is if the registers are zero or
not. Like I said, running the MSR is probably dangerous in 9 out of 10
situations, the one good use being the one you determined. I would
support adding the mfgptfix bit though - just as long as
On 22/01/08 22:15 +0100, Willy Tarreau wrote:
> On Tue, Jan 22, 2008 at 02:08:58PM -0700, Jordan Crouse wrote:
> > On 22/01/08 21:15 +0100, Willy Tarreau wrote:
> > > So it seems like applying the workaround on top of TinyBIOS 0.98 undoes
> > > this BIOS's work
; (S = siemens.)
>
> You're quite right. Same as we should write kHz and not Khz. But I'm
> used to change other people's work and particularly comments the least
> possible. Do you want an update ?
Please do - I don't mind if you change the comments - better that t
> Date: Mon, 19 Nov 2007 17:53:33 -0800
>
> This list [EMAIL PROTECTED] should be removed
> from MAINTAINERS if it continues to reject not moderate
> emails with patches to the list without subscribing.
Okay - moderation should be turned on. Please yell very loudly at me
(and ca
> Date: Mon, 19 Nov 2007 17:53:33 -0800
>
> This list [EMAIL PROTECTED] should be removed
> from MAINTAINERS if it continues to reject not moderate
> emails with patches to the list without subscribing.
Agreed. I'll switch to moderation.
>
>
>
--
Jordan Crouse
Sy
On 17/01/08 20:53 +0100, Arnd Hannemann wrote:
> Andres Salomon schrieb:
> > On Thu, 17 Jan 2008 10:54:30 +0100
> > Arnd Hannemann <[EMAIL PROTECTED]> wrote:
> >
> >> Andres Salomon schrieb:
> >>> On Wed, 16 Jan 2008 16:19:12 -0500
> >>> Andres Salomon <[EMAIL PROTECTED]> wrote:
> >>>
> On We
1400020 => b7:ef:5f:f4:bf:d1:95:68
> MSR register 0x51400021 => b7:fd:1f:f4:bf:cf:5a:d8
> MSR register 0x51400022 => b7:f3:bf:f4:bf:f5:fb:a8
> MSR register 0x51400023 => b7:fb:9f:f4:bf:fd:d9:f8
Hmmm - those look wrong. Is /dev/cpu/0/msr there? The applet on the
wiki has a bug t
On 17/01/08 22:50 +0100, Arnd Hannemann wrote:
> Jordan Crouse schrieb:
> > On 17/01/08 20:53 +0100, Arnd Hannemann wrote:
> >> Andres Salomon schrieb:
> >>> On Thu, 17 Jan 2008 10:54:30 +0100
> >>> Arnd Hannemann <[EMAIL PROTECTED]> wrote:
> &g
On 18/01/08 00:39 +0100, Arnd Hannemann wrote:
> Jordan Crouse schrieb:
> > On 17/01/08 23:52 +0100, Arnd Hannemann wrote:
> >
> >
> >
> >>> Hmmm - not sure whats happening here. I wonder if we're stuck in an
> >>> interrupt
that causes hangs exactly like you are seeing.
Jordan
--
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Advanced Micro Devices, Inc.
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More majordomo info at ht
screen, but the rest of the display area remains showing whatever
> contents were on the screen when the blank was triggered. Hitting a
> key goes back to displaying the current fb contents like you would
> expect.
Thanks for reporting that - thats a known bug, I'll send a patch to
On 27/01/08 14:55 -0500, Andrew Paprocki wrote:
> On Jan 27, 2008 2:28 PM, Jordan Crouse <[EMAIL PROTECTED]> wrote:
> > On 27/01/08 13:45 -0500, Andrew Paprocki wrote:
> > > Using 2.6.24, I can't get my Geode LX (LX800 CPU) to boot in anything
> > > other than
On Tuesday 26 June 2001 06:34, Alan Cox mentioned:
> > I suppose they received some pression from M$, but if people read of a
> > FUD from a M$ employed, then they can guess what is going on, if it is a
> > newspaper usually telling facts in a correct way...
>
> It is common for newspaper staff t
> After all - how often does the average linux machine boot? Once a day at
> most. Mine usually run until the next kernel upgrade. But then again,
> I'm not a kernel hacker, so this is to be taken more as a users point of
> view.
Don't forget that embedded devices boot much more often than their
So, are you saying, right now in front of the whole community, that you only
use Linux because you can develop on it? That if it wasn't for GCC you would
be playing Minesweeper right now?
I know thats not what you are saying, but thats how you come across. We
always tell everybody who woul
If you are using the vesa framebuffer on the Geode, you will also want to
make a minor change to vesafb.c. Because the framebuffer is located within
the processor itself, requesting the memory region always caused my Geode
boxes to freeze. I think that we can safely eliminate this call, since
From: Jordan Crouse <[EMAIL PROTECTED]>
A relatively recent version of the Geode LX datasheet listed the wrong
address for one of the MSRs that controls TFT panels, resulting in
breakage. This patch corrects the MSR address.
Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
---
d
On 29/10/07 17:02 -0700, H. Peter Anvin wrote:
> Jordan Crouse wrote:
> > From: Jordan Crouse <[EMAIL PROTECTED]>
> >
> > A relatively recent version of the Geode LX datasheet listed the wrong
> > address for one of the MSRs that controls TFT panels, result
zealous - the 5535 only supports
up to UDMA4, which matches the array.
Jordan
--
Jordan Crouse
Systems Software Development Engineer
Advanced Micro Devices, Inc.
[PATCH] Fix an ovverun found in the 5535 IDE driver
From: Jordan Crouse <[EMAIL PROTECTED]>
As found by the Coverity checker, a
. This
> changes it so that we set the substream when constructing the specific
> bus master DMA, and unsetting it when we tear down the BM's DMA.
>
> Signed-off-by: Andres Salomon <[EMAIL PROTECTED]>
Acked-by: Jordan Crouse <[EMAIL PROTECTED]>
> ---
>
>
PRD registers twice; even powering
> down the ACC shouldn't mess with the PRD registers (according to the 5536
> data sheet, section 5.3.7.4, power-down procedure). This patch reworks
> all that to first disable DMA, and then save PRD registers.
>
> Signed-off-by: Andres Salom
27;re not using.. well,
> that warrants spitting out an error message (imo).
>
> Signed-off-by: Andres Salomon <[EMAIL PROTECTED]>
Acked-by: Jordan Crouse <[EMAIL PROTECTED]>
> ---
>
> sound/pci/cs5535audio/cs5535audio.c | 24 +++---
> Signed-off-by: Andres Salomon <[EMAIL PROTECTED]>
Acked-by: Jordan Crouse <[EMAIL PROTECTED]>
> ---
>
> sound/pci/cs5535audio/cs5535audio.h | 10 +-
> 1 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/sound/pci/cs5535audio/cs5535audio.h
On 29/08/07 23:30 -0400, Andres Salomon wrote:
>
> Save the PCI state before disabling the device, and add some error checking.
>
> Signed-off-by: Andres Salomon <[EMAIL PROTECTED]>
Acked-by: Jordan Crouse <[EMAIL PROTECTED]>
> ---
>
> sound/pci/cs
opular chip now, so I recommend we put these in,
and if by some unlucky coincidence a 5535 bug pops up, we'll deal with it
when it happens.
Jordan
--
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Systems Software Development Engineer
Advanced Micro Devices, Inc.
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source code is open, so you can peruse
it and discover its secrets for yourself:
http://dev.laptop.org/git.do?p=geode-vsa;a=tree;hb=HEAD
Jordan
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Systems Software Development Engineer
Advanced Micro Devices, Inc.
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with the CS5510/20 VSA1 tree I
> have here (which isn't under LGPL)
Not to get any further off topic - but we're still soliciting volunteers
to help port the VSA2 code so that it will build with OSS tools. If you're
interested, don't hesitate to dive in. :) Patches alway
On Fri, 19 Oct 2007 14:01:56 +0200, Florian Fainelli wrote:
> Hi Andres,
>
> Le jeudi 18 octobre 2007, Andres Salomon a écrit :
>> While I certainly would like to see a generic GPIO API, this one isn't
>> really useful for geode GPIOs. It would be nice to have one that did
>> work for us as well
also adds a bit of sanity checking; it is no
> longer possible to use a GPIO above 28.
>
>
> Note the semantics of geode_gpio_isset() have changed:
> geode_gpio_isset(geode_gpio(3)|geode_gpio(4), ...)
> will only return true iff both GPIOs are set.
>
> Signed-off-by: Andr
On 18/10/07 15:26 -0400, Andres Salomon wrote:
> Simple cosmetic update for the cs5536 reboot fixup; define the MSR that's used
> for rebooting in geode.h, and use the define.
>
> Signed-off-by: Andres Salomon <[EMAIL PROTECTED]>
Acked-by: Jordan Crouse <[EMAIL PROTEC
On 07/12/06 22:16 -0800, Randy Dunlap wrote:
> From: Randy Dunlap <[EMAIL PROTECTED]>
>
> This driver seems to be for a PCI device.
Indeed it is. Nice catch.
> Signed-off-by: Randy Dunlap <[EMAIL PROTECTED]>
Acked-by: Jordan Crouse <[EMAIL PROTECTED]>
> ---
gt; 3.Ditto for a watchdog use - although that would be a separate
> driver using the kernel hooks anyway.
That was the plan - I do have a watchdog driver that I had when I first
wrote the MFGPT driver for a now defunct project. I should dust it off
and add it in.
Thanks,
Jordan
--
Jordan Cro
Attached is a trivial patch that renames a poorly worded PCI ID
for the Geode GX and CS5535 companion chips. The graphics processor
and host bridge actually live in the northbridge on the integrated
processor, not in the companion chip.
---
Jordan Crouse
Senior Linux Engineer
Advanced Micro
after they
have had a chance to soak a little bit more in the OLPC tree.
Jordan
GEODE: Add framebuffer support for the AMD Geode LX
From: Jordan Crouse <[EMAIL PROTECTED]>
Add framebuffer support for the AMD Geode LX graphics engine.
Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]&g
On 14/07/07 17:05 -0400, Andrew Paprocki wrote:
> Tony,
>
> Do you have the patch working already? I'd love to try this out in the
> meantime on the LX system I am developing with at the moment. I'm
> assuming you worked this into the existing Arcom framework (gxfb) and
> pulled the necessary piec
On 19/04/07 08:54 +0200, Jean Delvare wrote:
> Hi Len,
>
> On Wed, 18 Apr 2007 13:42:56 -0400, Lennart Sorensen wrote:
> > On Sat, Apr 14, 2007 at 07:28:07PM +0200, Jean Delvare wrote:
> > > Otherwise it looks OK to me, I take the patch. If others have comments
> > > or objections, just speak up a
the one used with the geode LX (which does work now).
That ISA detection is almost definately suffering from severe bit rot.
Once you get past that though, you should be fine - the silicon behind
the ACB hasn't changed since the MediaGX days.
Jordan
--
Jordan Crouse
Senior Linux Engineer
either. Regardless,
randomly hitting ISA ports seems scary to me. I know its a pain to use
the module params all the time, but thats really probably the cleanest way
to to it without carrying around a special patch for your system.
Jordan
--
Jordan Crouse
Senior Linux Engineer
Advanced Micro De
On 26/04/07 09:29 -0400, [EMAIL PROTECTED] wrote:
>
> These return all 0x00
>
> On the Geode LX800 where scx200_acb does work all 4 commands return all
> 0xff.
There is no ISA on the LX.
--
Jordan Crouse
Senior Linux Engineer
Advanced Micro Devices, Inc.
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To unsubscribe
On 27/04/07 10:02 +0200, Jean Delvare wrote:
> On Thu, 26 Apr 2007 10:03:23 -0400, Lennart Sorensen wrote:
> > On Thu, Apr 26, 2007 at 07:39:20AM -0600, Jordan Crouse wrote:
> > > There is no ISA on the LX.
> >
> > Isn't LPC a good equivalent?
>
> I suspe
anyway.
>
> Fixes: 7c65817e6d38 ("drm/msm: gpu: Enable zap shader for A5XX")
> Signed-off-by: Arnd Bergmann
Seems reasonable to me if Bjorn agrees.
Acked-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +++-
> 1 file changed, 3 insertions(
ad.
>
> Fixes: 7c65817e6d38 ("drm/msm: gpu: Enable zap shader for A5XX")
> Signed-off-by: Arnd Bergmann
(ARM && COMPILE_TEST) really gives the dependency checks a run for their money.
I assume Bjorn is cool with this.
Acked-by: Jordan Crouse
> ---
> drivers/gp
On Mon, Oct 23, 2017 at 05:55:37PM +0200, Benjamin Gaignard wrote:
> Instead a getting only one common device "/dev/ion" for
> all the heaps this patch allow to create one device
> entry ("/dev/ionX") per heap.
> Getting an entry per heap could allow to set security rules
> per heap and global ones
On Mon, Aug 06, 2018 at 02:37:18PM +0530, Amit Nischal wrote:
> On 2018-08-03 04:14, Stephen Boyd wrote:
> >Quoting Amit Nischal (2018-07-30 04:28:56)
> >>On 2018-07-25 12:28, Stephen Boyd wrote:
> >>>
> >>> Ok. Sounds good! Is the rate range call really needed? It can't be
> >>> determined in the
On Tue, Aug 07, 2018 at 10:58:19PM -0700, Stephen Boyd wrote:
> Quoting Jordan Crouse (2018-08-06 08:04:37)
> > On Mon, Aug 06, 2018 at 02:37:18PM +0530, Amit Nischal wrote:
> > > On 2018-08-03 04:14, Stephen Boyd wrote:
> > > >Quoting Amit Nischal (2018-07-30 04:28:5
On Wed, Aug 08, 2018 at 09:14:05PM +0530, Sibi Sankar wrote:
> Hi Rob,
> Thanks for the review
>
> On 08/07/2018 11:46 PM, Rob Herring wrote:
> >On Tue, Jul 31, 2018 at 06:27:24PM +0530, Sibi S wrote:
> >>Hi Philipp,
> >>Thanks for the review!
> >>
> >>On 07/31/2018 02:12 PM, Philipp Zabel wrote:
On Wed, Aug 08, 2018 at 03:37:24PM -0600, Jordan Crouse wrote:
> On Wed, Aug 08, 2018 at 09:14:05PM +0530, Sibi Sankar wrote:
> > Hi Rob,
> > Thanks for the review
> >
> > On 08/07/2018 11:46 PM, Rob Herring wrote:
> > >On Tue, Jul 31, 2018 at 06:27:24PM +
adreno now has to also be one.
> The code seems to deal fine with nvmem being completely disabled,
> it will just not set the right speed bin then, so we don't need
> a hard dependency.
>
> Fixes: f56d9df656c4 ("drm/msm/adreno: Read the speed bins for a5xx targets")
&
On Sat, Apr 07, 2018 at 06:00:29AM -0700, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2018-03-15 21:08:18)
> > From: Viresh Kumar
> >
> > This adds a new helper to let the power domain drivers to access
> > opp->np, so that they can read platform specific properties from the
> > node.
> >
> >
On Tue, Apr 10, 2018 at 01:08:13PM -0700, Rishabh Bhatnagar wrote:
> LLCC (Last Level Cache Controller) provides additional cache memory
> in the system. LLCC is partitioned into multiple slices and each
> slice gets its own priority, size, ID and other config parameters.
> LLCC driver programs the
On Tue, Sep 25, 2018 at 01:02:15PM -0500, Rob Herring wrote:
> On Fri, Aug 31, 2018 at 05:01:45PM +0300, Georgi Djakov wrote:
> > This binding is intended to represent the relations between the interconnect
> > controllers (providers) and consumer device nodes. It will allow creating
> > links
> >
On Mon, Aug 13, 2018 at 12:03:03PM +0530, Amit Nischal wrote:
> Changes in v3:
> * Modified the determine_rate() op to use the min/max rate range
> to round the requested rate within the set_rate range. With this,
> requested set rate will always stay within the limits.
>
> Changes in v2:
> Ad
On Mon, Aug 13, 2018 at 12:03:07PM +0530, Amit Nischal wrote:
> Add support for the graphics clock controller found on SDM845
> based devices. This would allow graphics drivers to probe and
> control their clocks.
>
> Signed-off-by: Amit Nischal
> ---
> drivers/clk/qcom/Kconfig| 9 +
>
not yet exist.
v3: Use macros and change port string per Georgi Djakov
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +
drivers/gpu/drm/msm
On Fri, Dec 07, 2018 at 10:06:56AM -0700, Jordan Crouse wrote:
> Try to get the interconnect path for the GPU and vote for the maximum
> bandwidth to support all frequencies. This is needed for performance.
> Later we will want to scale the bandwidth based on the frequency to
> also
On Mon, May 28, 2018 at 12:38:41PM +0530, Souptick Joarder wrote:
> On Mon, May 21, 2018 at 10:59 PM, Souptick Joarder
> wrote:
> > Use new return type vm_fault_t for fault handler. For
> > now, this is just documenting that the function returns
> > a VM_FAULT value rather than an errno. Once all
On Thu, May 17, 2018 at 05:02:17PM +0530, Vikash Garodia wrote:
> In order to invoke scm calls, ensure that the platform
> has the required support to invoke the scm calls in
> secure world.
>
> Signed-off-by: Vikash Garodia
> ---
> drivers/soc/qcom/mdt_loader.c | 21 +
> 1 f
On Thu, May 17, 2018 at 05:02:18PM +0530, Vikash Garodia wrote:
> Add a new routine to reset the ARM9 and brings it
> out of reset. This is in preparation to add PIL
> functionality in venus driver.
>
> Signed-off-by: Vikash Garodia
> ---
> drivers/media/platform/qcom/venus/firmware.c | 26
On Tue, Dec 18, 2018 at 06:50:38PM +0530, Jayant Shekhar wrote:
> Remove unused functions from dpu plane interface
> and unused variables from dpu plane state structure.
>
> Signed-off-by: Jayant Shekhar
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/disp/dpu
On Fri, Dec 14, 2018 at 02:19:12PM +0530, Jayant Shekhar wrote:
> Remove unused functions and macros from dpu hw interrupts
> file.
>
> Signed-off-by: Jayant Shekhar
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 30
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interr
Add documentation for the interconnect and interconnect-names bindings
for the GPU node as detailed by bindings/interconnect/interconnect.txt.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 4
1 file changed, 4 insertions(+)
diff --git a
interconnect name from driver and bindings
Jordan Crouse (3):
drm/msm/a6xx: Add support for an interconnect path
dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU
arm64: dts: sdm845: Add interconnect for GPU
.../devicetree/bindings/display/msm/gpu.txt | 4
arch/arm64
not yet exist.
v5: Remove hardcoded interconnect name and just use the default
v4: Don't use a port string at all to skip the need for names in the DT
v3: Use macros and change port string per Georgi Djakov
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Kconfig | 1 +
dr
Define an interconnect port for the GPU to set bus
capabilities.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 1005f1eb1920
read_aux_data_len() API entirely and also get rid of the memcpy
> operation from cmd_db to the caller.
>
> Cc: Mahesh Sivasubramanian
> Cc: Lina Iyer
> Cc: Bjorn Andersson
> Cc: Evan Green
> Cc: Jordan Crouse
> Cc: Rob Clark
> Signed-off-by: Stephen Boyd
> --
es here.
I'm still trying to track down the particulars of the fix from the BIOS
vendor. I'll let you know.
> Do you still need the disassembled reserve_bootmem_core?
Sure - you might as well - just to make sure its the same problem.
Jordan
--
Jordan Crouse
Systems Software
e the bootmem bitmap (at _pa_symbol(_text), which is
page 0x100), then the system gets appropriately angry.
As background, I'm using syslinux 3.36 as my loader here - I've used this
exact same version for a very long time, so I don't blame it in the least.
Something is getting confused
.
This fixes the problem with the DB800, and so it probably should
with the other Geode platforms affected by this.
Many thanks to hpa for the guiding hand.
Jordan
--
Jordan Crouse
Systems Software Development Engineer
Advanced Micro Devices, Inc.
[i386]: Return an error if the e820 detection
On 26/09/07 14:04 -0700, H. Peter Anvin wrote:
> Jordan Crouse wrote:
> > On 26/09/07 12:14 -0700, H. Peter Anvin wrote:
> >> Please try the following debug patch to let us know what is going on.
> >>
> >>-hpa
> >
> >> diff --git a/arch/i386
we detect this situation, declare the E820 data
> unusable and fall back to E801.
>
> Also, revert to original behavior of always probing all memory
> methods; that way all the memory information is available to the
> kernel.
>
> Signed-off-by: H. Peter Anvin <[EMAIL PROTECTED
code with the LX BIOS, so it would be a huge coincidence if they were
affected by the same problem.
Jordan
--
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Systems Software Development Engineer
Advanced Micro Devices, Inc.
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On 27/09/07 15:47 -0700, H. Peter Anvin wrote:
> Jordan Crouse wrote:
> >
> > Breaks on the Geode - original behavior.
> >
> > I think that having boot_prams.e820_entries != 0 makes the kernel
> > assume the e820 data is correct.
> >
>
> Okay, now
On 27/09/07 15:17 -0700, H. Peter Anvin wrote:
> As luck would have it, it's not just an obscure Geode system which has a
> broken E820 implementation. Today I received a bug report about a Dell
> system (XPS M1330) with broken E820.
>
> Unfortunately, the workaround for the Geode breaks this sys
On 27/09/07 16:27 -0700, H. Peter Anvin wrote:
> Jordan Crouse wrote:
> > On 27/09/07 15:47 -0700, H. Peter Anvin wrote:
> >> Jordan Crouse wrote:
> >>> Breaks on the Geode - original behavior.
> >>>
> >>> I think that having boot_prams.e820_en
On 27/09/07 16:36 -0700, H. Peter Anvin wrote:
> Jordan Crouse wrote:
> >>>
> >> Oh bugger, looks like this one might be genuinely my fault after all.
> >> The ID check in the new code is buggy.
> >>
> >> Can you please test this revised patch o
he math to figure out whats happening - and I'll check the release
notes to see what changed in the BIOS between the failing and working
version. If anybody familiar with arch/i386 can think of something
new in the kernel that may have precipitated this, do let me know. :)
Jordan
--
Jordan C
On Tue, May 22, 2018 at 04:04:51PM +0300, Stanimir Varbanov wrote:
> Hi Vikash,
>
> On 05/17/2018 02:32 PM, Vikash Garodia wrote:
> > In order to invoke scm calls, ensure that the platform
> > has the required support to invoke the scm calls in
> > secure world. This code is in preparation to add
configuration to be NULL just in case the caller
accidentally calls for a flush with the wrong device.
Signed-off-by: Jordan Crouse
---
drivers/iommu/io-pgtable.h | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
Add support for a split pagetable (TTBR0/TTBR1) scheme for
arm-smmu-v2. If split pagetables are enabled, create a
pagetable for TTBR1 and set up the sign extension bit so
that all IOVAs with that bit set are mapped and translated
from the TTBR1 pagetable.
Signed-off-by: Jordan Crouse
Add a new domain attribute to enable split pagetable support for devices
devices that support it.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index e90da6b..3f2250b 100644
--- a/include
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path. This clears the way
to change ctx->aspace to a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c| 2 ++
drivers/gpu/d
When we move to 64 bit addressing for a5xx and a6xx targets we will start
seeing pagefaults at larger addresses so format them appropriately in the
log message for easier debugging.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1
u domain to map and
unmap iova addresses in the pagetable. The driver/hardware can be used
to switch the pagetable according to its own specific implementation.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 135 ++-
1 file changed, 11
Add support for creating a auxiliary domain from the IOMMU device to
implement per-instance pagetables. Also add a helper function to
return the pagetable base address (ttbr) and asid to the caller so
that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse
Add a helper function to create a GEM address space attached to
an iommu auxiliary domain for a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.h | 4 +++
drivers/gpu/drm/msm/msm_gem_vma.c | 53 +++
2 files changed
cular, I want to make sure that this fits with the
current thinking about how aux domains should look and feel.
[1] https://patchwork.freedesktop.org/series/43447/
[2] https://patchwork.kernel.org/patch/10825061/
Jordan Crouse (15):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Add
Add an attribute to return the base address of the pagetable. This is used
by auxiliary domains from arm-smmu to return the address of the pagetable
to the leaf driver so that it can set the appropriate pagetable through
it's own means.
Signed-off-by: Jordan Crouse
---
include/linux/io
generating 32 bit addresses so switch over now to prepare
for using addresses above 4G for targets that support them.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++
2 files changed, 28 insertions
Add support for per-instance pagetables for a6xx targets. Add support
to handle split pagetables and create a new instance if the needed
IOMMU support exists and insert the necessary PM4 commands to trigger
a pagetable switch at the beginning of a user command.
Signed-off-by: Jordan Crouse
some of the target files but I think
it pays for itself in improved code flow and flexibility.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 37 --
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 50 ++
drivers/gpu/drm/msm
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