Replaces a simple division by 2 to a right shiftrotation of 1 bit.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-host.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware-host.c
b/drivers/pci/dwc/pcie-designware
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration, therefore this patch aims to add
endpoint mode support to the designware driver.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/Kconfig | 45
Hi Fabio,
On 28/03/2018 13:05, Fabio Estevam wrote:
> Hi Gustavo,
>
> On Wed, Mar 28, 2018 at 8:38 AM, Gustavo Pimentel
> wrote:
>
>> diff --git a/drivers/pci/dwc/pcie-designware-host.c
>> b/drivers/pci/dwc/pcie-designware-host.c
>> index 550fdbb..03e9b82 100
struct
> pci_epf *epf);
> int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
>struct pci_epf_header *hdr);
> int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
> - enum pci_barno bar,
> - dma_addr_t bar_phys, size_t size, int flags);
> + struct pci_epf_bar *epf_bar);
> void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, int bar);
> int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
>phys_addr_t phys_addr,
> diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
> index e897bf076701..f7d6f4883f8b 100644
> --- a/include/linux/pci-epf.h
> +++ b/include/linux/pci-epf.h
> @@ -97,6 +97,8 @@ struct pci_epf_driver {
> struct pci_epf_bar {
> dma_addr_t phys_addr;
> size_t size;
> + enum pci_barno barno;
> + int flags;
> };
>
> /**
>
Seems good to me. :)
Reviewed-by: Gustavo Pimentel
4, 0);
> + } else {
> + dw_pcie_writel_dbi2(pci, reg, size - 1);
> + dw_pcie_writel_dbi(pci, reg, flags);
> + }
> dw_pcie_dbi_ro_wr_dis(pci);
>
> return 0;
>
Seems good to me. :)
Reviewed-by: Gustavo Pimentel
(struct pci_epc *epc, u8 func_no,
>struct pci_epf_header *hdr);
> int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
> struct pci_epf_bar *epf_bar);
> -void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, int bar);
> +void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
> +struct pci_epf_bar *epf_bar);
> int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
>phys_addr_t phys_addr,
>u64 pci_addr, size_t size);
>
Seems good to me. :)
Reviewed-by: Gustavo Pimentel
_dbi2(pci, reg + 4, 0x0);
> + dw_pcie_writel_dbi(pci, reg + 4, 0x0);
> + }
> dw_pcie_dbi_ro_wr_dis(pci);
> }
>
>
Seems good to me. :)
Reviewed-by: Gustavo Pimentel
dpoint/functions/pci-epf-test.c | 28 +
> drivers/pci/endpoint/pci-epc-core.c | 32 +++-
> drivers/pci/endpoint/pci-epf-core.c | 4 +++
> include/linux/pci-epc.h | 11 ----
> include/linux/pci-epf.h | 2 ++
> 8 files changed, 95 insertions(+), 45 deletions(-)
>
For the whole series:
Tested-by: Gustavo Pimentel
Regards,
Gustavo
Hi Kishon,
On 24/04/2018 12:24, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 24 April 2018 03:06 PM, Gustavo Pimentel wrote:
>> Hi Kishon,
>>
>> On 24/04/2018 08:07, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Monday 23 April
Hi Kishon,
On 24/04/2018 12:43, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 24 April 2018 04:27 PM, Gustavo Pimentel wrote:
>> Hi Kishon,
>>
>> On 24/04/2018 08:19, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Tuesday 17 April
Add a seconds entry on the pci_epf_test_ids structure that disables the
linkup_notifier parameter on driver for the DesignWare EP.
Allow DesignWare EPs that doesn't have linkup notification signal to work
with pcitest.
Update the binding documentation accordingly.
Signed-off-by: Gu
Replace "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
however it still be compatible with any previous DT that uses the old
reg-name.
Replace the PCIe base address example by a real PCIe base address in use.
Signed-off-by: Gustavo Pimentel
Revi
Replace magic numbers by a self-explained define to ease human
comprehension.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Changes
Replace of all initial lowercase character in comments and debug messages
to uppercase to maintain coherence.
Fix messages coherence within the DesignWare driver.
Fix code style on dw_pcie_irq_domain_free() function.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
Acked-by: Joao Pinto
right shift rotation of 1
bit.
- Replacement of all initial lowercase character in comments and debug
messages to uppercase to maintain coherence.
Gustavo Pimentel (9):
bindings: PCI: designware: Example update
PCI: dwc: Add support for EP mode
PCI: endpoint: functions/pci-epf-test: Add second
Add a callback to define the maximum number of vectors used by the RC.
Since this is a parameter associated to each SoC IP setting, makes sense
to be configurable and easily visible to future modifications.
Set DesignWare driver vectors number maximum to 256.
Signed-off-by: Gustavo Pimentel
Add the DesignWare EP device ID entry to pci_endpoint_test driver table.
Allow the device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v1->v2:
- Changed device id following Kishon's suggestion
ce it by the equivalent operation in this case, the shift
rotation.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
Acked-by: Joao Pinto
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set versi
The PCIe controller dual mode is capable of operating in RC mode as well
as EP mode by configuration option. Till now only RC mode was supported,
with this patch is add EP support to the DesignWare driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v1->
Add device tree binding documentation for the EP in PCIe DesignWare driver.
Signed-off-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
Change v1->v2:
- Add a missing log description.
- Add "snps,dw-pcie" compatible string following Kishon's suggestion.
Change v2->v3
Add PCI_EPC_IRQ_MSIX type.
Add MSI-X callbacks signatures to ops structure.
Add sysfs interface for set/get MSI-X capability maximum number.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/endpoint/pci-ep-cfs.c | 24
drivers/pci/endpoint/pci-epc-core.c | 57
Remove duplicate defines located on pcie-designware.h file already
available on /include/uapi/linux/pci-regs.h file.
Add pci_epc_set_msi() maximum 32 interrupts validation.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-ep.c | 49
Change cdns_pcie_ep_raise_irq() signature, namely the interrupt_num variable
type
from u8 to u16 to accommodate the 2048 maximum MSI-X interrupts.
Signed-off-by: Gustavo Pimentel
Acked-by: Alan Douglas
---
drivers/pci/cadence/pcie-cadence-ep.c | 2 +-
1 file changed, 1 insertion(+), 1
triggering interruptions.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pci-dra7xx.c | 2 +-
drivers/pci/dwc/pcie-artpec6.c | 2 +-
drivers/pci/dwc/pcie-designware-ep.c | 143 -
drivers/pci/dwc/pcie-designware-plat.c | 4 +-
drivers/pci
Add MSI-X support to pcitest tool.
Modify pcitest.sh script to accomodate MSI-X interrupt tests.
Signed-off-by: Gustavo Pimentel
---
include/uapi/linux/pcitest.h | 1 +
tools/pci/pcitest.c | 18 +-
tools/pci/pcitest.sh | 25 +
3 files
interrupt ID number from the command section to a
register located in a BAR.
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/pci-endpoint-test.txt | 3 +
drivers/misc/pci_endpoint_test.c | 121 +++
drivers/pci/endpoint/functions/pci-epf-test.c
Replace "pdev->irq + index" operation by the pci_irq_vector() call,
that converts from device vector to Linux IRQ.
(suggestion made by Alan Douglas).
Signed-off-by: Gustavo Pimentel
---
drivers/misc/pci_endpoint_test.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-
Replace all initial lower case character into upper case in comments
and debug printks.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/pci_endpoint_test.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc
Add a legacy interrupt callback handler. Currently DesignWare IP don't
allow triggering the legacy interrupt.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-ep.c | 10 ++
drivers/pci/dwc/pcie-designware-plat.c | 3 +--
drivers/pci/dwc/pcie-designware.h
Replace all initial lower case character into upper case in comments
and debug printks.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/endpoint/functions/pci-epf-test.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/endpoint
driver.
Add a new input parameter (msix) to pcitest tool to test MSI-X feature.
Update the pcitest.sh script to support MSI-X feature tests.
[1] -> https://lkml.org/lkml/2018/4/27/342
Gustavo Pimentel (10):
PCI: endpoint: Add MSI-X interfaces
PCI: dwc: Add MSI-X callbacks handler
Hi Alan,
On 30/04/2018 16:35, Alan Douglas wrote:
> Hi Gustavo,
>
> On April 27, 2018, 4:57 p.m. Gustavo Pimentel wrote:
>> Add MSI-X support and update driver documentation accordingly.
>>
>> Add new driver parameter to allow interruption type selection.
>>
&g
Hi Lorenzo,
On 30/04/2018 15:22, Lorenzo Pieralisi wrote:
> On Fri, Apr 27, 2018 at 12:59:58PM +0100, Gustavo Pimentel wrote:
>> Add a seconds entry on the pci_epf_test_ids structure that disables the
>
> "Add a second entry..."
Fixed, sorry for letting it slip.
On 26/04/2018 17:56, Lorenzo Pieralisi wrote:
> On Tue, Apr 24, 2018 at 02:44:40PM +0100, Gustavo Pimentel wrote:
>> Adds a seconds entry on the pci_epf_test_ids structure that disables the
>
> "Add a second entry to..."
>
>> linkup_notifier parameter on driver
Vijay Abraham I wrote:
>>>> Hi Lorenzo,
>>>>
>>>> On Thursday 26 April 2018 10:26 PM, Lorenzo Pieralisi wrote:
>>>>> On Tue, Apr 24, 2018 at 02:44:40PM +0100, Gustavo Pimentel wrote:
>>>>>> Adds a seconds entry on the pci_epf_test_
Add the DesignWare EP device ID entry to pci_endpoint_test driver table.
Allow the device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion
Add device tree binding documentation for the EP in PCIe DesignWare driver.
Signed-off-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings
accordingly to the controller specific requirements.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig | 41 +--
drivers/pci/dwc/pcie-designware-ep.c | 3 +
drivers/pci/dwc/pcie-designware-plat.c| 149
The PCIe controller dual mode is capable of operating in RC mode as well
as EP mode by configuration option. Till now only RC mode was supported,
with this patch is add EP support to the DesignWare driver.
Gustavo Pimentel (4):
bindings: PCI: designware: Example update
PCI: dwc: Add support
Replace "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
however it still be compatible with any previous DT that uses the old
reg-name.
Replace the PCIe base address example by a real PCIe base address in use.
Signed-off-by: Gustavo Pimentel
Revi
Patch set was made against the Lorenzo's pci/dwc branch.
The PCIe controller dual mode is capable of operating in RC mode as well
as EP mode by configuration option. Till now only RC mode was supported,
with this patch is add EP support to the DesignWare driver.
Gustavo Pimentel (4):
bin
Replace "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
however it still be compatible with any previous DT that uses the old
reg-name.
Replace the PCIe base address example by a real PCIe base address in use.
Signed-off-by: Gustavo Pimentel
Revi
Add device tree binding documentation for the EP in PCIe DesignWare driver.
Signed-off-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings
Add the DesignWare EP device ID entry to pci_endpoint_test driver table.
Allow the device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion
accordingly to the controller specific requirements.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig | 37 +--
drivers/pci/dwc/pcie-designware-ep.c | 3 +
drivers/pci/dwc/pcie-designware-plat.c| 149
Hi Alan,
On 24/04/2018 10:57, Alan Douglas wrote:
> Hi Gustavo,
>
> On 10 April 2018 18:15, Gustavo Pimentel wrote:
>> Adds MSI-X support to the pcitest tool and modified the pcitest.sh script to
>> accomodate this new type of interruption test.
>>
>>
On Thu, Apr 4, 2019 at 13:20:23, Vidya Sagar wrote:
> Add an API to group all the tasks to be done to de-initialize host which
> can then be called by any Designware core based driver implementations
s/Designware/DesignWare
> while adding .remove() support in their respective drivers.
>
> Sign
bi_base, reg, 0x1);
> -}
> +void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
> +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
> +void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val);
> +u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg);
> +void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val);
> +u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg);
>
> static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
> {
> --
> 2.7.4
Seems harmless. After word replacement, ack for the whole patch:
Acked-by: Gustavo Pimentel
Thanks
Gustavo
Pimentel
On Tue, Apr 16, 2019 at 20:27:20, Vidya Sagar wrote:
> Add extended configuration space capability search API using struct dw_pcie *
> pointer
>
> Signed-off-by: Vidya Sagar
> ---
> Changes from [v2]:
> * None
>
> Changes from [v1]:
> * This is a new patch in v2 series
>
> drivers/pci/contro
r/dwc/pcie-designware.h
> index 86df36701a37..4ccd4c706ddb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -247,6 +247,8 @@ struct dw_pcie {
> #define to_dw_pcie_from_ep(endpoint) \
> container_of((endpoint), struct dw_pcie, ep)
>
> +u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
> +
> int dw_pcie_read(void __iomem *addr, int size, u32 *val);
> int dw_pcie_write(void __iomem *addr, int size, u32 val);
>
> --
> 2.17.1
With the replacement, you have my ack:
Acked-by: Gustavo Pimentel
Thanks,
Gustavo
On Wed, Apr 17, 2019 at 10:34:52, Vidya Sagar wrote:
> On 4/17/2019 2:57 PM, Gustavo Pimentel wrote:
> > On Tue, Apr 16, 2019 at 20:27:20, Vidya Sagar wrote:
> >
> >> Add extended configuration space capability search API using struct
> >> dw_pcie *
> >&
E_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1)
> +#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16)
> +#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17)
> +#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18)
> +
> +#define PCIE_PL_CHK_REG_ERR_ADDR
On Tue, Apr 16, 2019 at 20:27:18, Vidya Sagar wrote:
> Remove multiple write enable and disable sequences of dbi registers as
> Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
> DBI write-lock enable bit thereby not allowing any further writes to BAR-0
> register in conf
On Wed, Apr 24, 2019 at 6:19:53, Vidya Sagar wrote:
> Move PCIe config space capability search API to common DesignWare file
> as this can be used by both host and ep mode codes.
>
> Signed-off-by: Vidya Sagar
> Acked-by: Gustavo Pimentel
> ---
> Changes from [v4]:
>
-by: Vidya Sagar
> > Acked-by: Gustavo Pimentel
> > ---
> > Changes from [v3]:
> > * Rebased to linux-next top of the tree
> >
> > Changes from [v2]:
> > * None
> >
> > Changes from [v1]:
> > * Removed dw_pcie_find_next_ext_ca
;msi_irq) {
> + irq_set_chained_handler(pp->msi_irq, NULL);
> + irq_set_handler_data(pp->msi_irq, NULL);
> + }
>
> irq_domain_remove(pp->msi_domain);
> irq_domain_remove(pp->irq_domain);
>
Sounds good.
Acked-by: Gustavo Pimentel
Hi,
On 01/03/2019 05:04, Jisheng Zhang wrote:
> To avoid memory leak, we need to free the page for MSI in
> dw_pcie_free_msi().
>
> Signed-off-by: Jisheng Zhang
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 file
Look to Lucas Stach patch 3afc8299f39a ("PCI: dwc: skip MSI init if MSIs have
been explicitly disabled")
You need to change this to:
if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_enabled() && !pp->ops->msi_host_init)
> + dw_pcie_free_msi(pp);
> error:
> pci_free_host_bridge(bridge);
> return ret;
>
Sounds good, thanks.
Acked-by: Gustavo Pimentel
Hi,
On 01/03/2019 05:06, Jisheng Zhang wrote:
> Currently dwc host doesn't support the remove, but nothing prevent us
> from supporting it. Save the root bus for clean up work in driver
> remove code path.
>
> After this patch, the dwc host users could implement its remove as:
>
> static int foo
if (ret < 0)
> - goto error;
> + return ret;
> }
> }
>
> @@ -515,8 +512,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
> err_free_msi:
> if (IS_ENABLED(CONFIG_PCI_MSI) && !pp->ops->msi_host_init)
> dw_pcie_free_msi(pp);
> -error:
> - pci_free_host_bridge(bridge);
> return ret;
> }
>
>
Nice!
Acked-by: Gustavo Pimentel
On Thu, Feb 11, 2021 at 12:50:46, Krzysztof Wilczyński
wrote:
> Hi Gustavo,
>
> [...]
> > + * Typically this function will be called by the pci driver, which passes
>
> It would be "PCI" here.
Nicely catch.
>
> > + * through argument the 'struct pci_dev *' already pointing for the device
>
Add Documentation for dw-xdata-pcie driver.
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/dw-xdata-pcie.rst | 40
1 file changed, 40 insertions(+)
create mode 100644 Documentation/misc-devices/dw-xdata-pcie.rst
diff --git a/Documentation/misc
linux-...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Gustavo Pimentel (5):
misc: Add Synopsys DesignWare xData IP driver
misc: Add Synopsys DesignWare xData IP driver to Makefile and Kconfig
Documentation: misc-devices: Add Documentation for dw-xdata
Add Synopsys DesignWare xData IP driver. This driver enables/disables
the PCI traffic generator module pertain to the Synopsys DesignWare
prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/dw-xdata-pcie.c | 390 +++
1 file changed, 390 insertions
This patch describes the sysfs interface implemented on the dw-xdata-pcie
driver.
Signed-off-by: Gustavo Pimentel
---
Documentation/ABI/testing/sysfs-driver-xdata | 46
1 file changed, 46 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-xdata
Add Synopsys xData IP driver maintainer.
This driver aims to support Synopsys xData IP and is normally distributed
along with Synopsys PCIe EndPoint IP as a PCIe traffic generator (depends
of the use and licensing agreement).
Signed-off-by: Gustavo Pimentel
---
MAINTAINERS | 7 +++
1 file
Add Synopsys DesignWare xData IP driver to Makefile and Kconfig.
This driver enables/disables the PCIe traffic generator module
pertain to the Synopsys DesignWare prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/Kconfig | 10 ++
drivers/misc/Makefile | 1 +
2 files changed
Rework driver accordingly to Bjorn Helgaas's feedback
V6: Rework driver accordingly to Krzysztof Wilczy??ski's feedback
Cc: Vinod Koul
Cc: Dan Williams
Cc: Bjorn Helgaas
Cc: dmaeng...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-...@vger.kernel.org
Gustavo Pimentel (15):
generate a 64 bits message instead of two messages
of 32 bits.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-v0-core.c| 254 +++
drivers/dma/dw-edma/dw-edma-v0-debugfs.c | 48 +++---
drivers/dma/dw-edma/dw-edma-v0-regs.h| 149 +-
3
Fix comments offset characters' alignment to follow the same structure
of similar comments.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-v0-regs.h | 214 +-
1 file changed, 107 insertions(+), 107 deletions(-)
diff --git a/drivers/dma/dw
Add support for the HDMA feature.
This new feature enables the current eDMA IP to use a deeper prefetch
of the linked list, which reduces the algorithm execution latency
observed when loading the elements of the list, causing more stable
and higher data transfer.
Signed-off-by: Gustavo Pimentel
like container) defined by PCI-SIG that allows the one
or more proprietary capabilities defined by the vendor which aren't
standard or shared between the manufactures.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/pci.c | 34 ++
include/linux/
The latest eDMA IP development implements a Vendor-Specific Extended
Capability that contains the eDMA BAR, offset, map format, and the
number of read/write channels available.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 20 ---
drivers/dma/dw-edma/dw-edma
Add device_prep_interleave_dma() support to Synopsys DMA driver.
This feature implements a similar data transfer mechanism to the
scatter-gather implementation.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 85 ++
drivers/dma/dw
functional changes are expected.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-pcie.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c
b/drivers/dma/dw-edma/dw-edma-pcie.c
index 1ddea34..41384ff 100644
--- a/drivers/dma
It was added some extra checks to ensure that the driver doesn't try to
use more DMA channels than actually are available in hardware.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 21 +
drivers/dma/dw-edma/dw-edma-core.h | 2 ++
2 files ch
When the driver is compiled as a module and loaded if we try to unload
it, the Kernel shows a crash log. This Kernel crash is due to the
dma_async_device_unregister() call done after deleting the channels,
this patch fixes this issue.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw
its own linked list and data space well defined, which allows
different sizes and locations.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 51 +-
drivers/dma/dw-edma/dw-edma-core.h | 9 +-
drivers/dma/dw-edma/dw-edma-pcie.c | 185
Move struct dentry variable from static definition (dw-edma-v0-debugfs.c)
into dw_edma struct (dw-edma-core.h)
Also the variable was renamed from base_dir to debugfs.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 2 +-
drivers/dma/dw-edma/dw-edma-core.h
this solution is based on FPGA and might be subjected to
timmings constrains.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-pcie.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c
b/drivers
Reverting the applied patch because it caused a regression on
ARC700 platform (32 bits).
Fixes: 05655541c950 ("dmaengine: dw-edma: Fix scatter-gather address
calculation")
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 8
1 file changed, 4 insert
To keep code consistent, some comments with dma keyword written in lower
case are now in upper case.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-edma-core.c
b/drivers/dma
Currently, is missing a null check on a pcim_iomap_table() return value
and this can lead to a null pointer dereference if the desired BAR
wasn't mapped previously.
Fix this by adding a null check and returning -ENOMEM.
Addresses-Coverity: ("Dereference null return")
Signed-
c: Arnd Bergmann
Cc: Andrew Morton
Cc: Greg Kroah-Hartman
Cc: Jonathan Corbet
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Gustavo Pimentel (6):
misc: Add Synopsys DesignWare xData IP driver
misc: Add Synopsys DesignWare xData I
Add Synopsys DesignWare xData IP driver. This driver enables/disables
the PCI traffic generator module pertain to the Synopsys DesignWare
prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/dw-xdata-pcie.c | 394 +++
1 file changed, 394 insertions
Add Synopsys xData IP driver maintainer.
This driver aims to support Synopsys xData IP and is normally distributed
along with Synopsys PCIe EndPoint IP as a PCIe traffic generator (depends
of the use and licensing agreement).
Signed-off-by: Gustavo Pimentel
---
MAINTAINERS | 7 +++
1 file
Add Synopsys DesignWare xData IP driver to Kconfig.
This driver enables/disables the PCIe traffic generator module
pertain to the Synopsys DesignWare prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/Kconfig | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/misc
Add Documentation for dw-xdata-pcie driver.
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/dw-xdata-pcie.rst | 40
1 file changed, 40 insertions(+)
create mode 100644 Documentation/misc-devices/dw-xdata-pcie.rst
diff --git a/Documentation/misc
This patch describes the sysfs interface implemented on the dw-xdata-pcie
driver.
Signed-off-by: Gustavo Pimentel
---
Documentation/ABI/testing/sysfs-driver-xdata | 46
1 file changed, 46 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-xdata
To keep code consistent, some comments with dma keyword written in lower
case are now in upper case.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-edma-core.c
b/drivers/dma
When the driver is compiled as a module and loaded if we try to unload
it, the Kernel shows a crash log. This Kernel crash is due to the
dma_async_device_unregister() call done after deleting the channels,
this patch fixes this issue.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw
Add support for the HDMA feature.
This new feature enables the current eDMA IP to use a deeper prefetch
of the linked list, which reduces the algorithm execution latency
observed when loading the elements of the list, causing more stable
and higher data transfer.
Signed-off-by: Gustavo Pimentel
It was added some extra checks to ensure that the driver doesn't try to
use more DMA channels than actually are available in hardware.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 21 +
drivers/dma/dw-edma/dw-edma-core.h | 2 ++
2 files ch
Add Synopsys DesignWare xData IP driver to Makefile.
This driver enables/disables the PCIe traffic generator module
pertain to the Synopsys DesignWare prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/Makefile
Detected by CoverityScan CID 16555 ("Dereference null return")
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-pcie.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c
b/drivers/dma/dw-edma/dw-edma-pcie.c
ind
Reverting the applied patch because it caused a regression on
ARC700 platform (32 bits).
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-edma-core.c
b/drivers/dma/dw-edma
Move struct dentry variable from static definition (dw-edma-v0-debugfs.c)
into dw_edma struct (dw-edma-core.h)
Also the variable was renamed from base_dir to debugfs.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 2 +-
drivers/dma/dw-edma/dw-edma-core.h
Add device_prep_interleave_dma() support to Synopsys DMA driver.
This feature implements a similar data transfer mechanism to the
scatter-gather implementation.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-core.c | 85 ++
drivers/dma/dw
this solution is based on FPGA and might be subjected to
timmings constrains.
Signed-off-by: Gustavo Pimentel
---
drivers/dma/dw-edma/dw-edma-pcie.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c
b/drivers
create
their own and specific capability in the device config space.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/pci.c | 34 ++
include/linux/pci.h | 2 ++
include/uapi/linux/pci_regs.h | 6 ++
3 files changed, 42 insertions(+)
diff
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