M: Mans Rullgard
> --
> 2.16.3
>
>
> _______
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
clk) 1
> 9>,
> - <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1
> 18>;
> + <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1
> 6>,
> + <&CP110_LABEL(clk) 1 18>;
> clock-names = "pp_clk", "gop_clk",
> - "mg_clk", "axi_clk";
> + "mg_clk", "mg_core_clk", "axi_clk";
> marvell,system-controller = <&CP110_LABEL(syscon0)>;
> status = "disabled";
> dma-coherent;
> --
> 2.11.0
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
cooling-cells = <2>;
> + #cooling-cells = <2>;
> };
>
> gpio-leds {
> --
> 2.15.0.194.g9af6a3dea062
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
b>;
Same here
> + usb-phy = <&usb2_phy>;
> + status = "okay";
> + };
> +
Gregory
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
l,xmdio";
> reg = <0x12a600 0x10>;
> + clocks = <&CP110_LABEL(clk) 1 5>,
> + <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1
> 18>;
> status = "d
goto err_mg_clk;
> + goto err_mg_core_clk;
> }
>
> /* Get system's tclk rate */
> @@ -8851,6 +8862,10 @@ static int mvpp2_probe(struct platform_device *pdev)
> }
> err_axi_clk:
> clk_disable_unprepare(priv->axi_clk);
> +
> +err_mg_core_clk:
> + if (priv->hw_version == MVPP22)
> + clk_disable_unprepare(priv->mg_core_clk);
> err_mg_clk:
> if (priv->hw_version == MVPP22)
> clk_disable_unprepare(priv->mg_clk);
> @@ -8898,6 +8913,7 @@ static int mvpp2_remove(struct platform_device *pdev)
> return 0;
>
> clk_disable_unprepare(priv->axi_clk);
> + clk_disable_unprepare(priv->mg_core_clk);
> clk_disable_unprepare(priv->mg_clk);
> clk_disable_unprepare(priv->pp_clk);
> clk_disable_unprepare(priv->gop_clk);
> --
> 2.11.0
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
d0 ("net: mvpp2: Fix clock resource by adding an optional
> bus clock")
> Signed-off-by: Maxime Chevallier
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/net/ethernet/marvell/mvpp2.c | 15 ---
> 1 file changed, 8 insertions(+), 7 deletions(-)
Hi agin,
On mer., avril 25 2018, Gregory CLEMENT wrote:
> Hi Maxime,
>
> On mer., avril 25 2018, Maxime Chevallier
> wrote:
>
>> The Marvell XSMI controller needs 3 clocks to operate correctly :
>> - The MG clock (clk 5)
>> - The MG Core clock (c
ks,
Gregory
>
> thx!
> hofrat
>
> ___________
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
: 92ce45fb875d ("cpufreq: Add DVFS support for Armada 37xx")
Cc:
Reported-by: Christian Neubert
Reported-by: Ilias Apalodimas
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/armada-37xx-periph.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/clk/mvebu/a
>> > > was not the case.
>> > >
>> > > This patch fixes this issue, allowing to make the cpufreq support work
>> > > when the CPU clocks source are not the default ones.
>> > >
>> > > Fixes: 92ce45fb875d ("cpufreq: Add DVFS support f
h patches applied to mvebu/dt64
Thanks,
Gregory
> arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 7 +++
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi| 5 +
> 2 files changed, 12 insertions(+)
>
> --
> 2.20.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
interrupts = ;
> status = "disabled";
> };
> --
> 2.19.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
pcie";
> + };
> };
>
> eth0: ethernet@3 {
> --
> 2.19.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
> };
>
> /* J6 */
> --
> 2.19.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
#phy-cells = <1>;
> + };
> +
> + comphy2: phy@2 {
> + reg = <2>;
> + #phy-cells = <1>;
> + };
> +
0-espressobin.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> @@ -46,6 +46,7 @@
> /* J9 */
> &pcie0 {
> status = "okay";
> + phys = <&comphy1 0>;
> };
>
> /* J6 */
> --
> 2.19.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Hi,
> On Fri, 29 Jan 2021 17:01:35 +0100
> Gregory CLEMENT wrote:
>
>> Could you sent me the patch I don't have it in my emails boxes.
>
> https://lore.kernel.org/lkml/20201112032149.21906-1-chris.pack...@alliedtelesis.co.nz/raw
Applied on mvebu/arm
Thanks,
Gregory
ridge Peripheral Clock registers directly in this
> driver.
>
> [1] https://github.com/wtarreau/mhz
>
> Signed-off-by: Marek Behún
> Tested-by: Pali Rohár
> Tested-by: Tomasz Maciej Nowak
> Tested-by: Anders Trier Olesen
> Tested-by: Philip Soares
> Fixes: 92ce
vebu: armada-37xx-periph: add DVFS support for
> cpu clocks")
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/clk/mvebu/armada-37xx-periph.c | 28 --
> 1 file changed, 28 deletions(-)
>
> diff --git a/drivers/clk/mvebu/armada-37
: Marek Behún
> Signed-off-by: Pali Rohár
> Acked-by: Stephen Boyd
> Tested-by: Tomasz Maciej Nowak
> Tested-by: Anders Trier Olesen
> Tested-by: Philip Soares
> Fixes: 61c40f35f5cd ("clk: mvebu: armada-37xx-periph: Fix switching CPU rate
> from 300Mhz to 1.2GHz"
cpufreq: armada-37xx: fix frequency calculation for
> opp")
> Cc: sta...@vger.kernel.org
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/cpufreq/armada-37xx-cpufreq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cpu
nders Trier Olesen
> Tested-by: Philip Soares
> Fixes: 92ce45fb875d ("cpufreq: Add DVFS support for Armada 37xx")
> Cc: sta...@vger.kernel.org # 8db82563451f ("cpufreq: armada-37xx: fix
> frequency calculation for opp")
Acked-by: Gregory CLEMENT
Thanks,
Gregory
>
Pali Rohár writes:
> Variable cur_frequency in armada37xx_cpufreq_driver_init() is unused.
>
> Signed-off-by: Pali Rohár
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/cpufreq/armada-37xx-cpufreq.c | 10 +-
> 1 file changed, 1 insertion(+), 9 deletions
Tested-by: Anders Trier Olesen
> Tested-by: Philip Soares
> Fixes: 1c3528232f4b ("cpufreq: armada-37xx: Add AVS support")
> Cc: sta...@vger.kernel.org
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/cpufreq/armada-37xx-cpufreq.c | 37 +
> Tested-by: Anders Trier Olesen
> Tested-by: Philip Soares
> Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for
> cpu clocks")
> Cc: sta...@vger.kernel.org # 61c40f35f5cd ("clk: mvebu: armada-37xx-periph:
> Fix switching CPU rate from 300M
e7927b2 ("arm64: dts: marvell: armada-37xx: add nodes...")
> Cc: sta...@vger.kernel.org
> Cc: Gregory CLEMENT
> Cc: Miquel Raynal
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 3 ++-
> 1 file changed, 2 insertions(+),
09, 0x19) 0 0xf110 0x1
> - MBUS_ID(0x09, 0x15) 0 0xf111 0x1>;
> + MBUS_ID(0x09, 0x15) 0 0xf111 0x1
> + MBUS_ID(0x0c, 0x04) 0 0xf120 0x10>;
>
> internal-regs {
>
umentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
> create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c
>
> --
> 2.17.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
> @@ -8,7 +8,7 @@
> *
> */
> /*
> - * Schematic available at
> http://wiki.espressobin.net/tiki-download_file.php?fileId=200
> + * Schematic available at
> http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf
> */
>
> /dts-v1/;
> --
> 2.20.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
disabled";
> };
>
> - usb2: usb3@58000 {
> + usb2: usb@58000 {
> compatible = "marvell,armada-375-xhci";
> reg = <0x58000 0x2>,<0x5b880 0x80>;
>
gt; + CP11X_LABEL(usb3_1): usb@51 {
> compatible = "marvell,armada-8k-xhci",
> "generic-xhci";
> reg = <0x51 0x4000>;
> --
> 2.28.0
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
nand-on-flash-bbt;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@0 {
> + reg = <0x 0x0050>;
> + label = "u-boot";
> + };
> + partition@50{
> + reg = <0x0050 0x0040>;
> + label = "u-boot env";
> + };
> + partition@90{
> + reg = <0x0090 0x3F70>;
> + label = "user";
> + };
> + };
> + };
> +};
> +
> +&refclk {
> + clock-frequency = <2>;
> +};
> --
> 2.29.2
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
linux,default-trigger = "heartbeat";
> + };
> + };
> };
>
> &cp0_eth0 {
> @@ -27,3 +42,10 @@ &cp1_eth0 {
> managed = "in-band-status";
> sfp = <&sfp_eth1>;
> };
> +
> +&cp0_pinctrl {
> + cp0_led18_pins: led18-pins {
> + marvell,pins = "mpp33";
> + marvell,function = "gpio";
> + };
> +};
> --
> 2.29.2
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
/arm64/boot/dts/marvell/armada-8040.dtsi
> @@ -15,10 +15,6 @@ / {
> "marvell,armada-ap806";
> };
>
> -&smmu {
> - status = "okay";
> -};
> -
> &cp0_pcie0 {
> iommu-map =
> <0x0 &smmu 0x480 0x20>,
> --
> 2.25.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Allow Luton and Jaguar2 SoCs to use reset feature by adding the reset
node.
Signed-off-by: Gregory CLEMENT
---
arch/mips/boot/dts/mscc/jaguar2.dtsi | 5 +
arch/mips/boot/dts/mscc/luton.dtsi | 5 +
2 files changed, 10 insertions(+)
diff --git a/arch/mips/boot/dts/mscc/jaguar2.dtsi
b
-core
property support waiting for finding a butter solution for it.
Changelog:
v1 -> v2:
- Add binding documentation for the 2 new SoC
- Fix compatible string in name device tree node
- Add Acked-by from Alexande
Gregory
Gregory CLEMENT (3):
dt-bindings: reset: ocelot: Add Luton and Jagu
This adds the support for 2 others MIPS based VCore III SoCs: Luton
and Jaguar2.
Signed-off-by: Gregory CLEMENT
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/power/reset
This adds reset support for Luton and Jaguar2 in the ocelot-reset
driver. They are both MIPS based belonging to the Vcore III family.
Acked-by: Alexandre Belloni
Signed-off-by: Gregory CLEMENT
---
drivers/power/reset/ocelot-reset.c | 30 +++---
1 file changed, 27
1 -> v2:
- Convert the binding to yaml
- Squashed the patches adding new binding in a single one
Gregory CLEMENT (6):
dt-bindings: interrupt-controller: convert icpu intr bindings to
json-schema
dt-bindings: interrupt-controller: Add binding for few Microsemi
interrupt controllers
Add the Device Tree binding documentation for the Microsemi Jaguar2,
Luton and Serval interrupt controller that is part of the ICPU. It is
connected directly to the MIPS core interrupt controller.
Signed-off-by: Gregory CLEMENT
---
.../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
This patch extends irqchip driver for oceleot to be used with other
vcoreiii base platforms.
Acked-by: Alexandre Belloni
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-mscc-ocelot.c | 76 ++-
1 file changed, 54 insertions(+), 22 deletions(-)
diff --git a
This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Serval.
Based on a larger patch from Lars Povlsen
Acked-by: Alexandre Belloni
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-mscc-ocelot.c | 19 +++
1 file changed, 19
This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Jaguar2.
Based on a larger patch from Lars Povlsen
Acked-by: Alexandre Belloni
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-mscc-ocelot.c | 19 +++
1 file changed, 19
Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
Controller to YAML format
Signed-off-by: Gregory CLEMENT
---
.../mscc,ocelot-icpu-intr.txt | 21 ---
.../mscc,ocelot-icpu-intr.yaml| 60 +++
2 files changed, 60 insertions
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-mscc-ocelot.c | 38 +++
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-mscc-ocelot.c
b/drivers/irqchip/irq-mscc-ocelot.c
index 6d4029a2ded0..496f955b8fc4 100644
--- a/drivers
x driver cleanup when registration failed
>> cpufreq: armada-37xx: Fix determining base CPU frequency
>> cpufreq: armada-37xx: Remove cur_frequency variable
>> cpufreq: armada-37xx: Fix module unloading
>>
>> arch/arm64/boot/dts/marvell/armada-37xx.dtsi |
stop Cc-ing
> him.
>
> Cc: Andrew Lunn
> Cc: Sebastian Hesselbarth
> Cc: Gregory Clement
> Cc: Thomas Gleixner
> Cc: Thomas Petazzoni
> Signed-off-by: Marc Zyngier
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> CREDITS | 5 +
> MAINTAINERS
> +&cp0_eth0 {
> + status = "okay";
> + phy-mode = "10gbase-r";
> + phys = <&cp0_comphy4 0>;
> + local-mac-address = [ae 00 00 00 ff 00];
> + sfp = <&sfp_cp0_eth0>;
> + managed = "in-band-status";
> +};
&g
/* led2 is working only on v7 board */
> + status = "disabled";
> +
> + compatible = "gpio-leds";
> +
> + led2 {
> + label = "led2";
> + gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> + };
> };
>
> /* J9 */
> --
> 2.20.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
{
> + switch0port1: port@1 {
> + reg = <1>;
> + label = "lan0";
> + phy-handle = <&switch0phy0>;
> + };
> +
> + switch0port2: port@2 {
> + reg = <2>;
> + label = "lan1";
> + phy-handle = <&switch0phy1>;
> + };
> +
> + switch0port3: port@3 {
> + reg = <3>;
> + label = "lan2";
> + phy-handle = <&switch0phy2>;
> + };
> +
> + switch0port4: port@4 {
> + reg = <4>;
> + label = "lan3";
> + phy-handle = <&switch0phy3>;
> + };
> +
> + switch0port5: port@5 {
> + reg = <5>;
> + label = "wan";
> + phy-handle = <&extphy>;
> + phy-mode = "sgmii";
> + };
> + };
> +
> + mdio {
> + switch0phy3: switch0phy3@14 {
> + reg = <0x14>;
> + };
> + };
> +};
> --
> 2.27.0
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
This patch extends irqchip driver for oceleot to be used with other
vcoreiii base platforms.
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-mscc-ocelot.c | 76 ++-
1 file changed, 54 insertions(+), 22 deletions(-)
diff --git a/drivers/irqchip/irq-mscc
Add the Device Tree binding documentation for the Microsemi Jaguar2,
Luton and Serval interrupt controller that is part of the ICPU. It is
connected directly to the MIPS core interrupt controller.
Signed-off-by: Gregory CLEMENT
---
.../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Serval.
Based on a larger patch from Lars Povlsen
Acked-by: Alexandre Belloni
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-mscc-ocelot.c | 19 +++
1 file changed, 19
This patch extends irqchip driver for oceleot to be used with an other
vcoreiii base platform: Luton.
For this platform there is a few differences:
- the interrupt must be enabled for the parent controller
- there is no trigger register needed to be managed
Signed-off-by: Gregory CLEMENT
This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Jaguar2.
Based on a larger patch from Lars Povlsen
Acked-by: Alexandre Belloni
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-mscc-ocelot.c | 19 +++
1 file changed, 19
Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
Controller to YAML format
Signed-off-by: Gregory CLEMENT
---
.../mscc,ocelot-icpu-intr.txt | 21 ---
.../mscc,ocelot-icpu-intr.yaml| 60 +++
2 files changed, 60 insertions
orm and seemed in the end useless.
- Add acked-by from Alexandre on the last 2 patches.
v2 -> v3
- Fix new-line-at-end-of-file error in the yaml file
v1 -> v2:
- Convert the binding to yaml
- Squashed the patches adding new binding in a single one
Gregory CLEMENT (6):
dt-bindings:
Hi Tomasz,
On 23/02/2014 19:46, Tomasz Figa wrote:
> Hi Gregory,
>
> On 10.02.2014 18:42, Gregory CLEMENT wrote:
>> Until now the clock providers were initialized in the order found in
>> the device tree. This led to have the dependencies between the clocks
>> not
BREZILLON
Signed-off-by: Gregory CLEMENT
Signed-off-by: Boris BREZILLON
---
Mike,
This patch depend on the patch "clk: return probe defer when DT clock
not yet ready": http://article.gmane.org/gmane.linux.kernel/1643466
If for any reason you don't want to take it, then I w
ing" fixed this regression.
I got this issue in the driver drivers/i2c/busses/i2c-mv64xxx.c.
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
--
To unsubscribe from this
On 07/11/2013 09:59, Jisheng Zhang wrote:
> This symbol is used only in this file. The patch fix the following
> sparse warning:
> warning: symbol 'of_cpu_clk_setup' was not declared. Should it be static?
>
> Signed-off-by: Jisheng Zhang
Acked-by: Gregory CL
ol 'armada_xp_smp_prepare_cpus' was not declared. Should it be static?
> arch/arm/mach-mvebu/hotplug.c:24:12: warning:
> symbol 'armada_xp_cpu_die' was not declared. Should it be static?
>
> Signed-off-by: Jisheng Zhang
There will be some conflicts with my CPU I
On 07/11/2013 04:08, Jisheng Zhang wrote:
> Add of_node_put to properly decrement the refcount when we are
> done using a given node.
>
> Signed-off-by: Jisheng Zhang
> Reviewed-by: Ezequiel Garcia
Seems ok for me too
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> --
On 07/11/2013 04:08, Jisheng Zhang wrote:
> Add of_node_put to properly decrement the refcount when we are
> done using a given node.
>
> Signed-off-by: Jisheng Zhang
> Reviewed-by: Ezequiel Garcia
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/bus/mvebu-m
gt; Acked-by: Jason Cooper
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/pinctrl/mvebu/pinctrl-mvebu.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
> b/drivers/pinctrl/mvebu/pinctrl-mve
: Gregory CLEMENT
---
Hi,
I have received this board only recently, so that why its device tree
comes only now. This patch should not cause any trouble to other part
of the kernel, so that's why I think it is reasonable to have it in
3.15.
Thanks,
Gregory
arch/arm/boot/dts/Mak
Hi Andrew,
On 06/03/2014 14:14, Andrew Lunn wrote:
> On Thu, Mar 06, 2014 at 01:11:08PM +0100, Gregory CLEMENT wrote:
>> The Armada 385 RD board is the reference design board from Marvell
>> for the Armada 385 SoC. This commit adds a Device Tree description for
>> this boa
th0: ethernet@7 {
> }
> eth1: ethernet@74000 {
> }
>
> This at least works for i2c devices. The pdev->id is set using the
> alias number.
Well I think it doesn't work with ethernet devices because we already do
this in aramda-38x.dtsi:
aliases {
eth2 = ð2;
>> };
>>
>> eth1: ethernet@3 {
>> }
>> eth2: ethernet@34000 {
>> }
>> eth0: ethernet@7 {
>> }
>
> Ah, Erm, O.K.
>
> It seems to be an i2c thing. Take a look at i2c_add_adapter().
>
>
: Gregory CLEMENT
---
Changelog:
v1 -> v2:
- used the phy-mode "rgmii-id" to be able to work with the Marvell PHY
driver enabled
- put the ethernet nodes in the address order, as it has no effect to
change ti at this level (should be done at dtsi level)
- inverted the phy devic
On 06/03/2014 15:51, Gregory CLEMENT wrote:
> On 06/03/2014 15:46, Andrew Lunn wrote:
>>>>>> I think you can use aliases to get the order correct, independent of
>>>>>> how you list them in DT. That should be a lot safer than assuming
>>&g
Hi Mike,
On 24/02/2014 19:10, Gregory CLEMENT wrote:
> Until now the clock providers were initialized in the order found in
> the device tree. This led to have the dependencies between the clocks
> not respected: children clocks could be initialized before their
> parent clocks.
>
The debug trace in the atmel_usba_stop function made the assumption
that the driver pointer passed in parameter was not NULL. Since the
commit "usb: gadget: udc-core: fix a regression during gadget driver
unbinding", it was no more always true. This lead to a kernel crash.
This commit now use the
On 28/02/2014 16:50, Alexandre Belloni wrote:
> Hi Gregory,
>
> On 28/02/2014 at 15:34:01 +0100, Gregory CLEMENT wrote :
>> The debug trace in the atmel_usba_stop function made the assumption
>> that the driver pointer passed in parameter was not NULL. Since the
>> co
On 03/03/2014 17:33, Felipe Balbi wrote:
> On Fri, Feb 28, 2014 at 03:34:01PM +0100, Gregory CLEMENT wrote:
>> The debug trace in the atmel_usba_stop function made the assumption
>> that the driver pointer passed in parameter was not NULL. Since the
>> commit "us
unbinding)
Cc: sta...@vger.kernel.org # v3.2+
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2
Fixed the signature block in the commit log
drivers/usb/gadget/atmel_usba_udc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/gadget/atmel_usba_udc.c
Hi Thomas,
On 07/03/2014 18:17, Thomas Gleixner wrote:
> On Fri, 7 Mar 2014, Gregory CLEMENT wrote:
>
>> On 06/03/2014 20:05, Jason Cooper wrote:
>>> Thomas,
>>>
>>> nit: s/armanda/armada/ in the patch subject.
>>>
>>> Gregory,
>>
On 18/03/2014 21:55, Thomas Gleixner wrote:
> On Tue, 18 Mar 2014, Gregory CLEMENT wrote:
>> On 07/03/2014 18:17, Thomas Gleixner wrote:
>>> It might be the readback of the routing register. I don't have the
>>> datasheet of this.
>>
>> Sorry for the d
d for 3.15 if possible.
Thanks,
Gregory
Gregory CLEMENT (4):
clk: mvebu: add clock support for Armada 375
dt: Update binding information for mvebu core clocks with Armada 375
dt: Update binding information for mvebu gating clocks with Armada 375
clk: mvebu: add clock support for Armada 38
Add the binding information for the gating clocks of the Armada 375 SoCs
Signed-off-by: Gregory CLEMENT
Reviewed-by: Thomas Petazzoni
---
.../bindings/clock/mvebu-gated-clock.txt | 31 +-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/Documentation
Add the clock support for the new SoCs Armada 380 and Armada 385:
core clocks and gating clocks.
Signed-off-by: Gregory CLEMENT
Reviewed-by: Thomas Petazzoni
---
drivers/clk/mvebu/Kconfig | 4 +
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-38x.c | 167
From: Thomas Petazzoni
Add the binding information for the core clocks of the Armada 380 and
Armada 385 SoCs
Signed-off-by: Thomas Petazzoni
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt | 7 +++
1 file changed, 7 insertions(+)
diff
Add the binding information for the core clocks of the Armada 375 SoCs
Signed-off-by: Gregory CLEMENT
Reviewed-by: Thomas Petazzoni
---
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings
From: Thomas Petazzoni
Add the binding information for the gating clocks of the Armada 380
SoCs and the Armada 385 SoCs.
Signed-off-by: Thomas Petazzoni
Signed-off-by: Gregory CLEMENT
---
.../bindings/clock/mvebu-gated-clock.txt | 36 +++---
1 file changed, 32
Add the clock support for the new SoC Armada 375: core clocks and
gating clocks.
Signed-off-by: Gregory CLEMENT
Reviewed-by: Thomas Petazzoni
---
drivers/clk/mvebu/Kconfig | 4 +
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-375.c | 184
BREZILLON
Signed-off-by: Gregory CLEMENT
---
Since the v1, I have merged the strict dependency check from Boris.
And of course tested on my Armada 370 and Armada XP based board
drivers/clk/clk.c | 109 --
1 file changed, 106 insertions(+), 3
{
.compatible = "foo,bar-controller",
},
[...]
instead of
static struct of_device_id of_system_controller_table[] = {
{
.compatible = "foo,bar",
.data = (void *) &bar_controller,
},
[...]
This test is very paranoid,
gt; +
> void __init at91rm9200_dt_initialize(void)
> {
> at91_dt_ramc();
> @@ -506,6 +528,7 @@ void __init at91_dt_initialize(void)
> at91_dt_rstc();
> at91_dt_ramc();
> at91_dt_shdwc();
> + at91_dt_matrix();
>
> /* Init clock subsystem */
>
+
> arch/arm/boot/dts/at91sam9261ek.dts | 204 ++
> arch/arm/configs/at91_dt_defconfig | 2 +
> arch/arm/mach-at91/Kconfig | 1 -
> arch/arm/mach-at91/at91sam9261.c| 25 +-
> arch/arm/mach-at91/setup.c | 23 ++
> drivers/pinctrl/pin
d the SoC ID of a board without any PCI device and
then without the PCI core support.
Signed-off-by: Gregory CLEMENT
---
drivers/of/Kconfig | 4
drivers/of/address.c | 8 +---
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
oc_id available even without the
PCI support. It should go to the mvebu tree.
Thanks,
Gregory CLEMENT (2):
of: Allows to use the PCI translator without the PCI core
ARM: mvebu: Allows to get the SoC ID even without PCI enabled
arch/arm/mach-mvebu/Kconfig | 1 +
drivers/of/Kconfig
mvebu platforms.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 5e269d7263ce..df9e7d270810 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@
de la Garza
Acked-by: Gregory CLEMENT
> ---
> arch/arm/boot/compressed/atags_to_fdt.c |3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/compressed/atags_to_fdt.c
> b/arch/arm/boot/compressed/atags_to_fdt.c
> index d1153c8..75b6
On 03/04/2014 10:16, Daniel Lezcano wrote:
> On 03/28/2014 12:13 PM, Gregory CLEMENT wrote:
>> Add the wfi, cpu idle and cpu deep idle power states support for the
>> Armada XP SoCs.
>>
>> All the latencies and the power consumption values used at the
>> "ar
Hi Paul,
On 06/04/2014 11:37, Paul Bolle wrote:
> On Sat, 2014-04-05 at 20:04 +0100, Arnd Bergmann wrote:
>> Gregory CLEMENT (1):
>> ARM: mvebu: add initial support for the Armada 375 SOCs
>>
>> [...]
>>
>> Thomas Petazzoni (7):
>> [...]
Hi Felipe,
On 20/04/2014 05:20, Felipe Balbi wrote:
> On Fri, Apr 18, 2014 at 12:22:37PM +0200, Gregory CLEMENT wrote:
>> For the armada 38x SoCs which come with an xhci controller, specific
>> initialization must be done during probe, especially in relation with
>
Hi Thomas,
On 18/03/2014 22:04, Gregory CLEMENT wrote:
> On 18/03/2014 21:55, Thomas Gleixner wrote:
>> On Tue, 18 Mar 2014, Gregory CLEMENT wrote:
>>> On 07/03/2014 18:17, Thomas Gleixner wrote:
>>>> It might be the readback of the routing register. I don
can handle 8GB. But the DT won't take 64bit values.
> I'm not sure how to get it in. I'll look around for examples.
You can have a look on what we did for Armada XP:
arch/arm/boot/dts/armada-370-xp.dtsi
arch/arm/boot/dts/armada-xp.dtsi
arch/arm/boot/dts/armada-xp-gp.dts
I c
view it seems sensible but I am not an
DT expert.
Grégory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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