7;t appear:
GAIN 0x30 or 0x92 should be 0x82(thcal maybe?)
Can someone clarify this?
Maybe M06 or M09 are a custom firmware for focaltech ft5x,
then it has different registers?
Thanks in advance and
kind regards to everybody
--
Giulio Benetti
R&D Manager &
Advanced Research
MICRONOVA SRL
S
Hi Andy,
Il 18/07/2018 18:26, Andy Shevchenko ha scritto:
On Wed, Jul 18, 2018 at 5:06 PM, Giulio Benetti
wrote:
+ int ret;
+
+ ret = kstrtobool(buf, &freq_test_en);
+ if (ret == -EINVAL) {
What kind of other error code you may expect and why they are not
considere
Il 20/07/2018 14:53, Andy Shevchenko ha scritto:
On Thu, Jul 19, 2018 at 9:19 PM, Giulio Benetti
wrote:
Hi Andy,
Il 18/07/2018 18:26, Andy Shevchenko ha scritto:
On Wed, Jul 18, 2018 at 5:06 PM, Giulio Benetti
wrote:
+ int ret;
+
+ ret = kstrtobool(buf, &freq_tes
Il 20/07/2018 15:43, Rob Herring ha scritto:
On Wed, Jul 18, 2018 at 04:09:43PM +0200, Giulio Benetti wrote:
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti
---
drivers/rtc/rtc-ds1307.c | 77
1 file changed, 77 insertions(+)
diff --git a
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti
Signed-off-by: Alexandre Belloni
---
drivers/rtc/rtc-ds1307.c | 2 +-
1
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti
---
V10 =>
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti
Reviewed-by: Rob Herring
Signed-off-by: Alexandre Belloni
---
.../devicetree/bindings/rtc/rtc
Hi,
Il 22/01/2018 21:27, Giulio Benetti ha scritto:
Hi,
Il 22/01/2018 09:51, Maxime Ripard ha scritto:
On Sat, Jan 20, 2018 at 07:50:21PM +0100, Giulio Benetti wrote:
On previous handling, if specified DRM_MODE_FLAG_N*SYNC,
it was ignored,
because only PHSYNC and PVSYNC were taken into
Hi,
Il 24/01/2018 18:38, Giulio Benetti ha scritto:
Hi,
Il 22/01/2018 21:27, Giulio Benetti ha scritto:
Hi,
Il 22/01/2018 09:51, Maxime Ripard ha scritto:
On Sat, Jan 20, 2018 at 07:50:21PM +0100, Giulio Benetti wrote:
On previous handling, if specified DRM_MODE_FLAG_N*SYNC,
it was ignored
Hi,
Il 25/01/2018 16:21, Maxime Ripard ha scritto:
Hi,
On Wed, Jan 24, 2018 at 08:37:28PM +0100, Giulio Benetti wrote:
Hi,
Il 24/01/2018 18:38, Giulio Benetti ha scritto:
Hi,
Il 22/01/2018 21:27, Giulio Benetti ha scritto:
Hi,
Il 22/01/2018 09:51, Maxime Ripard ha scritto:
On Sat, Jan
ll-ve, pll-video1.
It only depends on 24Mhz main clock.
Remove all pll parents from gpu_parents_sun7i except "pll-gpu".
Signed-off-by: Giulio Benetti
---
drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-su
Hi,
Il 31/01/2018 09:43, Maxime Ripard ha scritto:
Hi,
On Wed, Jan 31, 2018 at 12:23:59AM +0100, Giulio Benetti wrote:
When mali.ko is inserted, it set default clocks and call all parent
clocks to stay into range, causing pll-video0 to change and
subsequently to change dclk to wrong
Include correct clock header sun7i-a20-ccu.h
instead of sun4i-a20-ccu.h.
Including sun4i header instead of sun7i
prevents using sun7i specific defines.
Substitute header inclusion in sun7i-a20.dtsi
using right one.
Signed-off-by: Giulio Benetti
---
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
1
Il 01/02/2018 16:19, Maxime Ripard ha scritto:
Hi,
On Wed, Jan 31, 2018 at 08:31:26PM +0100, Giulio Benetti wrote:
Include correct clock header sun7i-a20-ccu.h
instead of sun4i-a20-ccu.h.
You should wrap at 72 characters.
Ok, keep in mind for next patches. Thanks
Including sun4i header
Il 01/02/2018 11:14, Maxime Ripard ha scritto:
On Sat, Jan 27, 2018 at 11:07:09PM +0100, Giulio Benetti wrote:
I don't really know what the polarity of D0 would be just by
judging at that capture, but we would have noticed if the colors
were inverted for quite some time now.
D0-D2
Hi,
Il 01/02/2018 13:45, Maxime Ripard ha scritto:
On Wed, Jan 31, 2018 at 01:05:38PM +0100, Giulio Benetti wrote:
Hi,
Il 31/01/2018 09:43, Maxime Ripard ha scritto:
Hi,
On Wed, Jan 31, 2018 at 12:23:59AM +0100, Giulio Benetti wrote:
When mali.ko is inserted, it set default clocks and call
o, as I've checked with scope on A20,
if (flags & PVSYNC) then SUN4I_TCON0_IO_POL_VSYNC_POSITIVE
must be set, as name suggests.
It seems all display io polarities starts inverted if 0.
Signed-off-by: Giulio Benetti
PVSYNC and PHSYNC only
Signed-off-by: Giulio Benetti
---
dr
Can't set dclk polarity on sun4i.
Handle both positive and negative dclk polarity,
according to bus_flags.
Signed-off-by: Giulio Benetti
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon
Hi,
Il 22/01/2018 09:51, Maxime Ripard ha scritto:
On Sat, Jan 20, 2018 at 07:50:21PM +0100, Giulio Benetti wrote:
On previous handling, if specified DRM_MODE_FLAG_N*SYNC,
it was ignored,
because only PHSYNC and PVSYNC were taken into account.
DRM_MODE_FLAG_P*SYNC and DRM_MODE_FLAG_N*SYNC are
Hi,
Il 26/01/2018 15:56, Maxime Ripard ha scritto:
On Thu, Jan 25, 2018 at 05:50:18PM +0100, Giulio Benetti wrote:
On Sat, Jan 20, 2018 at 07:50:21PM +0100, Giulio Benetti wrote:
On previous handling, if specified DRM_MODE_FLAG_N*SYNC,
it was ignored,
because only PHSYNC and PVSYNC were taken
Il 26/01/2018 16:55, Giulio Benetti ha scritto:
Hi,
Il 26/01/2018 15:56, Maxime Ripard ha scritto:
On Thu, Jan 25, 2018 at 05:50:18PM +0100, Giulio Benetti wrote:
On Sat, Jan 20, 2018 at 07:50:21PM +0100, Giulio Benetti wrote:
On previous handling, if specified DRM_MODE_FLAG_N*SYNC,
it was
Hi,
Il 26/03/2018 12:01, Maxime Ripard ha scritto:
Hi,
On Sun, Mar 25, 2018 at 04:09:13PM +0200, Paul Kocialkowski wrote:
Le mercredi 21 mars 2018 à 21:03 +0100, Giulio Benetti a écrit :
The A20 supports RGB888 with H/V sync from LCD0. Add a pinmux setting
for the needed pins.
Signed-off-by
Hi,
Il 27/03/2018 00:24, Rob Herring ha scritto:
On Wed, Mar 21, 2018 at 09:03:07PM +0100, Giulio Benetti wrote:
This adds a vendor prefix "cdtech" for CDTech(H.K.) Electronics Limited
Would be good to have website and/or info about what this company does.
Do you mean to have it
interface
- same as above, call lcd0-rgb666, take care about using "-" instad of
"_" that can cause DTC warnings.
- remove @0 since only this set can achieve LCD0 RGB666, and I
don't think there will be other combinations.
Kind regards
--
Giulio Benetti
CTO
MICRONOV
Hi,
Il 12/04/2018 01:09, Paul Kocialkowski ha scritto:
Hi,
Le jeudi 12 avril 2018 à 00:22 +0200, Giulio Benetti a écrit :
Hi,
Il 10/04/2018 23:31, Paul Kocialkowski ha scritto:
This adds the pins definition for RGB666 LCD panels on the A20. It
was
imported from the A33 definition, that
Signed-off-by: Giulio Benetti
---
.../display/panel/cdtech,s043wq26h-ct7.txt | 7 ++
drivers/gpu/drm/panel/panel-simple.c | 28 ++
2 files changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/cdtech
sed jtag pins
HMI is supplied from +12Vdc.
Ethernet is absent, so for debugging, need to enable rndis on Usb otg
port through an A-A usb cable.
It comes in different flavours for connector types and can be found with
umounted features as requested by customers.
Signed-off-by: Giulio
The A20 supports RGB888 with H/V sync from LCD0. Add a pinmux setting
for the needed pins.
Signed-off-by: Giulio Benetti
---
arch/arm/boot/dts/sun7i-a20.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index
This adds a vendor prefix "micronova" for Micronova srl
Signed-off-by: Giulio Benetti
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindi
This adds a vendor prefix "cdtech" for CDTech(H.K.) Electronics Limited
Signed-off-by: Giulio Benetti
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/
exposed jtag pins
HMI is supplied from +12Vdc.
Ethernet is absent, so for debugging, need to enable rndis on Usb otg
port through an A-A usb cable.
It comes in different flavours for connector types and can be found with
umounted features as requested by customers.
Signed-off-by: Giulio
Signed-off-by: Giulio Benetti
---
.../display/panel/cdtech,s070wv95-ct16.txt | 7 ++
drivers/gpu/drm/panel/panel-simple.c | 27 ++
2 files changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/cdtech,s070wv95
The H3 has an ARM Mali 400 GPU, so add binding to our DT.
Signed-off-by: Giulio Benetti
---
.../devicetree/bindings/gpu/arm,mali-utgard.txt| 1 +
arch/arm/boot/dts/sun8i-h3.dtsi| 27 ++
2 files changed, 28 insertions(+)
diff --git a/Documentation
mode_valid function is missing for lvds.
Add it making it pointed by encoder helper functions.
Signed-off-by: Giulio Benetti
---
drivers/gpu/drm/sun4i/sun4i_lvds.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_lvds.c
b
inter.
Signed-off-by: Giulio Benetti
---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c
b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index b8da5a5..f2fa1f2 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/dr
, but it divides
also dclk by 2.
This patch is a way to avoid quirks all around TCON and DOTCLOCK drivers
for using A33 90° phase divided by 2 and consequently increase code
complexity.
Signed-off-by: Giulio Benetti
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 +
1 file ch
Hi,
Il 14/03/2018 09:05, Maxime Ripard ha scritto:
On Tue, Mar 13, 2018 at 11:16:45AM +0100, Giulio Benetti wrote:
The H3 has an ARM Mali 400 GPU, so add binding to our DT.
Signed-off-by: Giulio Benetti
How was this tested?
I wanted you asked me about this to ask you:
if I can't te
Hello Thierry,
Il 27/09/2018 13:59, Thierry Reding ha scritto:
On Tue, Jul 31, 2018 at 01:11:12AM +0200, Giulio Benetti wrote:
Add CDTech 4.3" S043WQ26H-CT7 support
Add CDTech 7" S070WV95-CT16 support
Giulio Benetti (5):
dt-bindings: Add vendor prefix for CDTech(H.K.) Electroni
If rs485 is enabled and RTS_AFTER_SEND is set on startup need to keep
TIOCM_RTS asserted to keep rs485 transceiver in RX when idle.
Check if rs485 is on and RTS_AFTER_SEND is set and mask port->mctrl with
TIOCM_RTS too and not only TIOCM_DTR.
Signed-off-by: Giulio Benetti
---
drivers/
Need to use rs485 transceiver so let's use existing em485 485 emulation
layer on top of 8250.
Add rs485_config callback to port.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_dw.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/driver
When rs485 enabled and RTS_AFTER_SEND set on startup, need to preserve
mctrl status, because later functions will call set_mctrl passing
port->mctrl=0 overriding rts status, resulting in rts pin in
transmission when idle.
Make mctrl reflect rts pin state.
Signed-off-by: Giulio Bene
Need to handle rs485 with 8250_dw port.
Use existing em485 emulation layer for 8250 taking care to fix some bug
and taking care especially of RTS_AFTER_SEND case.
Giulio Benetti (8):
serial: 8250_dw: add em485 support
serial: 8250_dw: allow enable rs485 at boot time
serial: 8250: Copy
with RTS_AFTER_SEND set, if so return -EBUSY in
rpm_suspend,
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_dw.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_dw.c
b/drivers/tty/serial/8250/8250_dw.c
index 888280ff5451..6b0ee6dc8ad0 100644
Some 8250 ports only have TEMT interrupt, so current implementation
can't work for ports without it. The only chance to make it work is to
loop-read on LSR register.
With NO TEMT interrupt check if both TEMT and THRE are set looping on
LSR register.
Signed-off-by: Giulio Benetti
---
dr
RS485 can modify mctrl on startup, especially when RTS_AFTER_SEND is on
TIOCM_RTS is set, then need to keep it set when registering port.
Copy mctrl to new port too.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a
If "linux,rs485-enabled-at-boot-time" is specified need to setup 485
in probe function.
Call uart_get_rs485_mode() to get rs485 configuration, then call
rs485_config() callback directly to setup port as rs485.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_dw.c |
em485 gets lost during serial8250_register_8250_port().
Copy em485 to final uart port.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/8250/8250_core.c
b/drivers/tty/serial/8250/8250_core.c
index
It can be useful to override 8250 mctrl lines with gpios, for rts on
rs485 for example, when rts is not mapped correctly to HW RTS pin.
Enable SERIAL_MCTRL_GPIO by default.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a
Sometimes mctrl signals can be connected to pins different from HW ones.
User serial_mctrl_gpio helpers to align HW signals(RTS, CTS, etc.) with
gpios-rts, gpios-cts etc.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_core.c | 6 ++
drivers/tty/serial/8250/8250_port.c | 18
e-checked the signals using another display:
"innolux,at043tn24" that has a more rounded clock frequency, so it's
accepted by drm and **signals are correct**.
Unfortunately I don't have your same display here to test, so I can't
help you about that precise panel.
Sorry.
B
Il 13/12/2018 04:08, Jonathan Liu ha scritto:
Hi Giulio,
On Wed, 12 Dec 2018 at 04:20, Giulio Benetti
wrote:
Hi Jonathan,
Il 11/12/2018 11:49, Jonathan Liu ha scritto:
Hi Giulio,
On Thu, 6 Dec 2018 at 22:00, Giulio Benetti
wrote:
Hi Jonathan,
Il 06/12/2018 08:29, Jonathan Liu ha
Il 13/12/2018 12:58, Giulio Benetti ha scritto:
Il 13/12/2018 04:08, Jonathan Liu ha scritto:
Hi Giulio,
On Wed, 12 Dec 2018 at 04:20, Giulio Benetti
wrote:
Hi Jonathan,
Il 11/12/2018 11:49, Jonathan Liu ha scritto:
Hi Giulio,
On Thu, 6 Dec 2018 at 22:00, Giulio Benetti
wrote:
Hi
Hi Jonathan,
Il 11/12/2018 11:49, Jonathan Liu ha scritto:
Hi Giulio,
On Thu, 6 Dec 2018 at 22:00, Giulio Benetti
wrote:
Hi Jonathan,
Il 06/12/2018 08:29, Jonathan Liu ha scritto:
Hi Giulio,
On Thu, 15 Feb 2018 at 17:54, Giulio Benetti
wrote:
Differently from other Lcd signals, HSYNC
Forgot to ask you,
Il 11/12/2018 18:20, Giulio Benetti ha scritto:
Hi Jonathan,
Il 11/12/2018 11:49, Jonathan Liu ha scritto:
Hi Giulio,
On Thu, 6 Dec 2018 at 22:00, Giulio Benetti
wrote:
Hi Jonathan,
Il 06/12/2018 08:29, Jonathan Liu ha scritto:
Hi Giulio,
On Thu, 15 Feb 2018 at 17:54
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti
---
drivers/rtc
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti
---
drivers/rtc/rtc-ds1307.c | 2 +-
1 file changed, 1 insertion(+), 1
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti
---
drivers/rtc/rtc-ds1307.c | 77
1 file changed, 77 insertions(+)
diff --git a
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti
---
.../devicetree/bindings/rtc/rtc-ds1307.txt | 1 +
drivers/rtc/rtc-ds1307.c
Hi,
please discard this patchset as I didn't add v7 to series.
Sorry.
Giulio
Il 18/07/2018 10:41, Giulio Benetti ha scritto:
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Be
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti
---
V6 => V7:
* changed PPM to PPB as rtc sysfs offset handles PPB
drivers/rtc/rtc-ds1307.c |
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti
---
V6 => V7
* already applied
.../devicetree/bindings/rtc/rtc-ds1307.txt | 1 +
driv
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti
---
drivers/rtc
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti
---
V6 => V7:
* already applied
drivers/rtc/rtc-ds1307.c | 2 +-
1 f
Hi Alexandre,
Il 18/07/2018 10:49, Giulio Benetti ha scritto:
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti
---
V6 => V7:
* changed PPM to PPB as rtc sysfs offset hand
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti
---
drivers/rtc
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti
---
drivers/rtc/rtc-ds1307.c | 2 +-
1 file changed, 1 insertion(+), 1
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti
---
.../devicetree/bindings/rtc/rtc-ds1307.txt | 1 +
drivers/rtc/rtc-ds1307.c
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti
---
V7 => V8:
* use BIT() and GENMASK() instead of raw value 0x
drivers/rtc/rtc-ds1307.c |
Il 18/07/2018 11:22, Giulio Benetti ha scritto:
+#define M41TXX_REG_CONTROL 0x07
+# define M41TXX_BIT_OUT BIT(7)
+# define M41TXX_BIT_FTBIT(6)
+# define M41TXX_BIT_CALIB_SIGNBIT(5)
+# define M41TXX_M_CALIBRATION GENMASK(5, 0)
This must be
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti
---
drivers/rtc/rtc-ds1307.c | 2 +-
1 file changed, 1 insertion(+), 1
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti
---
drivers/rtc
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti
---
V8 => V9:
* fix GENMASK() to get 0x1f, it must be GENMASK(4, 0)
drivers/rtc/rtc-ds1307.c |
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti
---
.../devicetree/bindings/rtc/rtc-ds1307.txt | 1 +
drivers/rtc/rtc-ds1307.c
Hi Andy,
Il 18/07/2018 14:47, Andy Shevchenko ha scritto:
On Wed, Jul 18, 2018 at 12:40 PM, Giulio Benetti
wrote:
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti
---
.../devicetree/bindings/rtc/rtc-ds1307.txt | 1 +
drivers/rtc/rtc-ds1307.c
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti
---
drivers/rtc/rtc-ds1307.c | 2 +-
1 file changed, 1 insertion(+), 1
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti
---
drivers/rtc/rtc-ds1307.c | 77
1 file changed, 77 insertions(+)
diff --git a
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti
---
drivers/rtc
Add Andy in Cc
Il 18/07/2018 16:09, Giulio Benetti ha scritto:
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if
Il 18/07/2018 18:26, Andy Shevchenko ha scritto:
On Wed, Jul 18, 2018 at 5:09 PM, Giulio Benetti
wrote:
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or
er details are listed in single patches
V3->V4:
* fixed binding compatible string as suggested by Jonathan Neuschäfer
---
Giulio Benetti (3):
dt-bindings: Add Hycon Technology vendor prefix
dt-bindings: touchscreen: Add HY46XX bindings
Input: add driver for the Hycon HY46XX touchpanel se
Update Documentation/devicetree/bindings/vendor-prefixes.yaml to
include "hycon" as a vendor prefix for "Hycon Technology".
Company website: https://www.hycontek.com/
Signed-off-by: Giulio Benetti
Reviewed-by: Jonathan Neuschäfer
---
Documentation/devicetree/bindings/vend
This patch adds support for Hycon HY46XX.
Signed-off-by: Giulio Benetti
---
V1->V2:
* removed proximity-sensor-switch property according to previous patch
As suggested by Dmitry Torokhov
* moved i2c communaction to regmap use
* added macro to avoid magic number
* removed cmd variable that co
This adds device tree bindings for the Hycon HY46XX touchscreen series.
Signed-off-by: Giulio Benetti
---
V1->V2:
As suggested by Rob Herring:
* fixed $id: address
* added "hycon," in front of every custom property
* changed all possible property to boolean type
* removed proximity-
Hello Rob, All,
On 4/6/21 3:24 PM, Rob Herring wrote:
On Fri, 02 Apr 2021 18:16:26 +0200, Giulio Benetti wrote:
This adds device tree bindings for the Hycon HY46XX touchscreen series.
Signed-off-by: Giulio Benetti
---
V1->V2:
As suggested by Rob Herring:
* fixed $id: address
* added &qu
On 4/7/21 8:56 PM, Rob Herring wrote:
On Wed, Apr 7, 2021 at 12:57 PM Giulio Benetti
wrote:
Hello Rob, All,
On 4/6/21 3:24 PM, Rob Herring wrote:
On Fri, 02 Apr 2021 18:16:26 +0200, Giulio Benetti wrote:
This adds device tree bindings for the Hycon HY46XX touchscreen series.
Signed-off-by
sun4i_dclk_round_rate is called before sun4i_tcon_mode_set,
so it finds dclk_min_div and dclk_max_div set to 0 and fails
adding crtc.
Move dclk_min_div and dclk_max_div to encoders init functions.
Signed-off-by: Giulio Benetti
---
drivers/gpu/drm/sun4i/sun4i_lvds.c | 4
drivers/gpu/drm
Hi,
Il 16/02/2018 16:50, Maxime Ripard ha scritto:
On Thu, Feb 15, 2018 at 07:05:56PM +0100, Giulio Benetti wrote:
If so, and if remember the captures properly, the sampling would occur
right before the rise, and not really around the fall.
Would 2/3 be better here?
Yes, you're right
Handle both positive and negative dclk polarity,
according to bus_flags.
Signed-off-by: Giulio Benetti
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i
Hi,
Il 28/02/2018 16:55, Maxime Ripard ha scritto:
Hi,
On Wed, Feb 28, 2018 at 01:51:58PM +0100, Giulio Benetti wrote:
sun4i_dclk_round_rate is called before sun4i_tcon_mode_set,
so it finds dclk_min_div and dclk_max_div set to 0 and fails
adding crtc.
Move dclk_min_div and dclk_max_div to
Phase value is not shifted before writing.
Shift left of 28 bits to fit right bits
Signed-off-by: Giulio Benetti
---
drivers/gpu/drm/sun4i/sun4i_dotclock.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
b/drivers/gpu/drm/sun4i
At the moment both min and max dclk div are set to 7.
This doesn't allow to have lower frequencies.
Increase dclk_max_div to 18 to achieve 30Mhz.
Signed-off-by: Giulio Benetti
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver
mode_valid function is missing for lvds.
Add it based on rgb model, also setting up dclk_min_div and dclk_max_div
Signed-off-by: Giulio Benetti
---
drivers/gpu/drm/sun4i/sun4i_lvds.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/drivers/gpu/drm
Hi,
Il 28/02/2018 17:34, Giulio Benetti ha scritto:
Hi,
Il 28/02/2018 16:55, Maxime Ripard ha scritto:
Hi,
On Wed, Feb 28, 2018 at 01:51:58PM +0100, Giulio Benetti wrote:
sun4i_dclk_round_rate is called before sun4i_tcon_mode_set,
so it finds dclk_min_div and dclk_max_div set to 0 and fails
my use is not the best, so I would like to have many
overlays in /boot folder and use different boot.scr depending on hardware.
Can you point me to somewhere or something?
I don't really know where to beat my head!
Thanks in advance.
--
Giulio Benetti
CTO
MICRONOVA SRL
Sede: Via A. Niedda 3 - 35010 Vigonza (PD)
Tel. 049/8931563 - Fax 049/8931346
Cod.Fiscale - P.IVA 02663420285
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Iscritta al Reg. Imprese di Padova N. 02663420285
Numero R.E.A. 258642
Hi everybody,
Il 04/06/2018 12:34, Matwey V. Kornilov ha scritto:
2018-06-04 13:12 GMT+03:00 Andy Shevchenko :
On Fri, 2018-06-01 at 14:40 +0200, Giulio Benetti wrote:
Need to handle rs485 with 8250_dw port.
Use existing em485 emulation layer for 8250 taking care to fix some
bug
and taking
Hi,
Il 04/06/2018 12:17, Andy Shevchenko ha scritto:
On Fri, 2018-06-01 at 14:40 +0200, Giulio Benetti wrote:
Some 8250 ports only have TEMT interrupt, so current implementation
can't work for ports without it. The only chance to make it work is to
loop-read on LSR register.
With NO
Hi,
Il 04/06/2018 12:13, Andy Shevchenko ha scritto:
On Fri, 2018-06-01 at 14:40 +0200, Giulio Benetti wrote:
em485 gets lost during serial8250_register_8250_port().
Copy em485 to final uart port.
Fixes better to go first.
I think you need to reorder the series.
Ok, thanks.
So after re
Hi,
Il 04/06/2018 13:38, Andy Shevchenko ha scritto:
On Mon, 2018-06-04 at 12:50 +0200, Giulio Benetti wrote:
Hi,
Il 04/06/2018 12:17, Andy Shevchenko ha scritto:
On Fri, 2018-06-01 at 14:40 +0200, Giulio Benetti wrote:
Some 8250 ports only have TEMT interrupt, so current
implementation
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