Hi Taniya,
On Tue, Jul 24, 2018 at 3:44 AM Taniya Das wrote:
>
> The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
> for changing the frequency of CPUs. The driver implements the cpufreq
> driver interface for this hardware engine.
>
> Signed-off-by: Saravana Kannan
> Sig
> drivers/interconnect/qcom/Kconfig | 9 +
> drivers/interconnect/qcom/Makefile | 2 +
> drivers/interconnect/qcom/msm8916.c | 510
> 5 files changed, 527 insertions(+)
> create mode 100644 drivers/interconnect/qcom/msm8916.c
>
Reviewed-by: Evan Green
/interconnect/interconnect.rst
> create mode 100644 drivers/interconnect/Kconfig
> create mode 100644 drivers/interconnect/Makefile
> create mode 100644 drivers/interconnect/core.c
> create mode 100644 include/linux/interconnect-provider.h
> create mode 100644 include/linux/interconnect.h
>
Thanks Georgi. This looks great!
Reviewed-by: Evan Green
ugh perhaps most other frameworks are
not quite as optional for a particular driver.
Reviewed-by: Evan Green
> 1 file changed, 78 insertions(+)
>
Reviewed-by: Evan Green
rpm {
> + interrupts = <0 168 1>;
It would be nice if this interrupt example were more proper, somethine
like . Other than that:
Reviewed-by: Evan Green
On Tue, Jul 31, 2018 at 3:44 PM Lina Iyer wrote:
>
> GPIOs that are wakeup capable have interrupt lines that are routed to
> the always-on interrupt controller (PDC) in parallel to the pinctrl. The
> interrupts listed here are the wake up lines corresponding to GPIOs.
>
> Signed-off-by: Lina Iyer
On Tue, Jul 31, 2018 at 12:20 PM Wolfram Sang wrote:
>
> On Mon, Jul 30, 2018 at 11:23:51AM -0600, Karthikeyan Ramasubramanian wrote:
> > This bus driver supports the GENI based i2c hardware controller in the
> > Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable
> > module sup
On Tue, Jul 31, 2018 at 3:09 AM Can Guo wrote:
>
> Add UFS PHY support to make SDM845 UFS work with common PHY framework.
>
> Signed-off-by: Can Guo
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 172
> +++-
> drivers/phy/qualcomm/phy-qcom-qmp.h | 15
> 2 fi
On Thu, Aug 9, 2018 at 10:26 AM Vivek Gautam
wrote:
>
> Hi Evan,
>
>
> On 8/9/2018 3:25 AM, Evan Green wrote:
> > On Tue, Jul 31, 2018 at 3:09 AM Can Guo wrote:
> >> Add UFS PHY support to make SDM845 UFS work with common PHY framework.
> >>
> >>
; static inline u32
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Reviewed-by: Evan Green
On Wed, Aug 1, 2018 at 1:33 PM Venkata Narendra Kumar Gutta
wrote:
>
> Cache error reporting controller is to detect and report single
> and double bit errors on Last Level Cache Controller (LLCC) cache.
> Add required support to register LLCC EDAC driver as platform driver,
> from LLCC driver.
>
On Wed, Aug 1, 2018 at 1:34 PM Venkata Narendra Kumar Gutta
wrote:
>
> From: Channagoud Kadabi
>
> Add error reporting driver for SBEs and DBEs. As of now, this driver
> supports erp for Last Level Cache Controller (LLCC). This driver takes
> care of dumping registers and adding config options to
On Fri, Aug 10, 2018 at 4:13 PM wrote:
>
> On 2018-08-10 10:23, Evan Green wrote:
> > On Wed, Aug 1, 2018 at 1:34 PM Venkata Narendra Kumar Gutta
> > wrote:
> >>
> >> From: Channagoud Kadabi
> >>
> >> Add error reporting driver for SBEs
On Tue, Aug 21, 2018 at 3:18 AM Sayali Lokhande wrote:
>
> From: Subhash Jadavani
>
> UFS host supplies the reference clock to UFS device and UFS device
> specification allows host to provide one of the 4 frequencies (19.2 MHz,
> 26 MHz, 38.4 MHz, 52 MHz) for reference clock. Host should set the
s/soc/qcom/llcc-slice.c | 55
> +++---
> include/linux/soc/qcom/llcc-qcom.h | 4 +--
> 2 files changed, 35 insertions(+), 24 deletions(-)
>
Reviewed-by: Evan Green
On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
wrote:
>
> From: Channagoud Kadabi
>
> Add error reporting driver for Single Bit Errors (SBEs) and Double Bit
> Errors (DBEs). As of now, this driver supports erp for Last Level Cache
> Controller (LLCC). This driver takes care of dumpi
On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
wrote:
>
> Cache error reporting controller is to detect and report single
Should be "Cache error reporting controller detects and reports single"...
Other than that:
Reviewed-by: Evan Green
On Thu, Aug 23, 2018 at 4:04 PM Evan Green wrote:
>
> On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
> wrote:
> >
> > From: Channagoud Kadabi
Also checkpatch.pl complains a bit about this patch:
WARNING: Non-standard signature: Co-develope
On Fri, Aug 24, 2018 at 11:32 AM wrote:
>
> On 2018-08-23 16:04, Evan Green wrote:
> > On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
> > wrote:
> >>
> >> From: Channagoud Kadabi
> >>
> >> Add error reporting driver for Sin
Hi David,
On Thu, Jul 26, 2018 at 4:30 PM David Dai wrote:
>
> Introduce Qualcomm SDM845 specific provider driver using the
> interconnect framework.
>
> Signed-off-by: David Dai
> ---
> .../bindings/interconnect/qcom-sdm845.txt | 22 +
> drivers/interconnect/qcom/Kconfig
This change makes the UFS controller's sysfs attributes writable, which
will enable users to modify attributes. This can be useful during factory
provisioning for setting up critical attributes like the reference clock
frequency.
Signed-off-by: Evan Green
---
Configfs was determined to b
t; > Signed-off-by: Can Guo
> > ---
> > drivers/phy/qualcomm/phy-qcom-qmp.c | 19 ---
> > 1 file changed, 12 insertions(+), 7 deletions(-)
> >
Reviewed-by: Evan Green
On Tue, Jul 10, 2018 at 1:38 PM Lina Iyer wrote:
>
> On Tue, Jul 10 2018 at 12:53 -0600, Evan Green wrote:
> >On Mon, Jul 9, 2018 at 10:27 AM Bjorn Andersson
> > wrote:
> >>
> >> Sorry for not getting back to you in a timely manner Evan, I wanted to
> >&g
On Fri, Jul 13, 2018 at 3:21 PM Karthik Ramasubramanian
wrote:
>
>
>
> On 7/9/2018 5:49 PM, Evan Green wrote:
> > pm_runtime_suspended can return 0 even if the last runtime power
> > management function called in the device was a suspend call. This
> > trips up the
Hi Rajendra,
On Thu, Jan 25, 2018 at 8:32 AM, Rajendra Nayak wrote:
> Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
>
> Signed-off-by: Rajendra Nayak
> ---
> arch/arm64/boot/dts/qcom/Makefile| 1 +
> arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 13 ++
> arch/arm64/boot/dt
Hi Lina,
On Fri, Mar 2, 2018 at 8:43 AM, Lina Iyer wrote:
> Active state requests are sent immediately to the mailbox controller,
> while sleep and wake state requests are cached in this driver to avoid
> taxing the mailbox controller repeatedly. The cached values will be sent
> to the controller
Hi Rishabh,
On Tue, Apr 10, 2018 at 1:09 PM Rishabh Bhatnagar
wrote:
> LLCC (Last Level Cache Controller) provides additional cache memory
> in the system. LLCC is partitioned into multiple slices and each
> slice gets its own priority, size, ID and other config parameters.
> LLCC driver program
Usage: required
> +Value type:
> +Definition: The tuple has phandle to llcc device as the first
> + argument and the second argument is the usecase
> + id of the client.
> +For Example:
> + venus {
> + cache-slice-names = "vidsc0", "vidsc1";
> + cache-slices = <&llcc VIDSC0_ID>, <&llcc VIDSC1_ID>;
My git complains about some whitespace weirdness on the line above. Other
than that:
Reviewed-by: Evan Green
-Evan
On Tue, Mar 20, 2018 at 12:00 AM Manu Gautam wrote:
> Hi,
> On 3/19/2018 11:21 PM, Evan Green wrote:
> > Hi Manu,
> >
> > On Fri, Mar 16, 2018 at 2:46 AM Manu Gautam
wrote:
> [snip]
> >> index d1c6905..5d78d43 100644
> >> --- a/drivers/phy/q
reserved-memory {
> > + [...]
> > + qcom,cmd-db@85fe {
> Nitpick: This may want to be called 'memory@85fe' because we prefer
> generic node names.
Another nit: the cmd-db region seems to need "no-map" to make the example
actually work.
Reviewed-by: Evan Green
-Evan
On Thu, Apr 5, 2018 at 4:17 PM Stephen Boyd wrote:
> Quoting Taniya Das (2018-04-02 03:33:26)
> >
> > >
> > >> +
> > >> +#include "common.h"
> > >> +#include "clk-regmap.h"
> > >> +
> > >> +#define CLK_RPMH_ARC_EN_OFFSET 0
> > >> +#define CLK_RPMH_VRM_EN_OFFSET 4
> > >> +#define CLK_RPMH_VRM_OFF_
YPE_EDGE_RISING at the GIC.
>
> Reported-by: Evan Green
> Signed-off-by: Lina Iyer
> ---
> drivers/irqchip/qcom-pdc.c | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Evan Green
On Thu, Sep 27, 2018 at 7:01 AM Christoph Hellwig wrote:
>
> On Thu, Sep 27, 2018 at 06:32:47AM +, Avri Altman wrote:
> > Also, in this context there is the series in
> > https://www.spinics.net/lists/linux-scsi/msg123479.html
> > which allows to send UPIUs via a bsg device.
> >
> > It's not a
To overcome this h/w limitation, the DLL needs to be re-initialized
> and restored with its old settings once clocks are ungated.
>
> Signed-off-by: Veerabhadrarao Badiganti
Reviewed-by: Evan Green
Enable support for the micro SD slot on the MTP.
Signed-off-by: Evan Green
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 53 +
1 file changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index
pinctrl states. It's not obvious to
me that all this messing with drive-strength saves non-negligible amounts of
power, so I didn't add them and figured we could add them later if needed.
Evan Green (3):
dt-bindings: mmc: sdhci-msm: Clarify register requirements
arm64: dts: qcom: s
Add the SD controller to SDM845.
Signed-off-by: Evan Green
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 1419b0098cb38..bb8eacdf40910 100644
--- a
In sdhci-msm-v5 and beyond, the MCI registers are removed, so there is only
one register region required.
Signed-off-by: Evan Green
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc
On Wed, Nov 21, 2018 at 11:18 PM Bjorn Andersson
wrote:
>
> On Fri 26 Oct 10:35 PDT 2018, Evan Green wrote:
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index b72bdb0a31a5..9c72edb678ec 100644
> > --- a/arch/a
testing, I was able to test this on sdm845, but haven't tested
msm8996.
This patch sits atop the UFS device nodes series [1].
[1] https://lore.kernel.org/lkml/20181026173544.136037-1-evgr...@chromium.org/
Evan Green (4):
dt-bindings: phy-qcom-qmp: Move #clock-cells to child
arm64: dt
Register a simple clock provider for the PHY pipe clock sources so that
device tree users can point at these clocks via phandles to the lane
nodes.
Signed-off-by: Evan Green
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion
cell.
Fix these incomplete and broken bindings. Move the #clock-cells into the
child node, since that is the actual clock provider, and not all
instances of qcom-qmp-phy are clock providers. Also set #clock-cells to
zero, since there's nothing to pass to it.
Signed-off-by: Evan
Move #clock-cells into the child node for instances of the qcom-qmp-phy
nodes, and set it to zero, in accordance with the proper bindings. PHYs
that don't provide clocks don't have #clock-cells, and so are left alone.
Signed-off-by: Evan Green
---
arch/arm64/boot/dts/qcom/sdm84
Move #clock-cells into the child node and set it to 0 to conform to the
proper binding specification.
Signed-off-by: Evan Green
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch
On Wed, Nov 14, 2018 at 6:36 AM Veerabhadrarao Badiganti
wrote:
>
> >>> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> >>> index b001cf4..3c28152 100644
> >>> --- a/drivers/mmc/host/sdhci.h
> >>> +++ b/drivers/mmc/host/sdhci.h
> >>> @@ -524,6 +524,7 @@ struct sdhci_host {
> >>>
Add PM suspend callbacks to the msm core driver that select the
sleep and default pinctrl states. Then wire those callbacks up
in the sdm845 driver, for those boards that may have GPIO hogs
that need to change state during suspend.
Signed-off-by: Evan Green
Reviewed-by: Stephen Boyd
On Fri, Nov 9, 2018 at 11:20 PM Bjorn Andersson
wrote:
>
> On Fri 09 Nov 14:28 PST 2018, Evan Green wrote:
>
> > Add PM suspend callbacks to the msm core driver that select the
> > sleep and default pinctrl states. Then wire those callbacks up
> > in the sdm845 driver
initializing prescale_index as if it were directly a divisor,
rather than the index into adc5_prescale_ratios that it is.
Fix the uninitialized value, and change the static initialization to use
indices into adc5_prescale_ratios.
Signed-off-by: Evan Green
---
drivers/iio/adc/qcom-spm
On Tue, Nov 27, 2018 at 10:03 AM Georgi Djakov wrote:
>
> Modern SoCs have multiple processors and various dedicated cores (video, gpu,
> graphics, modem). These cores are talking to each other and can generate a
> lot of data flowing through the on-chip interconnects. These interconnect
> buses c
On Wed, Dec 5, 2018 at 1:19 PM Doug Anderson wrote:
>
> Hi,
>
> On Wed, Nov 28, 2018 at 2:34 PM Evan Green wrote:
> > +&sdhc_2 {
> > + status = "okay";
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = &
.
- Fixed alphabetization of node placement in sdm845-mtp.dtsi (Doug)
- Fixed card detect name to match schematics (Doug).
- Moved comment about drive strength next to the drive-strength entry
(Doug)
- Removed drive-strength from card detect input pin (Doug).
- Consolidated tlmm nodes in
Add one of the two SD controllers to SDM845.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
---
Changes in v2:
- Reworded commit message to note that there are multiple SD
controllers.
arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++
1 file changed, 15 insertions
In sdhci-msm-v5 and beyond, the MCI registers are removed, so there is only
one register region required.
Signed-off-by: Evan Green
---
Changes in v2: None
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation
Enable support for one of the micro SD slots on the MTP.
Signed-off-by: Evan Green
---
Changes in v2:
- Fixed alphabetization of node placement in sdm845-mtp.dtsi (Doug)
- Fixed card detect name to match schematics (Doug).
- Moved comment about drive strength next to the drive-strength entry
med ufsphy to phy (Vivek)
- Removed #clock-cells (Vivek)
Can Guo (1):
arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp
Evan Green (4):
dt-bindings: phy-qcom-qmp: Fix register underspecification
phy: qcom-qmp: Utilize fully-specified DT registers
arm64: dts: qcom: sdm845: add UFS
don't exist, which
reverts to the original behavior of overreaching and prints a complaint.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
---
As Doug mentioned, this should land before the dts patches land, otherwise
the old driver code will use the tx2 register region as pcs_misc.
that don't
provide a pipe clock. Also, document the pcs_misc register region, which
was being quietly supplied and used.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
Reviewed-by: Rob Herring
---
Changes in v6: None
Changes in v5:
- Fix incorrect register value in example, copied
Add the second lane registers for the USB PHY, now that the
QMP phy bindings have been updated. This way the driver can stop
reaching beyond its register region to get at the second lane.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
Reviewed-by: Bjorn Andersson
---
Changes in v6
From: Can Guo
Enable the UFS host controller and PHY on sdm845-mtp.
Signed-off-by: Can Guo
Signed-off-by: Evan Green
Reviewed-by: Vivek Gautam
Reviewed-by: Douglas Anderson
---
Changes in v6:
- Fix renamed nodes in MTP (Bjorn)
Changes in v5: None
Changes in v4: None
Changes in v3: None
Add the UFS controller and PHY to SDM845.
Signed-off-by: Evan Green
Signed-off-by: Douglas Anderson
Reviewed-by: Bjorn Andersson
---
As Doug mentioned in v2, this should land after (or with) the driver fix
in this series.
Changes in v6:
- Removed resets and reset-names (Bjorn)
- Renamed
On Thu, Dec 6, 2018 at 3:34 PM Doug Anderson wrote:
>
> Hi,
> On Thu, Dec 6, 2018 at 10:45 AM Evan Green wrote:
> >
> > In sdhci-msm-v5 and beyond, the MCI registers are removed, so there is only
> > one register region required.
> >
> > Signed-off-by: Ev
ct path name strings sorted in the
> same
> +order as the interconnects property. Consumers drivers
> will use
> +interconnect-names to match interconnect paths with
> interconnect
> +specifier pairs.
> +
> +Example:
> +
> + sdhci@7864000 {
> + ...
> + interconnects = <&pnoc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>;
> + interconnect-names = "sdhc-ddr";
> + };
Reviewed-by: Evan Green
users;
> void*data;
> diff --git a/include/linux/interconnect.h b/include/linux/interconnect.h
> index 04b2966ded9f..41f7ecc2f20f 100644
> --- a/include/linux/interconnect.h
> +++ b/include/linux/interconnect.h
> @@ -26,6 +26,7 @@ struct device;
>
> struct icc_path *icc_get(struct device *dev, const int src_id,
> const int dst_id);
> +struct icc_path *of_icc_get(struct device *dev, const char *name);
> void icc_put(struct icc_path *path);
> int icc_set(struct icc_path *path, u32 avg_bw, u32 peak_bw);
>
> @@ -37,6 +38,12 @@ static inline struct icc_path *icc_get(struct device *dev,
> const int src_id,
> return NULL;
> }
>
> +static inline struct icc_path *of_icc_get(struct device *dev,
> + const char *name)
> +{
> + return NULL;
> +}
> +
> static inline void icc_put(struct icc_path *path)
> {
> }
With these nits fixed:
Reviewed-by: Evan Green
ology"
...Or a slightly different flavor: "Then the providers configure each
node along the path to support a bandwidth that satisfies all
bandwidth requests that cross through that node".
> constraints. The topology could be complicated and multi-tiered and is SoC
> specifi
On Tue, Nov 27, 2018 at 10:04 AM Georgi Djakov wrote:
>
> From: David Dai
>
> Add RSC (Resource State Coordinator) provider
> dictating network-on-chip interconnect bus performance
> found on SDM845-based platforms.
>
> Signed-off-by: David Dai
> Signed-off-by: Georgi Djakov
> ---
> arch/arm64
On Tue, Nov 27, 2018 at 10:04 AM Georgi Djakov wrote:
>
> From: David Dai
>
> Introduce Qualcomm SDM845 specific provider driver using the
> interconnect framework.
>
> Signed-off-by: David Dai
> Signed-off-by: Georgi Djakov
> ---
> .../bindings/interconnect/qcom,sdm845.txt | 24 +
> driv
On Mon, Dec 3, 2018 at 2:38 PM Stephen Boyd wrote:
>
> Quoting Evan Green (2018-11-29 14:13:57)
> > Register a simple clock provider for the PHY pipe clock sources so that
> > device tree users can point at these clocks via phandles to the lane
> > nodes.
> >
Add PM suspend callbacks to the msm core driver that select the
sleep and default pinctrl states. Then wire those callbacks up
in the sdm845 driver, for those boards that may have GPIO hogs
that need to change state during suspend.
Signed-off-by: Evan Green
---
drivers/pinctrl/qcom/pinctrl
Add the gpio-ranges property to the TLMM node so that GPIO hogs work.
Signed-off-by: Evan Green
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b72bdb0a31a57
On Sun, Jul 1, 2018 at 5:12 AM Georgi Djakov wrote:
>
> Hi Evan,
>
> On 06/26/2018 11:48 PM, Evan Green wrote:
> > On Wed, Jun 20, 2018 at 5:11 AM Georgi Djakov
> > wrote:
>
> >> +static int qcom_icc_init(struct icc_node *node)
> >>
store+0xd4/0xf8
[ 68.621014] [] kobj_attr_store+0x18/0x28
[ 68.626672] [] sysfs_kf_write+0x5c/0x68
[ 68.632240] [] kernfs_fop_write+0x174/0x1b8
[ 68.638177] [] __vfs_write+0x58/0x160
[ 68.643567] [] vfs_write+0xcc/0x184
[ 68.648780] [] SyS_write+0x64/0xb4
Signed-off-by: Evan Green
---
On Mon, Jul 9, 2018 at 10:27 AM Bjorn Andersson
wrote:
>
> Sorry for not getting back to you in a timely manner Evan, I wanted to
> read up more on the details of how this is supposed to work. I still
> haven't done so, but here's my concern:
>
> When we power down the SoC we're no longer powering
Ahoy Georgi!
On Mon, Jul 9, 2018 at 8:51 AM Georgi Djakov wrote:
>
> This patch introduces a new API to get requirements and configure the
> interconnect buses across the entire chipset to fit with the current
> demand.
>
> The API is using a consumer/provider-based model, where the providers are
On Mon, Jul 9, 2018 at 8:51 AM Georgi Djakov wrote:
>
> On some Qualcomm SoCs, there is a remote processor, which controls some of
> the Network-On-Chip interconnect resources. Other CPUs express their needs
> by communicating with this processor. Add a driver to handle communication
> with this r
On Mon, Jul 9, 2018 at 8:51 AM Georgi Djakov wrote:
>
> Add driver for the Qualcomm interconnect buses found in msm8916 based
> platforms.
>
> Signed-off-by: Georgi Djakov
> ---
> drivers/interconnect/Kconfig| 5 +
> drivers/interconnect/Makefile | 1 +
> drivers/interconnect/q
On Mon, Jul 9, 2018 at 8:51 AM Georgi Djakov wrote:
>
> Add documentation for the interconnect consumer bindings, that will allow
> to link a device node (consumer) to its interconnect controller hardware.
>
> Tha aim is to enable drivers to request a framework API to configure an
> interconnect p
On Wed, Jun 20, 2018 at 5:11 AM Georgi Djakov wrote:
>
> Add driver for the Qualcomm interconnect buses found in msm8916 based
> platforms.
>
> Signed-off-by: Georgi Djakov
> ---
> drivers/interconnect/Kconfig| 5 +
> drivers/interconnect/Makefile | 1 +
> drivers/interconnect/
Hi Georgi,
On Wed, Jun 20, 2018 at 5:11 AM Georgi Djakov wrote:
>
> On some Qualcomm SoCs, there is a remote processor, which controls some of
> the Network-On-Chip interconnect resources. Other CPUs express their needs
> by communicating with this processor. Add a driver to handle comminication
Hi Georgi. Thanks for the new spin of this.
On Wed, Jun 20, 2018 at 5:11 AM Georgi Djakov wrote:
>
> This patch introduce a new API to get requirements and configure the
> interconnect buses across the entire chipset to fit with the current
> demand.
>
> The API is using a consumer/provider-based
On Tue, Jun 19, 2018 at 1:38 AM Can Guo wrote:
>
> Add UFS PHY support to make SDM845 UFS work with common PHY framework.
>
> Signed-off-by: Can Guo
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 173
> +++-
> drivers/phy/qualcomm/phy-qcom-qmp.h | 15
> 2 fi
m/phy-qcom-qmp.c | 25 ++---
> 1 file changed, 14 insertions(+), 11 deletions(-)
>
I'm not a PHY expert, so I can't say much about the mechanics or
ramifications of the is_dual_lane_phy change is, but for at least the
sanity of the patch, here's my tag:
Reviewed-by: Evan Green
On Tue, May 22, 2018 at 5:08 AM Ulf Hansson wrote:
> First, I thought I preferred this option, as it becomes clear of what
> goes on. However I then realize, that it may not be worth it, because
> in the end I guess the caller (sdhci), will not be able to deal with
> error codes. For example, wha
, and b) wire
card detect up to a GPIO that doesn't sleep, this is a spurious warning.
This change silences that warning, at the cost of pushing this problem
down to users that have sleeping GPIOs and controllers with this quirk.
Signed-off-by: Evan Green
---
Changes since v1:
-
On Thu, May 24, 2018 at 5:35 AM Vijay Viswanath
wrote:
> On 5/22/2018 11:40 PM, Evan Green wrote:
> > On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath > wrote:
> >
> >> In addition to offsets of certain registers changing, the registers in
> >> core_mem hav
On Thu, May 24, 2018 at 6:01 AM Vijay Viswanath
wrote:
> On 5/22/2018 11:42 PM, Evan Green wrote:
> > Hi Vijay. Thanks for this patch.
> >
> > On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath > wrote:
> >
> >> From: Sayali Lokhande
> >
...
> &
Hi Georgi,
On Fri, Mar 9, 2018 at 1:11 PM Georgi Djakov
wrote:
> Add driver for the Qualcomm interconnect buses found in msm8916 based
> platforms.
> Signed-off-by: Georgi Djakov
> ---
>drivers/interconnect/Kconfig| 5 +
>drivers/interconnect/Makefile | 1 +
>driver
On Fri, Mar 9, 2018 at 1:10 PM Georgi Djakov
wrote:
> Currently we support only platform data for specifying the interconnect
> endpoints. As now the endpoints are hard-coded into the consumer driver
> this may leed to complications when a single driver is used by multiple
Nit: s/leed/lead/
-Ev
On Fri, Mar 9, 2018 at 1:11 PM Georgi Djakov
wrote:
> On some Qualcomm SoCs, there is a remote processor, which controls some of
> the Network-On-Chip interconnect resources. Other CPUs express their needs
> by communicating with this processor. Add a driver to handle comminication
> with this re
Hi Georgi,
On Fri, Mar 9, 2018 at 1:12 PM Georgi Djakov
wrote:
> This patch introduce a new API to get requirements and configure the
> interconnect buses across the entire chipset to fit with the current
> demand.
> The API is using a consumer/provider-based model, where the providers are
> th
] [] state_store+0xd4/0xf8
[ 54.091733] [] kobj_attr_store+0x18/0x28
[ 54.097396] [] sysfs_kf_write+0x5c/0x68
[ 54.102961] [] kernfs_fop_write+0x174/0x1b8
[ 54.108887] [] __vfs_write+0x58/0x160
[ 54.114276] [] vfs_write+0xcc/0x184
[ 54.119487] [] SyS_write+0x64/0xb4
Signed-off-by: Evan
oot/dts/qcom/pm8998.dtsi | 55
> 2 files changed, 88 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/pm8005.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/pm8998.dtsi
>
Reviewed-by: Evan Green
On Wed, May 16, 2018 at 2:52 AM Adrian Hunter
wrote:
> On 02/05/18 02:47, Evan Green wrote:
> > For a controller with SDHCI_QUIRK_NO_CARD_NO_RESET, there are several
> > conditions where sdhci_do_reset is called under a spinlock with
interrupts
> > disabled. The card d
+++
> include/linux/soc/qcom/llcc-qcom.h | 180
> 5 files changed, 642 insertions(+)
> create mode 100644 drivers/soc/qcom/llcc-sdm845.c
> create mode 100644 drivers/soc/qcom/llcc-slice.c
> create mode 100644 include/linux/soc/qcom/llcc-qcom.h
Thanks Rishabh.
Reviewed-by: Evan Green
On Wed, Dec 12, 2018 at 10:41 AM Jonathan Cameron
wrote:
>
> On Sat, 8 Dec 2018 12:05:15 +
> Jonathan Cameron wrote:
>
> > On Tue, 4 Dec 2018 11:57:32 -0800
> > Matthias Kaehlcke wrote:
> >
> > > On Tue, Dec 04, 2018 at 11:14:19AM -0800, Evan Green
with these changes I can run as a different user, and drop
all other privileges.
Evan Green (2):
soc: qcom: rmtfs-mem: Add class to enable uevents
soc: qcom: rmtfs-mem: Make sysfs attributes world-readable
drivers/soc/qcom/rmtfs_mem.c | 29 +
1 file change
Currently the qcom_rmtfs_memN devices are entirely invisible to the udev world.
Add a class to the rmtfs device so that uevents fire when the device is added.
Signed-off-by: Evan Green
---
drivers/soc/qcom/rmtfs_mem.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions
those attributes readable by all.
Signed-off-by: Evan Green
---
drivers/soc/qcom/rmtfs_mem.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rmtfs_mem.c b/drivers/soc/qcom/rmtfs_mem.c
index 0bf800ee2a978..4eeb9f02e7889 100644
--- a/drivers/soc/qcom/rmtfs_
On Mon, Dec 10, 2018 at 9:31 AM Evan Green wrote:
>
> On Wed, Dec 5, 2018 at 7:15 PM Martin K. Petersen
> wrote:
> >
> >
> > Evan,
> >
> > > Ah, I see. But I think it's useful to reflect max_discard_sectors,
> > > max_write_zeroes_sector
d serial characters, rather than edited ones.
Either way, this looks good to me.
Reviewed-by: Evan Green
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