This add the necessary binding documentation for the power domain
found on Rockchip Socs.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
.../bindings/arm/rockchip/power_domain.txt | 48 ++
1 file changed, 48 insertions(+)
create mode 100644
drm/rockchip already has support for disabling all displays on suspend
and enabling them on resume.
Disable automatic VT switching on suspend by the pm console tracking
layer.
Tested on veyron, used `echo mem > sys/power/state`
=> verified no VT switch.
Caesar Wang (1):
drm: ro
off-by: Caesar Wang
---
drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
index a5d889a..eb4e0db 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_f
Tested on veyron devices,play music then shutdown device,here carefully
to speaker or headphone.
Caesar Wang (1):
ASoC: max98090: add shutdown callback for max98090
sound/soc/codecs/max98090.c | 17 +
1 file changed, 17 insertions(+)
--
1.9.1
--
To unsubscribe from this
To fix pop noise when shutdown,the pop noise during shutdown
is the pmic cutoff power of codec without any notice.
Signed-off-by: jay.xu
Signed-off-by: zhengxing
Signed-off-by: Caesar Wang
Serien-cc: linux-kernel@vger.kernel.org
Serien-cc: devicet...@vger.kernel.org
Serien-cc: diand
Heiko,
在 2015年04月08日 17:25, Heiko Stübner 写道:
Hi Caesar,
Am Mittwoch, 8. April 2015, 16:52:08 schrieb Caesar Wang:
To fix pop noise when shutdown,the pop noise during shutdown
is the pmic cutoff power of codec without any notice.
Signed-off-by: jay.xu
Signed-off-by: zhengxing
Signed-off-by
Mark,
在 2015年04月08日 17:50, Mark Brown 写道:
On Wed, Apr 08, 2015 at 04:52:08PM +0800, Caesar Wang wrote:
+static void max98090_i2c_shutdown(struct i2c_client *i2c)
+{
+ struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
+
+ dev_info(&i2c->dev, "
To fix pop noise when shutdown,the pop noise during shutdown
is the pmic cutoff power of codec without any notice.
Signed-off-by: jay.xu
Signed-off-by: zhengxing
Signed-off-by: Caesar Wang
Serien-cc: linux-kernel@vger.kernel.org
Serien-cc: devicet...@vger.kernel.org
Serien-cc: diand
Kever,
在 2015年04月08日 18:51, Kever Yang 写道:
Hi Caesar,
On 04/08/2015 06:18 PM, Caesar Wang wrote:
To fix pop noise when shutdown,the pop noise during shutdown
is the pmic cutoff power of codec without any notice.
Signed-off-by: jay.xu
Signed-off-by: zhengxing
Signed-off-by: Caesar Wang
To fix pop noise when shutdown,the pop noise during shutdown
is the pmic cutoff power of codec without any notice.
Signed-off-by: jay.xu
Signed-off-by: zhengxing
Signed-off-by: Caesar Wang
---
Changes in v3:
- modify the shutdown function before remove(..)
- fix the `Serien-cc`
Changes in
for next kernel.
Caesar Wang (3):
dt-bindings: add document of Rockchip power domain
power-domain: rockchip: add power domain driver
ARM: dts: add RK3288 power-domain node
.../bindings/arm/rockchip/power_domain.txt | 48 ++
arch/arm/boot/dts/rk3288.dtsi | 59
This add the necessary binding documentation for the power domain
found on Rockchip Socs.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
.../bindings/arm/rockchip/power_domain.txt | 48 ++
1 file changed, 48 insertions(+)
create mode 100644
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power
mode.
The RK3288 PMU is dedicated for managing the power ot the whole chip.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
arch/arm/mach
syncchronous reset and
then sync revoked.so we need to enable clocks of all devices.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
Changes in v13:
- Remove essential clocks from rk3288 PD_VIO domain
Some clocks are essential for the system health and should not
be turned down
Hi Mark,
Can you apply it into your drm branch if it's indeed uesful for u?
在 2015年03月31日 18:22, Caesar Wang 写道:
drm/rockchip already has support for disabling all displays on suspend
and enabling them on resume.
Disable automatic VT switching on suspend by the pm console tracking
Paul,
Thanks your commnets!:-)
在 2015年04月20日 17:26, Paul Bolle 写道:
On Sun, 2015-04-19 at 18:44 +0800, Caesar Wang wrote:
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
+obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
PM_GENERIC_DOMAINS is a bool symbol, so
Hi Kevin, Heiko
Thanks for your comments.
Sorry for delay reply.
在 2015年04月28日 02:28, Kevin Hilman 写道:
Heiko Stübner writes:
Am Freitag, 24. April 2015, 16:07:45 schrieb Caesar Wang:
Add power domain drivers based on generic power domain for
Rockchip platform, and support RK3288
Ulf,
Thanks for your comments.:-)
在 2015年05月28日 18:38, Ulf Hansson 写道:
On 24 April 2015 at 10:07, Caesar Wang wrote:
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power
mode.
The RK3288 PMU is dedicated
This add the necessary binding documentation for the power domain
found on Rockchip Socs.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v15: None
Changes in v9:
- add document decription.
Series-changes:8
- document go back to v2.
Series-changes:3
- DT structure has
r-controller, hevc-power-controller).
Series-changes: 2
- make pd_vio clocks all one entry per line and alphabetize.
- power: power-controller move back to pinctrl: pinctrl.
Changes in v9:
- add document decription.
Series-changes:8
- document go back to v2.
Series-changes:3
- DT structure has changed
At the moment, we can support these power-domain type on RK3288.
We can add more types on RK3288 in the future, that's need to do.
Signed-off-by: Caesar Wang
---
Changes in v15:
- change the comment.
Changes in v9: None
include/dt-bindings/power-domain/rk3288.h | 11 +++
1
reset-circuit should reset be synchronous on rk3288,
then sync revoked. So we need to enable clocks of all devices.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v15:
- As Tomasz remarked previously the dts should represent the hardware
and the power-domains are part of
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power
mode.
The RK3288 PMU is dedicated for managing the power ot the whole chip.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v15:
- As
在 2015年06月15日 23:00, Paul Bolle 写道:
On Sun, 2015-06-14 at 13:13 +0800, Caesar Wang wrote:
--- /dev/null
+++ b/drivers/soc/rockchip/Kconfig
+config PM_GENERIC_DOMAINS
+tristate "Rockchip generic power domain"
Since my remarks on v13 you removed the module specific
node on RK3288.
Caesar Wang (3):
soc/rockchip: Add efuse bindings for Rockchip SoC efuse driver
soc/rockchip: efuse: Add Rockchip SoC efuse support
ARM: dts: Add RK3288 efuse node
.../bindings/fuse/rockchip,rockchip-efuse.txt | 14 ++
arch/arm/boot/dts/rk3288.dtsi
Add efuse bindings for RK3066, RK3188, RK3288 and RK3368.
Signed-off-by: Jianqun Xu
Signed-off-by: Caesar Wang
---
Changes in v2:
- Change the document decription.
.../devicetree/bindings/fuse/rockchip,rockchip-efuse.txt | 14 ++
1 file changed, 14 insertions(+)
create mode
Add the efuse node on RK3288, we can get some information
when enable the efuse driver.
e.g.: the CPU version, leakage.
Signed-off-by: Caesar Wang
---
Changes in v2:
- Add the dts node on RK3288.
arch/arm/boot/dts/rk3288.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch
Add driver for efuse found on Rockchip RK3066,RK3188,RK3288 and
RK3368 SoCs.
eFuse is organized as 32bits by 8 one-time programmable
electrical fuses with random access interface.
Signed-off-by: Jianqun Xu
Signed-off-by: Caesar Wang
---
Changes in v2:
- Move the efuse driver into driver/soc
Hi Srinivas,
在 2015年06月16日 17:21, Srinivas Kandagatla 写道:
Hi Stefan,
On 16/06/15 09:52, Stefan Wahren wrote:
Hi Caesar,
[add Maxime and Srinivas]
Am 16.06.2015 um 09:27 schrieb Caesar Wang:
The original driver is uploaded by Jianqun.
Here is his patchs:
https://patchwork.kernel.org
p_entry) from []
(secondary_start_kernel+0x138/0x160)
[34473.737059] [] (secondary_start_kernel) from [<00100464>]
(0x100464)
[34474.903740] SMP: failed to stop secondary CPUs
[34476.099964] SMP: failed to stop secondary CPUs
...
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/
Verified on url =
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.14
Caesar Wang (3):
ARM: rockchip: fix the CPU soft reset
ARM: rockchip: ensure CPU to enter WIF state
ARM: rockchip: fix the SMP code style
arch/arm/mach-rockchip/platsmp.c | 24
Use the below scripts to check:
scripts/checkpatch.pl -f arch/arm/mach-rockchip/platsmp.c
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI state.
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/platsmp.c b
在 2015年06月05日 14:32, Kever Yang 写道:
Hi Caesar,
Subject typo WIF/WFI.
OK
On 06/05/2015 12:47 PM, Caesar Wang wrote:
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI state.
Signed-off-by: Caesar Wang
Heiko,
在 2015年06月05日 16:45, Heiko Stübner 写道:
Hi Caesar,
thanks for investigating this.
Am Freitag, 5. Juni 2015, 12:47:55 schrieb Caesar Wang:
In general, the correct flow is:
cpu off:
reset_control_assert
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd))
cpu on
Verified on url =
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.14
Caesar Wang (3):
ARM: rockchip: fix the CPU soft reset
ARM: rockchip: ensure CPU to enter WFI/WFE state
ARM: rockchip: fix the SMP code style
arch/arm/mach-rockchip/platsmp.c | 56
lines checked
Changes in v2:
- As Kever points out, Fix the subject typo WIF/WFI in PATCH [2/3].
- As Heiko suggestion, re-adjust the cpu on/off flow in PATCH [1/3].
- Use the checkpatch.pl -f --subjective to check in PATCH [3/3].
Signed-off-by: Caesar Wang
---
arch/arm/mach-roc
rnel panic - not syncing: Watchdog detected hard
LOCKUP on cpu 0
...
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 46 +++-
1 file changed, 31 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI/WFE state.
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/platsmp.c
o check in PATCH [3/3].
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 6672fdd..ac9173e 100644
--- a/arch/arm/mach-rockchip/plats
Verified on url =
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.14
Caesar Wang (3):
ARM: rockchip: fix the CPU soft reset
ARM: rockchip: ensure CPU to enter WFI/WFE state
ARM: rockchip: fix the SMP code style
arch/arm/mach-rockchip/platsmp.c | 36
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI/WFE state.
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/platsmp.c
[34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on
cpu 0
...
.
- As Heiko suggestion, re-adjust the cpu on/off flow in PATCH [1/3].
- Use the checkpatch.pl -f --subjective to check in PATCH [3/3].
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mac
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI/WFE state.
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/platsmp.c
done
done
The following is reproducile log:
[34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing:Watchd
done
done
The following is reproducile log:
[34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing:Watchd
.
- As Heiko suggestion, re-adjust the cpu on/off flow in PATCH [1/3].
- Use the checkpatch.pl -f --subjective to check in PATCH [3/3].
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mac
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI/WFE state.
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/platsmp.c
在 2015年06月06日 04:55, Doug Anderson 写道:
Caesar,
On Fri, Jun 5, 2015 at 10:05 AM, Caesar Wang wrote:
+ if (!on)
+ reset_control_assert(rstc);
+
+ ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
+ if (ret <
在 2015年06月07日 11:43, Doug Anderson 写道:
Caesar,
On Sat, Jun 6, 2015 at 7:51 PM, Caesar Wang wrote:
@@ -150,13 +159,15 @@ static int __cpuinit rockchip_boot_secondary(unsigned
int cpu,
* sram_base_addr + 4: 0xdeadbeaf
* sram_base_addr + 8: start address for
在 2015年06月06日 04:24, Doug Anderson 写道:
Russell,
On Fri, Jun 5, 2015 at 11:29 AM, Russell King - ARM Linux
wrote:
1) v7_coherency_exit() is specific to v7 CPUs and can't be used by
generic code.
Oh, I see. So (I think) you're saying that perhaps the reason that
Caesar needed his patch w
Verified on url =
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.14
Tested by 176000 cycles are pass with CPU up/dowm test scripts.
Caesar Wang (3):
ARM: rockchip: fix the CPU soft reset
ARM: rockchip: ensure CPU to enter WFI/WFE state
ARM: rockchip: fix
r
[ 4072.587426] CPU3: Booted secondary processor
Signed-off-by: Caesar Wang
Reviewed-by: Doug Anderson
Changes in v5:
- back to v2 cpu on/off flow, As Heiko point out in patch v3.
- delay more time in rockchip_boot_secondary().
From CPU up/down tests, Needed more time to comp
Use the below scripts to check:
scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c
Signed-off-by: Caesar Wang
Changes in v5:
- Add the changelog.
Changes in v4: None
Changes in v3: None
Changes in v2:
- Use the checkpatch.pl -f --subjective to check.
---
arch/arm
ed by chip (hardware) in the future.
Signed-off-by: Caesar Wang
Changes in v5:
- Fix the patch decription.
- Add the changelog.
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v2:
- As Kever points out, Fix the subject typo WFI/WFE.
---
arch/arm/mach-rockchip/pla
在 2015年06月08日 15:11, Caesar Wang 写道:
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In ther other case we need to turn power on and the deassert reset.
In general, the correct flow is:
CPU off
在 2015年06月08日 17:24, Russell King - ARM Linux 写道:
On Mon, Jun 08, 2015 at 03:11:34PM +0800, Caesar Wang wrote:
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In ther other case we need to turn power on
在 2015年06月08日 17:28, Russell King - ARM Linux 写道:
On Mon, Jun 08, 2015 at 03:11:35PM +0800, Caesar Wang wrote:
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index bd40852..5bc2a89 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip
在 2015年06月08日 17:43, Russell King - ARM Linux 写道:
On Mon, Jun 08, 2015 at 03:11:34PM +0800, Caesar Wang wrote:
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 5b4ca3c..bd40852 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip
x the commnet Unified format.
Series-changes: 5
- Add the changelog.
Series-changes: 2
- Use the checkpatch.pl -f --subjective to check.
Caesar Wang (3):
ARM: rockchip: fix the CPU soft reset
ARM: rockchip: ensure CPU to enter WFI/WFE state
ARM: rockchip: fix the SMP code style
arch/arm
Use the below scripts to check:
scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c
Signed-off-by: Caesar Wang
---
Changes in v6:
- fix the commnet Unified format.
Series-changes: 5
- Add the changelog.
Series-changes: 2
- Use the checkpatch.pl -f --subjective to check.
arch
ed by chip (hardware) in the future.
Signed-off-by: Caesar Wang
---
Changes in v6:
- Fix the delay 1ms describing.
Series-changes: 5
- Fix the patch decription.
- Add the changelog.
Series-changes: 2
- As Kever points out, Fix the subject typo WFI/WFE.
arch/arm/mach-rockchip/platsmp.c | 7 +
the same as cpu0, if the cpu0 early wake up, perhaps the other cpus
can't startup. As we know, the cpu0 can wake up when the cpu1/2/3 write
the 'sram+4/8' and send the sev.
Anyway.
At the moment, 1ms delay will be happy work for cpu up/down scripts test.
Signed-off-by: Caesa
在 2015年06月09日 05:54, Caesar Wang 写道:
在 2015年06月08日 17:24, Russell King - ARM Linux 写道:
On Mon, Jun 08, 2015 at 03:11:34PM +0800, Caesar Wang wrote:
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In
在 2015年06月18日 16:29, Srinivas Kandagatla 写道:
On 18/06/15 08:05, Stefan Wahren wrote:
Hi Srinivas,
Am 16.06.2015 um 12:54 schrieb Srinivas Kandagatla:
On 16/06/15 11:06, Caesar Wang wrote:
Hi Srinivas,
在 2015年06月16日 17:21, Srinivas Kandagatla 写道:
Hi Stefan,
On 16/06/15 09:52, Stefan
n and Voltage Domain Summary' these power domains
are positioned directly under VD_LOGIC, so fix that in 'rk3399.dtsi'.
Signed-off-by: Johan Jonker
Reviewed-by: Caesar Wang
Thanks,
-Caesar
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++--
1 file chan
Signed-off-by: Caesar Wang
---
Documentation/devicetree/bindings/pwm/pwm-rockchip.txt | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
index 3182126
So I have to add the new pwm for next genenation Rockchip SoCs.
Tested on RK3288 SDK board.
Changes in v2:
* address comments from Beniamino Galvani Reding:
- remove #include .
- of_iomap be removed,and devm_ioremap replace it.
- remove a line no be used.
Caesar Wang (2):
Suggested-by: Beniamino Galvani
Signed-off-by: Caesar Wang
---
drivers/pwm/pwm-rockchip.c | 97 +-
1 file changed, 79 insertions(+), 18 deletions(-)
diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
index eec2145..3628a1b 100644
Eduardo,
在 2014/9/10 20:46, Eduardo Valentin 写道:
Hello Caesar,
On Wed, Sep 10, 2014 at 12:39:07PM +0800, Caesar Wang wrote:
Dear Eduardo,
I'm sorry for it.
I just received this message.Maybe my mailbox has a problem.
No problems. You can take your time.
Thank you for your comment
在 2014年09月18日 04:13, Dmitry Torokhov 写道:
On Wed, Sep 17, 2014 at 12:48:16PM -0700, Doug Anderson wrote:
Caesar,
On Tue, Sep 16, 2014 at 8:59 PM, Caesar Wang wrote:
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Signed-off-by: zhaoyifeng
Signed-off-by
Dear Dmitry,
在 2014年09月18日 01:02, Dmitry Torokhov 写道:
Hi Caesar,
On Wed, Sep 17, 2014 at 11:59:10AM +0800, Caesar Wang wrote:
Thermal is TS-ADC Controller module supports
user-defined mode and automatic mode.
User-defined mode refers,TSADC all the control signals entirely by
software
Tomeu,
在 2014年09月18日 17:27, Tomeu Vizoso 写道:
On 17 September 2014 05:59, Caesar Wang wrote:
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Hi Caesar,
is there any reason to not use the existing thermal bindings? You can
find a description in
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Signed-off-by: zhaoyifeng
Signed-off-by: Caesar Wang
---
.../bindings/thermal/rockchip-thermal.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation
ame TSADC_XXX->TSADCV2_XXX,it eill ready to merge compatible other
SoCs.
- fix a identation
- remove clk_set_rate(),it's no necessary.
- fix the SIMPLE_DEV_PM_OPS() function style.
Tested on rk3288 SDK board and pinky-v1 board.
Caesar Wang (3):
thermal: roc
Signed-off-by: Caesar Wang
---
arch/arm/boot/dts/rk3288.dtsi | 44 +++
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 36be7bb..6092d34 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch
: Caesar Wang
---
drivers/thermal/Kconfig| 10 +
drivers/thermal/Makefile | 1 +
drivers/thermal/rockchip_thermal.c | 605 +
3 files changed, 616 insertions(+)
create mode 100644 drivers/thermal/rockchip_thermal.c
diff --git a/drivers
x27;s no necessary.
- fix the SIMPLE_DEV_PM_OPS() function style.
Caesar Wang (5):
thermal: rockchip: add driver for thermal
dt-bindings: document Rockchip thermal
ARM: dts: add RK3xxx CPU Thermal data
ARM: dts: add main Thermal info to rk3288
ARM: dts: enable Thermal on rk3288-evb
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Signed-off-by: zhaoyifeng
Signed-off-by: Caesar Wang
---
.../bindings/thermal/rockchip-thermal.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation
when a thermal shutdown at 125C.Via GPIO give PMIC,
Reset the entire chip.
Signed-off-by: Caesar Wang
---
arch/arm/boot/dts/rk3288-evb.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index 2964370..a6872aa
This patch changes a dtsi file to contain the thermal data
on RK3288 and later SoCs. This data will
enable a thermal shutdown over 125C.
Signed-off-by: Caesar Wang
---
arch/arm/boot/dts/rk3xxx-cpu-thermal.dtsi | 32 +++
1 file changed, 32 insertions(+)
create mode
This patch is depend on rk3xxx-cpu-thermal.dtsi,or
it will compile error.
Signed-off-by: Caesar Wang
---
arch/arm/boot/dts/rk3288.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 36be7bb
: Caesar Wang
---
drivers/thermal/Kconfig| 10 +
drivers/thermal/Makefile | 1 +
drivers/thermal/rockchip_thermal.c | 608 +
3 files changed, 619 insertions(+)
create mode 100644 drivers/thermal/rockchip_thermal.c
diff --git a/drivers
dt-bindings in rockchip-thermal.txt
- remove Author mark
- rename TSADC_XXX->TSADCV2_XXX,it eill ready to merge compatible other
SoCs.
- fix a identation
- remove clk_set_rate(),it's no necessary.
- fix the SIMPLE_DEV_PM_OPS() function style.
Tested on
: Caesar Wang
---
drivers/thermal/Kconfig| 9 +
drivers/thermal/Makefile | 1 +
drivers/thermal/rockchip_thermal.c | 790 +
3 files changed, 800 insertions(+)
create mode 100644 drivers/thermal/rockchip_thermal.c
diff --git a/drivers
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Signed-off-by: zhaoyifeng
Signed-off-by: Caesar Wang
---
.../bindings/thermal/rockchip-thermal.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644
Documentation
Signed-off-by: Caesar Wang
---
arch/arm/boot/dts/rk3288-evb.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index 2964370..b68d21b 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm
Signed-off-by: Caesar Wang
---
arch/arm/boot/dts/rk3288.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 36be7bb..ba7ad94 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
This patch added to support the PWM controller found on
RK3288 SoC.
Signed-off-by: Caesar Wang
---
drivers/pwm/pwm-rockchip.c | 141 +++--
1 file changed, 122 insertions(+), 19 deletions(-)
diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm
in rockchip_pwm_data struct
- remove the devm_ioremap(),fixed in lcdc driver.
Changes in v2:
* address comments from Beniamino Galvani:
- remove #include .
- of_iomap be removed,and devm_ioremap replace it.
- remove a line no be used.
Caesar Wang (2):
pwm: rockchip: document R
Document new compatible for PWM founding on RK3288 SoC
Signed-off-by: Caesar Wang
---
Documentation/devicetree/bindings/pwm/pwm-rockchip.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
b/Documentation/devicetree
This patch added to support the PWM controller found on
RK3288 SoC.
Signed-off-by: Caesar Wang
---
drivers/pwm/pwm-rockchip.c | 124 ++---
1 file changed, 105 insertions(+), 19 deletions(-)
diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm
Document new compatible for PWM founding on RK3288 SoC
Signed-off-by: Caesar Wang
---
Documentation/devicetree/bindings/pwm/pwm-rockchip.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
b/Documentation/devicetree
ddress comments from Beniamino Galvani:
- remove #include .
- of_iomap be removed,and devm_ioremap replace it.
- remove a line no be used.
Caesar Wang (2):
pwm: rockchip: document RK3288 SoC compatible
pwm: rockchip: Added to support for RK3288 SoC
.../devicetree/bindings/pwm/pwm-rock
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Signed-off-by: zhaoyifeng
Signed-off-by: Caesar Wang
---
.../bindings/thermal/rockchip-thermal.txt | 33
1 file changed, 33 insertions(+)
create mode 100644
Documentation
-off-by: Caesar Wang
---
drivers/thermal/Kconfig|9 +
drivers/thermal/Makefile |1 +
drivers/thermal/rockchip_thermal.c | 659
3 files changed, 669 insertions(+)
create mode 100644 drivers/thermal/rockchip_thermal.c
diff --git a
This series adds support for the thermal Found on Rockhip SoCs.
Caesar Wang (2):
dt-bindings: document Rockchip thermal
thermal: rockchip: add driver for Rockchip thermal
Tested on rk3288 Board.
.../bindings/thermal/rockchip-thermal.txt | 33 +
drivers/thermal/Kconfig
Hi Heiko,
在 2014年08月24日 07:03, Heiko Stübner 写道:
Hi Caesar,
Am Samstag, 23. August 2014, 08:15:33 schrieb Caesar Wang:
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Signed-off-by: zhaoyifeng
Signed-off-by: Caesar Wang
---
.../bindings/thermal
Heiko,
在 2014年08月24日 07:33, Heiko Stübner 写道:
Am Samstag, 23. August 2014, 08:15:34 schrieb Caesar Wang:
Thermal is TS-ADC Controller module supports user-defined mode and automatic
mode.
User-defined mode refers,TSADC all the control signals entirely by software
writing to register for
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