On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote:
> We use helpers like GENERIC_EVENT_ATTR() to list the generic events in
> sysfs. To avoid name collisions, GENERIC_EVENT_ATTR() requires the perf
> event macros to start with PME.
We got all the raw event codes covered for P7 with the help of
po
On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote:
> On Power7, the DCACHE_SRC field in MMCRA register identifies the memory
> hierarchy level (eg: L2, L3 etc) from which a data-cache miss for a
> marked instruction was satisfied.
>
> Use the 'perf_mem_data_src' object to export this hierarchy lev
On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote:
> +static void power7_get_mem_data_src(union perf_mem_data_src *dsrc,
> + struct pt_regs *regs)
> +{
> + u64 idx;
> + u64 mmcra = regs->dsisr;
> + u64 addr;
> + int ret;
> + unsigned int instr;
> +
> + if
On 09/10/2013 07:36 AM, Michael Ellerman wrote:
> On Fri, 2013-08-30 at 09:54 +0530, Anshuman Khandual wrote:
>> This patchset is the re-spin of the original branch stack sampling
>> patchset which introduced new PERF_SAMPLE_BRANCH_COND filter. This patchset
>> also en
On 09/26/2013 04:44 PM, Stephane Eranian wrote:
> So you are saying that the HW filter is exclusive. That seems odd. But
> I think it is
> because of the choices is ANY. ANY covers all the types of branches. Therefore
> it does not make a difference whether you add COND or not. And
> vice-versa, if
# PERF_SAMPLE_BRANCH_ANY_CALL
bl sw_4_2 # PERF_SAMPLE_BRANCH_ANY_CALL
# Restore LR
mtlr 25
blr # PERF_SAMPLE_BRANCH_ANY_RET
Adding documentation support for conditional branch filter.
Signed-off-by: Anshuman Khandual
Reviewed-by: Stephane Eranian
---
tools/perf/Documentation/perf-record.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/Documentation/perf-record.txt
b/tools/perf
This patch adds conditional branch filtering support,
enabling it for PERF_SAMPLE_BRANCH_COND in perf branch
stack sampling framework by utilizing an available
software filter X86_BR_JCC.
Signed-off-by: Anshuman Khandual
Reviewed-by: Stephane Eranian
---
arch/x86/kernel/cpu
(2) bctarl
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/perf_event_server.h | 2 +-
arch/powerpc/perf/core-book3s.c | 200 +--
arch/powerpc/perf/power8-pmu.c | 19 ++-
3 files changed, 198 insertions(+), 23 de
instructions.
Signed-off-by: Anshuman Khandual
Reviewed-by: Stephane Eranian
---
include/uapi/linux/perf_event.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 0b1df41..5da52b6 100644
--- a/include/uapi
Adding perf record support for new branch stack filter criteria
PERF_SAMPLE_BRANCH_COND.
Signed-off-by: Anshuman Khandual
---
tools/perf/builtin-record.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c
index ecca62e..802d11d 100644
Enables conditional branch filter support for POWER8
utilizing MMCRA register based filter and also invalidates
a BHRB branch filter combination involving conditional
branches.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power8-pmu.c | 10 ++
1 file changed, 10 insertions
On 08/30/2013 05:18 PM, Stephane Eranian wrote:
> 2013/8/30 Anshuman Khandual
>> >
>> > This patchset is the re-spin of the original branch stack sampling
>> > patchset which introduced new PERF_SAMPLE_BRANCH_COND filter. This patchset
>> > also en
On 09/26/2013 12:01 PM, Michael Ellerman wrote:
> +int powernv_hwrng_present(void)
> +{
> + return __raw_get_cpu_var(powernv_rng) != NULL;
> +}
> +
> static unsigned long rng_whiten(struct powernv_rng *rng, unsigned long val)
> {
> unsigned long parity;
> @@ -42,6 +48,17 @@ static unsig
On 08/30/2013 05:18 PM, Stephane Eranian wrote:
> 2013/8/30 Anshuman Khandual
>> >
>> > This patchset is the re-spin of the original branch stack sampling
>> > patchset which introduced new PERF_SAMPLE_BRANCH_COND filter. This patchset
>> > also en
On 09/21/2013 12:11 PM, Anshuman Khandual wrote:
> On 08/30/2013 05:18 PM, Stephane Eranian wrote:
>> 2013/8/30 Anshuman Khandual
>>>>
>>>> This patchset is the re-spin of the original branch stack sampling
>>>> patchset which introduced new
On 09/21/2013 12:25 PM, Stephane Eranian wrote:
> On Tue, Sep 10, 2013 at 4:06 AM, Michael Ellerman
> wrote:
>> >
>> > On Fri, 2013-08-30 at 09:54 +0530, Anshuman Khandual wrote:
>>> > > This patchset is the re-spin of the original branch stack samplin
On 09/25/2013 07:49 AM, Michael Ellerman wrote:
> On Mon, 2013-09-23 at 14:45 +0530, Anshuman Khandual wrote:
>> On 09/21/2013 12:25 PM, Stephane Eranian wrote:
>>> On Tue, Sep 10, 2013 at 4:06 AM, Michael Ellerman
>>> wrote:
>>>>>
>>>>> O
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/perf_event_server.h | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_server.h
index 9710be3..e3f10bb 100644
On 11/16/2012 05:12 PM, Paul Mackerras wrote:
> On Fri, Nov 16, 2012 at 02:29:04PM +0530, Anshuman Khandual wrote:
>> Signed-off-by: Anshuman Khandual
>
> That's not a sufficient description of why you are making this
> change. In particular, what is the motivation
On 04/16/2013 10:53 PM, Segher Boessenkool wrote:
>> +/* r3 = n (where n = [0-1023])
>> + * The maximum number of BHRB entries supported with PPC_MFBHRBE
>> instruction
>> + * is 1024. We have limited number of table entries here as POWER8
>> implements
>> + * 32 BHRB entries.
>> + */
>> +
>> +/*
On 04/17/2013 12:38 PM, Michael Ellerman wrote:
> On Tue, Apr 16, 2013 at 09:24:10PM +0530, Anshuman Khandual wrote:
>> This patch provides basic enablement for perf branch stack sampling framework
>> on POWER8 processor with a new PMU feature called BHRB (Branch History
>&
On 04/17/2013 05:37 PM, Anshuman Khandual wrote:
> On 04/17/2013 12:38 PM, Michael Ellerman wrote:
>> On Tue, Apr 16, 2013 at 09:24:10PM +0530, Anshuman Khandual wrote:
>>> This patch provides basic enablement for perf branch stack sampling
>>> framework
>>>
This patch adds couple of generic functions to power_pmu structure
which would configure the BHRB and it's filters. It also adds
representation of the number of BHRB entries present on the PMU.
A new PMU flag PPMU_BHRB would indicate presence of BHRB feature.
Signed-off-by: Anshuman Kha
This patch adds new POWER8 instruction encoding for reading
the BHRB buffer entries and also clearing it. Encoding for
"clrbhrb" instruction is straight forward. But "mfbhrbe"
encoding involves reading a certain index of BHRB buffer
into a particular GPR register.
Signed-off-b
passing to the user space. This also enables
processing of BHRB data and converts them into generic perf branch
stack data format.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/perf_event_server.h | 1 +
arch/powerpc/perf/core-book3s.c | 167
from perf_event_bhrb.c into
core-book3s.c
- Improved documentation for the patchset
Anshuman Khandual (5):
powerpc, perf: Add new BHRB related instructions for POWER8
powerpc, perf: Add basic assembly code to read BHRB entries on POWER8
powerpc, perf: Add new BHRB related generic functions
This patch populates BHRB specific data for power_pmu structure. It
also implements POWER8 specific BHRB filter and configuration functions.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power8-pmu.c | 57 +-
1 file changed, 56 insertions(+), 1
-deterministic results.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/Makefile | 2 +-
arch/powerpc/perf/bhrb.S | 44
2 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/perf/bhrb.S
diff --git a/arch/powerpc/perf
On 04/22/2013 05:11 AM, Michael Ellerman wrote:
> On Thu, Apr 18, 2013 at 05:56:12PM +0530, Anshuman Khandual wrote:
>> This patch adds new POWER8 instruction encoding for reading
>> the BHRB buffer entries and also clearing it. Encoding for
>> "clrbhrb" instruction
On 04/22/2013 08:20 AM, Michael Neuling wrote:
> Michael Ellerman wrote:
>
>> On Mon, Apr 22, 2013 at 11:13:43AM +1000, Michael Neuling wrote:
>>> Michael Ellerman wrote:
>>>
>>>> On Thu, Apr 18, 2013 at 05:56:12PM +0530, Anshuman Khandual wrote:
&g
On 04/22/2013 08:20 AM, Michael Neuling wrote:
> Michael Ellerman wrote:
>
>> On Mon, Apr 22, 2013 at 11:13:43AM +1000, Michael Neuling wrote:
>>> Michael Ellerman wrote:
>>>
>>>> On Thu, Apr 18, 2013 at 05:56:12PM +0530, Anshuman Khandual wrote:
&g
This patch adds couple of generic functions to power_pmu structure
which would configure the BHRB and it's filters. It also adds
representation of the number of BHRB entries present on the PMU.
A new PMU flag PPMU_BHRB would indicate presence of BHRB feature.
Signed-off-by: Anshuman Kha
This patch populates BHRB specific data for power_pmu structure. It
also implements POWER8 specific BHRB filter and configuration functions.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power8-pmu.c | 57 +-
1 file changed, 56 insertions(+), 1
-deterministic results.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/Makefile | 2 +-
arch/powerpc/perf/bhrb.S | 44
2 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/perf/bhrb.S
diff --git a/arch/powerpc/perf
passing to the user space. This also enables
processing of BHRB data and converts them into generic perf branch
stack data format.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/perf_event_server.h | 1 +
arch/powerpc/perf/core-book3s.c | 167
nd a general purpose register to put the value which was
read from the buffer entry.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/ppc-opcode.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
from perf_event_bhrb.c into
core-book3s.c
- Improved documentation for the patchset
Changes in V4
-
- Incorporated review comments on V3 regarding new instruction encoding
Anshuman Khandual (5):
powerpc, perf: Add new BHRB related instructions for POWER8
powerpc, perf: Add basic
>
> AFAICT, Power7 supports one extra level in the cache-hierarchy, so we propose
> to add a new cache level, REM_CCE3 shown above.
>
> To maintain consistency in terminology (i.e 2-hops = remote, 3-hops =
> distant),
> I propose leaving the REM_MEM1 unused and adding another level, REM_MEM3.
>
Fixing some conditions during BHRB entry processing.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/core-book3s.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 09db68d..1de2756 100644
The 'to' field inside branch entries might contain stale values from previous
PMU interrupt instances which had indirect branches. So clear all the values
before reading a fresh set of BHRB entries after a PMU interrupt.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/core-bo
On 05/06/2013 04:41 PM, Michael Neuling wrote:
> Anshuman Khandual wrote:
>
>> Fixing some conditions during BHRB entry processing.
>
> I think we can simplify this a lot more... something like the below.
>
I feel that the conditional handling of the invalid BHRB entr
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/perf_event_server.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_server.h
index 57b42da..3f0c15c 100644
--- a/arch/powerpc/include/asm
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power8-pmu.c | 57 +-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 106ae0b..153408c 100644
--- a/arch/powerpc/perf
This patch provides basic enablement for perf branch stack sampling framework
on POWER8 processor with a new PMU feature called BHRB (Branch History Rolling
Buffer).
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/core-book3s.c | 96 +++--
arch/powerpc
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/Makefile | 2 +-
arch/powerpc/perf/bhrb.S | 34 ++
2 files changed, 35 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/perf/bhrb.S
diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf
This patch adds new instructions support for reading various
BHRB entries and also clearing the BHRB buffer.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/ppc-opcode.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch
% top libc-2.11.2.so[k] vfprintf
libc-2.11.2.so[k] vfprintf
0.92% top top [k] _init
[unknown] [k] 0x0fe037f4
Anshuman Khandual (5
% top top [k] _init
[unknown] [k] 0x0fe037f4
Changes in V2
--
- Added copyright messages to the newly created files
- Modified couple of commit messages
Anshuman Khandual (5):
powerpc, perf: Add new BHRB related
This patch provides basic enablement for perf branch stack sampling framework
on POWER8 processor with a new PMU feature called BHRB (Branch History Rolling
Buffer).
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/core-book3s.c | 96 +++--
arch/powerpc
This patch adds new instructions support for reading various
BHRB entries and also clearing the BHRB buffer.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/ppc-opcode.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch
Defines BHRB functions, data and flags for POWER8
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power8-pmu.c | 57 +-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
This patch adds the basic assembly code to read BHRB entries
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/Makefile | 2 +-
arch/powerpc/perf/bhrb.S | 44
2 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc
This patch adds some new BHRB related generic functions, data and flags
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/perf_event_server.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm
Completely ignore BHRB privilege state filter request as we are
already configuring MMCRA register with privilege state filtering
attribute for the accompanying PMU event. This would help achieve
cleaner user space interaction for BHRB.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf
.data.old test-mmap-ring
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.002 MB perf.data (~102 samples) ]
(2) The second patch fixes context migration for BHRB filter configuration
Anshuman Khandual (2):
powerpc, perf: Ignore separate BHRB privilege
When the task moves around the system, the corresponding cpuhw
per cpu strcuture should be popullated with the BHRB filter
request value so that PMU could be configured appropriately with
that during the next call into power_pmu_enable().
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf
instructions.
Signed-off-by: Anshuman Khandual
---
include/uapi/linux/perf_event.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index fb104e5..cb0de86 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include
Adding documentation support for conditional branch filter.
Signed-off-by: Anshuman Khandual
---
tools/perf/Documentation/perf-record.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/Documentation/perf-record.txt
b/tools/perf/Documentation/perf-record.txt
Enables conditional branch filter support for POWER8
utilizing MMCRA register based filter and also invalidates
a BHRB branch filter combination involving conditional
branches.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power8-pmu.c | 10 ++
1 file changed, 10 insertions
From: Peter Zijlstra
This patch adds conditional branch filtering support,
enabling it for PERF_SAMPLE_BRANCH_COND in perf branch
stack sampling framework by utilizing an available
software filter X86_BR_JCC.
Signed-off-by: Peter Zijlstra
Signed-off-by: Anshuman Khandual
---
arch/x86/kernel
Adding perf record support for new branch stack filter criteria
PERF_SAMPLE_BRANCH_COND.
Signed-off-by: Anshuman Khandual
---
tools/perf/builtin-record.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c
index cdf58ec..833743a 100644
This patchset introduces conditional branch filter in perf branch stack
sampling framework incorporating review comments from Michael Neuling,
Peter Zijlstra and Stephane Eranian.
Anshuman Khandual (5):
perf: New conditional branch filter criteria in branch stack sampling
powerpc, perf
On 05/21/2013 07:25 PM, Stephane Eranian wrote:
> On Thu, May 16, 2013 at 12:15 PM, Michael Neuling wrote:
>> Peter Zijlstra wrote:
>>
>>> On Wed, May 15, 2013 at 03:37:22PM +0200, Stephane Eranian wrote:
On Fri, May 3, 2013 at 2:11 PM, Peter Zijlstra
wrote:
> We should always hav
>
> Your description from patch 0 should be here.
>
Sure, will bring it here.
>
>> diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
>> index f7d1c4f..8ed323d 100644
>> --- a/arch/powerpc/perf/power8-pmu.c
>> +++ b/arch/powerpc/perf/power8-pmu.c
>> @@ -525,16 +525,17
On 05/22/2013 05:53 PM, Stephane Eranian wrote:
> Hi,
>
>
>
> On Wed, May 22, 2013 at 8:43 AM, Anshuman Khandual
> wrote:
>> On 05/21/2013 07:25 PM, Stephane Eranian wrote:
>>> On Thu, May 16, 2013 at 12:15 PM, Michael Neuling wrote:
>>>> Peter Zij
On 05/22/2013 02:29 PM, Anshuman Khandual wrote:
>>
>> Your description from patch 0 should be here.
> Does it sound better ?
>
>>
>>> - if ((br_privilege != 7) && (br_privilege != 0))
>>> - return -1;
>>> +
>>>
> There are 4 options:
> 1. [not a kernel interface] use ptrace to execute the register changing
> command inside the specified pid. The next context switch saves the new
> value in the thread_struct. Dirty hack.
>
> 2. Add a new syscall which would receive pid + register value and do the
> job.
On 10/12/2012 06:58 AM, Sukadev Bhattiprolu wrote:
>
> From 89cb6a25b9f714e55a379467a832ee015014ed11 Mon Sep 17 00:00:00 2001
> From: Sukadev Bhattiprolu
> Date: Tue, 18 Sep 2012 10:59:01 -0700
> Subject: [PATCH] perf: Add a few generic stalled-cycles events
>
> The existing generic event 'stall
On 10/15/2012 10:53 PM, Arun Sharma wrote:
> On 10/15/12 8:55 AM, Robert Richter wrote:
>
> [..]
>> Perf tool works then out-of-the-box with:
>>
>> $ perf record -e cpu/stalled-cycles-fixed-point/ ...
>>
>> The event string can easily be reused by other architectures as a
>> quasi standard.
>
>
On 09/07/2016 08:38 AM, Kees Cook wrote:
> On Tue, Sep 6, 2016 at 1:36 PM, Dave Hansen wrote:
>> On 09/06/2016 01:31 AM, Anshuman Khandual wrote:
>>> [NODE (0)]
>>> ZONELIST_FALLBACK
>>> (0) (node 0) (zone DMA c140c000)
>>>
On 09/06/2016 10:19 PM, Dan Williams wrote:
> Now that track_pfn_insert() is no longer used in the DAX path, it no
> longer needs to comprehend pfn_t values.
>
> Signed-off-by: Dan Williams
> ---
> arch/x86/mm/pat.c |4 ++--
> include/asm-generic/pgtable.h |4 ++--
> mm/memor
tem]
> [Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for
> convenience) to record what (public, well-known) commit your patch series was
> built on]
> [Check https://git-scm.com/docs/git-format-patch for more information]
>
> url:
> https://github.c
)
Signed-off-by: Anshuman Khandual
---
Changes in V4:
- Explicitly included mmzone.h header inside page_alloc.c
- Changed the kernel address printing from %lx to %pK
Changes in V3:
- Moved all these new sysfs code inside CONFIG_NUMA
Changes in V2:
- Added more details into the commit message
- Added
On 09/07/2016 10:16 PM, Huang, Ying wrote:
> From: Huang Ying
>
> In this patch, the size of the swap cluster is changed to that of the
> THP (Transparent Huge Page) on x86_64 architecture (512). This is for
> the THP swap support on x86_64. Where one swap cluster will be used to
> hold the con
On 09/07/2016 10:16 PM, Huang, Ying wrote:
> From: Huang Ying
>
> This patch make it possible to charge or uncharge a set of continuous
> swap entries in the swap cgroup. The number of swap entries is
> specified via an added parameter.
>
> This will be used for the THP (Transparent Huge Page)
On 09/07/2016 10:16 PM, Huang, Ying wrote:
> From: Huang Ying
>
> The swap cluster allocation/free functions are added based on the
> existing swap cluster management mechanism for SSD. These functions
> don't work for the rotating hard disks because the existing swap cluster
> management mechan
On 09/07/2016 10:16 PM, Huang, Ying wrote:
> From: Huang Ying
>
> This patch make it possible to charge or uncharge a set of continuous
> swap entries in the swap cgroup. The number of swap entries is
> specified via an added parameter.
>
> This will be used for the THP (Transparent Huge Page)
On 09/07/2016 10:16 PM, Huang, Ying wrote:
> From: Huang Ying
>
> The swap cluster allocation/free functions are added based on the
> existing swap cluster management mechanism for SSD. These functions
> don't work for the rotating hard disks because the existing swap cluster
> management mechan
On 09/07/2016 10:16 PM, Huang, Ying wrote:
> From: Huang Ying
>
> With this patch, a THP (Transparent Huge Page) can be added/deleted
> to/from the swap cache as a set of sub-pages (512 on x86_64).
>
> This will be used for the THP (Transparent Huge Page) swap support.
> Where one THP may be add
On 09/07/2016 10:16 PM, Huang, Ying wrote:
> From: Huang Ying
>
> In this patch, the size of the swap cluster is changed to that of the
> THP (Transparent Huge Page) on x86_64 architecture (512). This is for
> the THP swap support on x86_64. Where one swap cluster will be used to
> hold the con
zone_names[] is used to identify any zone given it's index which
can be used in many other places. So moving the definition into
include/linux/mmzone.h for broader access.
Signed-off-by: Anshuman Khandual
---
include/linux/mmzone.h | 17 +
mm/page_alloc.c
)
(3) (node 2) (zone DMA c002)
ZONELIST_NOFALLBACK
(0) (node 3) (zone DMA c003)
Signed-off-by: Anshuman Khandual
---
drivers/base/memory.c | 46 ++
1 file changed, 46 insertions(+)
diff --git a/drivers/base
On 09/01/2016 02:40 AM, Andrew Morton wrote:
> On Wed, 31 Aug 2016 08:55:49 +0530 Anshuman Khandual
> wrote:
>
>> zone_names[] is used to identify any zone given it's index which
>> can be used in many other places. So moving the definition into
>> include/l
On 09/01/2016 02:42 AM, Andrew Morton wrote:
> On Wed, 31 Aug 2016 08:55:50 +0530 Anshuman Khandual
> wrote:
>
>> Each individual node in the system has a ZONELIST_FALLBACK zonelist
>> and a ZONELIST_NOFALLBACK zonelist. These zonelists decide fallback
>> o
On 06/20/2017 10:40 AM, Balbir Singh wrote:
> On Fri, 2017-06-16 at 20:52 -0700, Ram Pai wrote:
>> Memory protection keys enable applications to protect its
>> address space from inadvertent access or corruption from
>> itself.
>
> I presume by itself you mean protection between threads?
Between
On 06/17/2017 09:22 AM, Ram Pai wrote:
> The Documentaton file is moved from x86 into the generic area,
> since this feature is now supported by more than one archs.
>
> Signed-off-by: Ram Pai
> ---
> Documentation/vm/protection-keys.txt | 110
> ++
> Documentat
On 06/17/2017 09:22 AM, Ram Pai wrote:
> Added test support for PowerPC implementation off protection keys.
>
> Signed-off-by: Ram Pai
First of all, there are a lot of instances where we use *pkru*
named functions on power even the real implementations have
taken care of doing appropriate things
On 06/19/2017 11:29 PM, Ram Pai wrote:
> On Mon, Jun 19, 2017 at 09:06:13PM +1000, Michael Ellerman wrote:
>> Ram Pai writes:
>>
>>> Signed-off-by: Ram Pai
>>> ---
>>> arch/powerpc/kernel/exceptions-64s.S | 16 ++--
>>> 1 file changed, 10 insertions(+), 6 deletions(-)
>>>
>>> diff --
On 06/17/2017 09:22 AM, Ram Pai wrote:
> The value of the AMR register at the time of exception
> is made available in gp_regs[PT_AMR] of the siginfo.
>
> This field can be used to reprogram the permission bits of
> any valid pkey.
>
> Similarly the value of the pkey, whose protection got violate
On 06/17/2017 09:22 AM, Ram Pai wrote:
> Handle Data and Instruction exceptions caused by memory
> protection-key.
>
> Signed-off-by: Ram Pai
> (cherry picked from commit a5e5217619a0c475fe0cacc3b0cf1d3d33c79a09)
To which tree this commit belongs to ?
>
> Conflicts:
> arch/powerpc/includ
On 06/17/2017 09:22 AM, Ram Pai wrote:
> Replace the magic number used to check for DSI exception
> with a meaningful value.
>
> Signed-off-by: Ram Pai
> ---
> arch/powerpc/include/asm/reg.h | 9 -
> arch/powerpc/kernel/exceptions-64s.S | 2 +-
> 2 files changed, 9 insertions(+), 2
On 06/17/2017 09:22 AM, Ram Pai wrote:
> Map the PTE protection key bits to the HPTE key protection bits,
> while creatiing HPTE entries.
>
> Signed-off-by: Ram Pai
> ---
> arch/powerpc/include/asm/book3s/64/mmu-hash.h | 5 +
> arch/powerpc/include/asm/pkeys.h | 7 +++
> ar
On 06/17/2017 09:22 AM, Ram Pai wrote:
> Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6
> in the 4K backed hpte pages. These bits continue to be used
> for 64K backed hpte pages in this patch, but will be freed
> up in the next patch.
The counting 3, 4, 5 and 6 are in BE format I believ
On 06/17/2017 09:22 AM, Ram Pai wrote:
> Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6
> in the 64K backed hpte pages. This along with the earlier
> patch will entirely free up the four bits from 64K PTE.
>
> This patch does the following change to 64K PTE that is
> backed by 64K hpte.
On 06/21/2017 05:26 AM, Ram Pai wrote:
> On Tue, Jun 20, 2017 at 12:24:53PM +0530, Anshuman Khandual wrote:
>> On 06/17/2017 09:22 AM, Ram Pai wrote:
>>> The value of the AMR register at the time of exception
>>> is made available in gp_regs[PT_AMR] of the siginfo.
>
On 06/21/2017 05:13 AM, Ram Pai wrote:
> On Tue, Jun 20, 2017 at 12:54:45PM +0530, Anshuman Khandual wrote:
>> On 06/17/2017 09:22 AM, Ram Pai wrote:
>>> Handle Data and Instruction exceptions caused by memory
>>> protection-key.
>>>
>>> Signed-of
On 06/21/2017 04:53 AM, Ram Pai wrote:
> On Tue, Jun 20, 2017 at 03:50:25PM +0530, Anshuman Khandual wrote:
>> On 06/17/2017 09:22 AM, Ram Pai wrote:
>>> Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6
>>> in the 4K backed hpte pages. These bits continue to
On 06/17/2017 09:22 AM, Ram Pai wrote:
> Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6
> in the 4K backed hpte pages. These bits continue to be used
> for 64K backed hpte pages in this patch, but will be freed
> up in the next patch.
>
> The patch does the following change to the 64K P
On 10/16/2017 02:49 PM, changbin...@intel.com wrote:
> From: Changbin Du
>
> This patch introduced 4 new interfaces to allocate a prepared
> transparent huge page.
> - alloc_transhuge_page_vma
> - alloc_transhuge_page_nodemask
> - alloc_transhuge_page_node
> - alloc_transhuge_page
>
If
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