On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote: > On Power7, the DCACHE_SRC field in MMCRA register identifies the memory > hierarchy level (eg: L2, L3 etc) from which a data-cache miss for a > marked instruction was satisfied. > > Use the 'perf_mem_data_src' object to export this hierarchy level to user > space. Some memory hierarchy levels in Power7 don't map into the arch-neutral > levels. However, since newer generation of the processor (i.e. Power8) uses > fewer levels than in Power7, we don't really need to define new hierarchy > levels just for Power7. > > We instead, map as many levels as possible and approximate the rest. See > comments near dcache-src_map[] in the patch. > > Usage: > > perf record -d -e 'cpu/PM_MRK_GRP_CMPL/' <application> > perf report -n --mem-mode --sort=mem,sym,dso,symbol_daddr,dso_daddr" > > For samples involving load/store instructions, the memory > hierarchy level is shown as "L1 hit", "Remote RAM hit" etc. > # or > > perf record --data <application> > perf report -D > > Sample records contain a 'data_src' field which encodes the > memory hierarchy level: Eg: data_src 0x442 indicates > MEM_OP_LOAD, MEM_LVL_HIT, MEM_LVL_L2 (i.e load hit L2).
Successfully built and boot tested this entire patchset both on a P7 and P8 system. Running some sample tests with ebizzy micro benchmark. Till now got only 0x142 and 0x0 values for data_src object for the sample records. Will experiment around bit more on P7 and P8 systems and post the results. Regards Anshuman -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
