dmaengine: PL08x: Allow using PL08x with sound drivers

This patch serie extend the PL08x driver to allow using it with sound drivers. Sound drivers require the cyclic transfer mode and that tx_status give reliable results. * Patch 1 is a trivial fix * Patch 2 implement the cyclic mode needed by sound drivers * Patch 3 fix the tx_status implementation

[PATCH 3/3] dmaengine: PL08x: Make the transfer status reliable

To reliably get the current DMA position it is not possible to just read the PL08x registers. As several reads are needed the values are not consistent. To overcome this keep track of the position as each LLI finish, this give a coarse but reliable value. Signed-off-by: Alban Bedel --- drivers

[PATCH 1/3] dmaengine: PL08x: Fix reading the byte count in cctl

Signed-off-by: Alban Bedel --- drivers/dma/amba-pl08x.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c index d1cc579..fc8bedf 100644 --- a/drivers/dma/amba-pl08x.c +++ b/drivers/dma/amba-pl08x.c @@ -453,7 +453,8

[PATCH 2/3] dmaengine: PL08x: Add cyclic transfer support

Signed-off-by: Alban Bedel --- drivers/dma/amba-pl08x.c | 184 ++ 1 files changed, 138 insertions(+), 46 deletions(-) diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c index fc8bedf..b097788 100644 --- a/drivers/dma/amba-pl08x.c +++ b

[PATCH] pwm-backlight: Add support for active low PWM backlights

Signed-off-by: Alban Bedel --- .../bindings/video/backlight/pwm-backlight.txt |1 + drivers/video/backlight/pwm_bl.c | 22 ++- include/linux/pwm_backlight.h |1 + 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a

[PATCH] pwm: lpc32xx - Fix the PWM polarity

Signed-off-by: Alban Bedel --- drivers/pwm/pwm-lpc32xx.c |6 +- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index adb87f0..a2704b8 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -51,7

[PATCH 3/3] pwm: lpc32xx - Set the chip base for dynamic allocation

Signed-off-by: Alban Bedel --- drivers/pwm/pwm-lpc32xx.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index f45ce2c..3e63689 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -121,6 +121,7

[PATCH 1/3] pwm: lpc32xx - Fix the PWM polarity

The duty cycles value goes from 1 (99% HIGH) to 256 (0% HIGH) but it is stored modulo 256 in the register as it is only 8 bits wide. Signed-off-by: Alban Bedel --- drivers/pwm/pwm-lpc32xx.c | 17 - 1 files changed, 16 insertions(+), 1 deletions(-) diff --git a/drivers/pwm/pwm

[PATCH 2/3] pwm: lpc32xx - Properly disable the clock on device remove

A single clock is used for all PWMs meaning the clock ref count might be between 0 and N when remove() is called. Instead of a single clk_disable() call pwm_disable() on each PWM, that ensure that clk_disable() is called for each PWM that were still enabled. Signed-off-by: Alban Bedel

[PATCH 0/3] pwm: lpc32xx - Various small fixes

A few fixes for the LPC32 PWM driver: * [PATCH 1/3] pwm: lpc32xx - Fix the PWM polarity * [PATCH 2/3] pwm: lpc32xx - Properly disable the clock on device remove * [PATCH 3/3] pwm: lpc32xx - Set the chip base for dynamic allocation Alban -- To unsubscribe from this list: send the line "unsubscribe

Re: [PATCH] pwm: lpc32xx - Fix the PWM polarity

On Tue, 6 Nov 2012 07:47:22 -0200 Alexandre Pereira da Silva wrote: > Can you test the 0 and 255 values on actual hardware and see the effective > values? 0 -> 0% 1 -> 99% 128 -> 50% 255 -> 1% So yes 0 mean 256. > It may be handled as the RELOADV where 0 really means 256. If so, you

Re: [PATCH] pwm-backlight: Add support for active low PWM backlights

On Tue, 6 Nov 2012 07:44:06 +0100 Thierry Reding wrote: > > --- a/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt > > +++ b/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt > > @@ -14,6 +14,7 @@ Required properties: > > Optional properties: > >- pwm-nam

[PATCH] pwm-backlight: Allow any kind of brightness curve

levels are expected to be in the range from 0 to 255, where 0 is 0% duty and 255 is 100% duty. Signed-off-by: Alban Bedel --- .../bindings/video/backlight/pwm-backlight.txt |8 ++--- drivers/video/backlight/pwm_bl.c | 28 +-- include/linux/pwm_backlight.h

[PATCH] pwm: lpc32xx - Fix the PWM polarity

Signed-off-by: Alban Bedel --- drivers/pwm/pwm-lpc32xx.c |6 +- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index adb87f0..0dc278d 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -51,7

Re: [PATCH] pwm: lpc32xx - Fix the PWM polarity

On Thu, 08 Nov 2012 10:51:35 +0100 Roland Stigge wrote: > On 07/11/12 16:25, Alban Bedel wrote: > > Signed-off-by: Alban Bedel > > --- > > drivers/pwm/pwm-lpc32xx.c |6 +- > > 1 files changed, 5 insertions(+), 1 deletions(-) > > > > diff --git a/

Re: [PATCH] pwm: lpc32xx - Fix the PWM polarity

On Thu, 08 Nov 2012 11:44:48 +0100 Roland Stigge wrote: > On 08/11/12 11:33, Alban Bedel wrote: > > On Thu, 08 Nov 2012 10:51:35 +0100 > > Roland Stigge wrote: > > > >> On 07/11/12 16:25, Alban Bedel wrote: > >>> Signed-off-by: Alban Bedel > &g

[PATCH] pwm: lpc32xx - Fix the PWM polarity

The duty cycles value goes from 1 (99% HIGH) to 256 (0% HIGH) but it is stored modulo 256 in the register as it is only 8 bits wide. Signed-off-by: Alban Bedel --- drivers/pwm/pwm-lpc32xx.c |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/pwm/pwm-lpc32xx.c b

Re: [PATCH] [media] v4l2-async: Always unregister the subdev on failure

On Fri, 1 Jul 2016 13:55:44 +0200 Hans Verkuil wrote: > On 05/11/2016 06:32 PM, Alban Bedel wrote: > > On Wed, 11 May 2016 12:22:44 -0400 > > Javier Martinez Canillas wrote: > > > >> Hello Alban, > >> > >> On 05/11/2016 11:40 AM, Alban Bedel w

[PATCH] usbnet: ax88179_178a: Add support for writing the EEPROM

Implement the .set_eeprom callback to allow setting the MAC address as well as a few other parameters. Note that the EEPROM must have a correct PID/VID checksum set otherwise the SROM is used and reads return the SROM content. Signed-off-by: Alban Bedel --- drivers/net/usb/ax88179_178a.c | 57

[PATCH v2] [media] v4l2-async: Always unregister the subdev on failure

plug these holes. Signed-off-by: Alban Bedel --- Changelog: v2: * Added the missing unbind() calls as suggested by Javier. --- drivers/media/v4l2-core/v4l2-async.c | 29 + 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2

Re: [PATCH] usbnet: ax88179_178a: Add support for writing the EEPROM

On Wed, 24 Aug 2016 16:30:39 +0200 Oliver Neukum wrote: > On Wed, 2016-08-24 at 15:52 +0200, Alban Bedel wrote: > > Implement the .set_eeprom callback to allow setting the MAC address > > as well as a few other parameters. Note that the EEPROM must have a > > correct

Re: [PATCH] usbnet: ax88179_178a: Add support for writing the EEPROM

On Thu, 25 Aug 2016 11:16:36 +0200 Oliver Neukum wrote: > On Wed, 2016-08-24 at 16:40 +0200, Alban Bedel wrote: > > On Wed, 24 Aug 2016 16:30:39 +0200 > > Oliver Neukum wrote: > > > > > On Wed, 2016-08-24 at 15:52 +0200, Alban Bedel wrote: >

[PATCH] gpio: ath79: Convert to the state container design pattern

Turn the ath79 driver into a true driver supporting multiple instances. While at it also removed unneed includes and make use of the BIT() macro. Signed-off-by: Alban Bedel --- This patch apply on top of my previous MIPS GPIO patches that are pending for 4.3, so it might be better to take it

[PATCH 1/4] devicetree: Add bindings for the ATH79 USB phy

Signed-off-by: Alban Bedel --- .../devicetree/bindings/phy/phy-ath79-usb.txt | 18 ++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-ath79-usb.txt diff --git a/Documentation/devicetree/bindings/phy/phy-ath79-usb.txt b

[PATCH 0/4] MIPS: ath79: Add USB support on the TL-WR1043ND

Hi, this serie add a driver for the USB phy on the ATH79 SoCs and enable the USB port on the TL-WR1043ND. The phy controller is really trivial as it only use reset lines. Alban Alban Bedel (4): devicetree: Add bindings for the ATH79 USB phy phy: Add a driver for the ATH79 USB phy MIPS

[PATCH 2/4] phy: Add a driver for the ATH79 USB phy

The ATH79 USB phy is very simple, it only have a reset. On some SoC a second reset is used to force the phy in suspend mode regardless of the USB controller status. Signed-off-by: Alban Bedel --- drivers/phy/Kconfig | 8 +++ drivers/phy/Makefile| 1 + drivers/phy/phy-ath79

[PATCH 3/4] MIPS: ath79: Add the EHCI controller and USB phy to the AR9132 dtsi

Signed-off-by: Alban Bedel --- arch/mips/boot/dts/qca/ar9132.dtsi | 24 1 file changed, 24 insertions(+) diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi b/arch/mips/boot/dts/qca/ar9132.dtsi index fb7734e..665ee84 100644 --- a/arch/mips/boot/dts/qca/ar9132.dtsi +++ b

[PATCH 4/4] MIPS: ath79: Enable the USB port on the TL-WR1043ND

Signed-off-by: Alban Bedel --- arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts index 003015a..cd51199 100644 --- a/arch/mips/boot/dts/qca

[PATCH] reset: Fix of_reset_control_get() for consistent return values

an't be found. This is because the error code returned by of_property_match_string() is just passed down as an index to of_parse_phandle_with_args(), which then returns -EINVAL. To get a consistent return value with both code paths we must return -ENOENT when of_property_match_string()

[PATCH] MIPS: Fix the build on jz4740 after removing the custom gpio.h

Somehow the wrong version of the patch to remove the use of custom gpio.h on mips has been merged. This patch add the missing fixes for a build error on jz4740 because linux/gpio.h doesn't provide any machine specfics definitions anymore. Signed-off-by: Alban Bedel --- arch/mips/jz4740/

[PATCH] phy: Add a driver for the ATH79 USB phy

qualcom name. Signed-off-by: Alban Bedel --- MAINTAINERS | 8 +++ drivers/phy/qualcomm/Kconfig | 11 +++- drivers/phy/qualcomm/Makefile| 1 + drivers/phy/qualcomm/phy-ath79-usb.c | 108 +++ 4 files changed, 127

[PATCH] usb: host: Remove the deprecated ATH79 USB host config options

option when the EHCI platform driver is enabled on the ATH79 platform. Signed-off-by: Alban Bedel --- arch/mips/Kconfig| 1 + drivers/usb/host/Kconfig | 25 - 2 files changed, 1 insertion(+), 25 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index

[PATCH v3 1/3] nvmem: Update the OF binding to use a subnode for the cells list

that we can turn any kind of device in a nvmem provider. While discouraged for new uses the old scheme is still supported for backward compatibility. Signed-off-by: Alban Bedel --- Documentation/devicetree/bindings/nvmem/nvmem.txt | 55 --- drivers/nvmem/core.c

[PATCH v3 0/3] mtd: Add support for reading MTD devices via the nvmem API

binding or an nvmem cell. To avoid this problem we update the nvmem cell binding to use a 'nvmem-cells' subnode with compatible string to hold the list of nvmem cells. This new binding make sure that any kind of device can be used as nvmem provider. Alban Bedel (3): nvmem: Update the

[PATCH v3 3/3] mtd: Add support for reading MTD devices via the nvmem API

Allow drivers that use the nvmem API to read data stored on MTD devices. For this the mtd devices are registered as read-only NVMEM providers. On OF systems only devices that have the 'nvmem-provider' property are registered, on non-OF system all MTD devices are registered. Signed-off

[PATCH v3 2/3] doc: bindings: Add bindings documentation for mtd nvmem

Config data for drivers, like MAC addresses, is often stored in MTD. Add a binding that define how such data storage can be represented in device tree. Signed-off-by: Alban Bedel --- Changelog: v2: * Added a "Required properties" section with the nvmem-provider property v3: * Fix

[PATCH v2] gpio: ath79: Fix potential NULL dereference in ath79_gpio_probe()

!= res == NULL e = devm_ioremap(e1, res->start, e2); Signed-off-by: Wei Yongjun [al...@free.fr: Fixed patch to apply on current tree] Signed-off-by: Alban Bedel --- drivers/gpio/gpio-ath79.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-ath79.c b/drivers/gpio/gpio-ath7

[PATCH 1/8] nvmem: core: Set the provider read-only when no write callback is given

If no write callback is given the device should be marked as read-only. While at it also move from a bit or to a logical or as that is a logical expression. Signed-off-by: Alban Bedel --- drivers/nvmem/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/nvmem

[PATCH 2/8] nvmem: core: Fix of_nvmem_cell_get() for optional cells

of_nvmem_cell_get() should return -ENOENT when a cell isn't defined, otherwise callers can't distinguish between a missing cell and other errors. Signed-off-by: Alban Bedel --- drivers/nvmem/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvme

[PATCH 0/8] nvmem: Various small fixes and improvements

Hi, this series is mostly small bug fixes, but also add a new API to make things simpler in drivers that need to request an optional cell. Alban Bedel (8): nvmem: core: Set the provider read-only when no write callback is given nvmem: core: Fix of_nvmem_cell_get() for optional cells

[PATCH 6/8] nvmem: core: Always reference the device returned by nvmem_device_get()

ement the reference count like it is done in the DT path. To fix this we replace the call to nvmem_find() with a call to __nvmem_device_get() which does all the referencing and return a proper ERR_PTR in case of error. Signed-off-by: Alban Bedel --- drivers/nvmem/core.c | 2 +- 1 file chang

[PATCH 4/8] nvmem: core: Fix cell lookup when no cell is found

struct nvmem_cell the iteration variable then contains an invalid value. This is easily solved by using a variable to iterate over the list and one to return the cell found. Signed-off-by: Alban Bedel --- drivers/nvmem/core.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions

[PATCH 5/8] nvmem: core: Properly handle connection ID in of_nvmem_device_get()

properly implement an optional connection. Return -ENOENT instead to let the caller know that the connection doesn't exists. Signed-off-by: Alban Bedel --- drivers/nvmem/core.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/nvmem/core.c b/drivers/nvmem/c

[PATCH 3/8] nvmem: Add nvmem_cell_get_optional and devm_nvmem_cell_get_optional

Add helper functions to make the driver code simpler when a cell is optional. Using these functions just return NULL when the cell doesn't exists or if nvmem is disabled. Signed-off-by: Alban Bedel --- drivers/nvmem/core.c | 48 ++ include/linux/

[PATCH 7/8] nvmem: core: Fix device reference leak

: Alban Bedel --- drivers/nvmem/core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index 2fa97b373601..176fe72f4eb5 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -811,6 +811,7 @@ static struct nvmem_device *__nvmem_device_get

[PATCH 8/8] nvmem: core: Avoid useless iterations in nvmem_cell_get_from_lookup()

Once the correct cell has been found there is no need to continue iterating, just stop there. While at it replace the goto used to leave the loop with simple break statements. Signed-off-by: Alban Bedel --- drivers/nvmem/core.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff

[PATCH 1/2] phy: ath79-usb: Fix the power on error path

In the power on function the error path doesn't return the suspend override to its proper state. It should should deassert this reset line to enable the suspend override. Signed-off-by: Alban Bedel --- drivers/phy/qualcomm/phy-ath79-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 del

[PATCH 1/2] phy: ath79-usb: Fix the power on error path

In the power on function the error path doesn't return the suspend override to its proper state. It should should deassert this reset line to enable the suspend override. Signed-off-by: Alban Bedel --- drivers/phy/qualcomm/phy-ath79-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 del

[PATCH] MIPS: ath79: Enable OF serial ports in the default config

CONFIG_SERIAL_OF_PLATFORM is needed to get a working console on the OF boards, enable it in the default config to get a working setup out of the box. Signed-off-by: Alban Bedel --- arch/mips/configs/ath79_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/configs

[PATCH 2/2] phy: ath79-usb: Fix the main reset name to match the DT binding

g it. This patch fix the driver to match the new binding. Signed-off-by: Alban Bedel --- drivers/phy/qualcomm/phy-ath79-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-ath79-usb.c b/drivers/phy/qualcomm/phy-ath79-usb.c index f7d64f3910b4..09

[PATCH v3 01/12] devicetree: Add bindings for the SoC of the ATH79 family

Signed-off-by: Alban Bedel --- .../devicetree/bindings/mips/ath79-soc.txt | 21 + 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ath79-soc.txt diff --git a/Documentation/devicetree/bindings/mips/ath79-soc.txt b

[PATCH v3 00/12] MIPS: ath79: Add OF support and DTS for TL-WR1043ND

use ePAPR names * Fixed the qca9550 compatible string in the PLL bindings and driver * Fixed the example in the GPIO controller binding * Moved the new vendor entry to the correct place Alban Bedel (12): devicetree: Add bindings for the SoC of the ATH79 family MIPS: ath79: Add

[PATCH v3 02/12] MIPS: ath79: Add basic device tree support

Add the bare minimum to load a device tree. Signed-off-by: Alban Bedel --- v3: * Removed the empty Builtin devicetree menu --- arch/mips/Kconfig | 1 + arch/mips/ath79/machtypes.h | 1 + arch/mips/ath79/setup.c | 27 ++- 3 files changed, 28 insertions

[PATCH v3 04/12] devicetree: Add bindings for the ATH79 interrupt controllers

Signed-off-by: Alban Bedel --- v2: * Fixed the node names to respect ePAPR * Removed the unneeded @0 on the node name --- .../interrupt-controller/qca,ath79-cpu-intc.txt| 44 ++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings

[PATCH v3 03/12] devicetree: Add bindings for the ATH79 DDR controllers

The DDR controller of the ARxxx and AR9xxx families provides an interface to flush the FIFO between various devices and the DDR. This is mainly used by the IRQ controller to flush the FIFO before running the interrupt handler of such devices. Signed-off-by: Alban Bedel --- v2: * Fix the node

[PATCH v3 05/12] devicetree: Add bindings for the ATH79 MISC interrupt controllers

Signed-off-by: Alban Bedel --- v2: * Fixed the node names to respect ePAPR --- .../interrupt-controller/qca,ath79-misc-intc.txt | 30 ++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt

[PATCH v3 07/12] devicetree: Add bindings for the ATH79 PLL controllers

Signed-off-by: Alban Bedel --- v2: * Fixed the node names to respect ePAPR * Fixed the missing 's' in 'fallbacks' and the 'clocks' property v3: * Fix the compatible string for qca9550 --- .../devicetree/bindings/clock/qca,ath79-pll.txt| 33

[PATCH v3 08/12] MIPS: ath79: Add OF support to the clocks

Allow using the SoC clocks in the device tree. --- v3: * Fix the compatible string for qca9550 --- arch/mips/ath79/clock.c | 63 ++--- 1 file changed, 44 insertions(+), 19 deletions(-) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index

[PATCH v3 10/12] MIPS: ath79: Add OF support to the GPIO driver

Replace the simple GPIO chip registration by a platform driver and make ath79_gpio_init() just register the device. Signed-off-by: Alban Bedel --- v2: * Added an 'ngpios' property instead of the many matches * Use a platform data struct to store the device config on non-DT

[PATCH v3 06/12] MIPS: ath79: Add OF support to the IRQ controllers

Add OF support for the CPU and MISC interrupt controllers of most supported ATH79 devices. Signed-off-by: Alban Bedel --- arch/mips/ath79/irq.c | 87 ++- 1 file changed, 86 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/irq.c b/arch

[PATCH v3 09/12] devicetree: Add bindings for the ATH79 GPIO controllers

These bindings support the GPIO controllers found on the Qualcomm Atheros AR7xxx/AR9XXX SoC. Signed-off-by: Alban Bedel --- v2: * Add the ngpios property to have fewer fallbacks and simpler code v3: * Fix missing 's' typo * Fix the example to be valid with the binding --- .../

[PATCH v3 11/12] of: Add vendor prefix for TP-Link Technologies Co. Ltd

Signed-off-by: Alban Bedel --- v3: * Put the new entry at the right place --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt

[PATCH v3 12/12] MIPS: Add basic support for the TL-WR1043ND version 1

Add a DTS for TL-WR1043ND version 1 and allow to have it built in the kernel to circumvent the broken u-boot found on these boards. Currently only the UART, LEDs and buttons are supported. Signed-off-by: Alban Bedel --- v2: * Rebased for the new vendor directory structure * Merged the 2

[PATCH 0/4] spi: spi-ath79: Devicetree support and misc fixes

platform is moved to the generic clock framework. Finally the last patch is to ensure that CS_HIGH chips using CS0 get the proper CS level before the first transfer. Alban Alban Bedel (4): devicetree: add binding documentation for the AR7100 SPI controller spi: spi-ath79: Add device tree support

[PATCH 4/4] spi: spi-ath79: Set the initial state of CS0

The internal chip select CS0 wasn't initialized properly to work with CS HIGH chips. Signed-off-by: Alban Bedel --- drivers/spi/spi-ath79.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c index b37bedd..bf1f9b3 100644 --- a/dr

[PATCH 3/4] spi: spi-ath79: Use clk_prepare_enable and clk_disable_unprepare

Clocks should be prepared and unprepared, fix this by using clk_prepare_enable() and clk_disable_unprepare() instead of clk_enable() and clk_disable(). Signed-off-by: Alban Bedel --- drivers/spi/spi-ath79.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi

[PATCH 2/4] spi: spi-ath79: Add device tree support

Set the OF node of the spi controller and use the generic GPIO based chip select instead of the custom controller data. As the controller data isn't used by any board just drop it. Signed-off-by: Alban Bedel --- .../mips/include/asm/mach-ath79/ath79_spi_platform.h | 4 drivers/sp

[PATCH 1/4] devicetree: add binding documentation for the AR7100 SPI controller

Signed-off-by: Alban Bedel --- .../devicetree/bindings/spi/spi-ath79.txt | 24 ++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-ath79.txt diff --git a/Documentation/devicetree/bindings/spi/spi-ath79.txt b

[PATH] MIPS: ath79: Various small fix to prepare OF support

This first small serie allow using ZBOOT, fix a few errors in the registers definitions and rework the DDR controller interface. The DDR controller interface patch is mostly to simplify the IRQ controller code before adding OF support. Following this will a be serie that add the OF bindings and co

[PATCH 1/5] MIPS: ath79: Enable ZBOOT support

ZBOOT is working fine, so allow using it. Signed-off-by: Alban Bedel --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a326c4c..cc7f262 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -128,6 +128,7 @@ config ATH79

[PATCH 4/5] MIPS: ath79: Fix the PCI memory size and offset of window 7

: Alban Bedel --- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index aa3800c..e2669a8 100644 --- a/arch/mips/include/asm/mach

[PATCH 3/5] MIPS: ath79: Correctly name the defines for the PLL_FB register

This register is named PLL_FB and is not a divider but a multiplier. To make things less confusing rename the AR_PLL_DIV_SHIFT and AR_PLL_DIV_MASK macros to AR_PLL_FB_SHIFT and AR_PLL_FB_MASK. Signed-off-by: Alban Bedel --- arch/mips/ath79/clock.c| 6

[PATCH 2/5] MIPS: ath79: Add a missing new line in log message

The memory setup log is missing a new line. Signed-off-by: Alban Bedel --- arch/mips/ath79/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index a73c93c..7fc8397 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips

[PATCH 5/5] MIPS: ath79: Improve the DDR controller interface

ction and simply rely on a shared global pointer. Replace this by a simple API to setup the PCI memory windows and use the write buffer flush independently of the SoC type. That remove the need for the shared global pointer, simplify the IRQ handler code. Signed-off-by: Alban Bedel --- arch

[PATH] MIPS: ath79: Add OF support and DTS for TL-WR1043ND

This series add OF bindings and code support for the interrupt controllers, clocks and GPIOs. However it was only tested on a TL-WR1043ND with an AR9132, others SoCs are untested, and a few are not supported at all. Most code changes base on the previous bug fix series: [PATH] MIPS: ath79: Various

[PATCH 01/14] devicetree: Add bindings for the SoC of the ATH79 familly

Signed-off-by: Alban Bedel --- .../devicetree/bindings/mips/ath79-soc.txt | 21 + 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ath79-soc.txt diff --git a/Documentation/devicetree/bindings/mips/ath79-soc.txt b

[PATCH 04/14] devicetree: Add bindings for the ATH79 interrupt controllers

Signed-off-by: Alban Bedel --- .../interrupt-controller/qca,ath79-cpu-intc.txt| 45 ++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt diff --git a/Documentation/devicetree/bindings

[PATCH 11/14] MIPS: ath79: Add OF support to the GPIO driver

Replace the simple GPIO chip registration by a platform driver and make ath79_gpio_init() just register the device. Signed-off-by: Alban Bedel --- arch/mips/ath79/dev-common.c | 13 arch/mips/ath79/gpio.c | 73 +--- 2 files changed, 81

[PATCH 09/14] MIPS: ath79: Add OF support to the clocks

Allow using the SoC clocks in the device tree. Signed-off-by: Alban Bedel --- arch/mips/ath79/clock.c | 63 ++--- 1 file changed, 44 insertions(+), 19 deletions(-) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index 1fcb691..682bf61

[PATCH 08/14] MIPS: ath79: Use the common clk API

Make the code simpler and open the way for device tree clocks. Signed-off-by: Alban Bedel --- arch/mips/Kconfig | 1 + arch/mips/ath79/clock.c | 29 ++--- 2 files changed, 3 insertions(+), 27 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index

[PATCH 02/14] MIPS: ath79: Add basic device tree support

Add the bare minimum to load a device tree. Signed-off-by: Alban Bedel --- arch/mips/Kconfig | 1 + arch/mips/ath79/Kconfig | 10 ++ arch/mips/ath79/machtypes.h | 1 + arch/mips/ath79/setup.c | 27 ++- 4 files changed, 38 insertions(+), 1

[PATCH 03/14] devicetree: Add bindings for the ATH79 DDR controllers

The DDR controller of the ARxxx and AR9xxx famillies provides an interface to flush the FIFO between various devices and the DDR. This is mainly used by the IRQ controller to flush the FIFO before running the interrupt handler of such devices. Signed-off-by: Alban Bedel --- .../memory

[PATCH 07/14] devicetree: Add bindings for the ATH79 PLL controllers

Signed-off-by: Alban Bedel --- .../devicetree/bindings/clock/qca,ath79-pll.txt| 33 ++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qca,ath79-pll.txt diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b

[PATCH 05/14] devicetree: Add bindings for the ATH79 MISC interrupt controllers

Signed-off-by: Alban Bedel --- .../interrupt-controller/qca,ath79-misc-intc.txt | 30 ++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt diff --git a/Documentation/devicetree/bindings

[PATCH 10/14] devicetree: Add bindings for the ATH79 GPIO controllers

These bindings support the GPIO controllers found on the Qualcomm Atheros AR7xxx/AR9XXX SoC. Signed-off-by: Alban Bedel --- .../devicetree/bindings/gpio/gpio-ath79.txt| 40 ++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio

[PATCH 06/14] MIPS: ath79: Add OF support to the IRQ controllers

Add OF support for the CPU and MISC interrupt controllers of most supported ATH79 devices. Signed-off-by: Alban Bedel --- arch/mips/ath79/irq.c | 87 ++- 1 file changed, 86 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/irq.c b/arch

[PATCH 12/14] MIPS: Add a basic dtsi for the AR9132

A basic dtsi for the AR9132 with support for the DDR controller, CPU and MISC interrupt controller, GPIO controller, the UART and the watchdog. Signed-off-by: Alban Bedel --- arch/mips/boot/dts/ar9132.dtsi | 119 + 1 file changed, 119 insertions

[PATCH 14/14] MIPS: Add basic support for the TL-WR1043ND version 1

Add a DTS for TL-WR1043ND version 1 and allow to have it built in the kernel to circumvent the broken u-boot found on these boards. Currently only the UART, LEDs and buttons are supported. Signed-off-by: Alban Bedel --- arch/mips/ath79/Kconfig | 5 ++ arch/mips/boot/dts

[PATCH 13/14] of: Add vendor prefix for TP-Link Technologies Co. Ltd

Signed-off-by: Alban Bedel --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b13aa55..9e965b6 100644 --- a

[PATCH v2 0/5] MIPS: ath79: Various small fix to prepare OF support

First re-run of this serie of misc fix and preparation for OF support on ATH79. * Dropped the bad PCI patch * Moved the patch to use the common clk API out of the OF support serie into this one. Alban Bedel (5): MIPS: ath79: Enable ZBOOT support MIPS: ath79: Add a missing new line in

[PATCH v2 1/5] MIPS: ath79: Enable ZBOOT support

ZBOOT is working fine, so allow using it. Signed-off-by: Alban Bedel --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f501665..9075147 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -131,6 +131,7 @@ config ATH79

[PATCH v2 5/5] MIPS: ath79: Use the common clk API

Make the code simpler and open the way for device tree clocks. Signed-off-by: Alban Bedel --- arch/mips/Kconfig | 1 + arch/mips/ath79/clock.c | 29 ++--- 2 files changed, 3 insertions(+), 27 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index

[PATCH v2 3/5] MIPS: ath79: Correctly name the defines for the PLL_FB register

This register is named PLL_FB and is not a divider but a multiplier. To make things less confusing rename the AR_PLL_DIV_SHIFT and AR_PLL_DIV_MASK macros to AR_PLL_FB_SHIFT and AR_PLL_FB_MASK. Signed-off-by: Alban Bedel --- arch/mips/ath79/clock.c| 6

[PATCH v2 4/5] MIPS: ath79: Improve the DDR controller interface

ction and simply rely on a shared global pointer. Replace this by a simple API to setup the PCI memory windows and use the write buffer flush independently of the SoC type. That remove the need for the shared global pointer, simplify the IRQ handler code. Signed-off-by: Alban Bedel --- v2: * Up

[PATCH v2 2/5] MIPS: ath79: Add a missing new line in log message

The memory setup log is missing a new line. Signed-off-by: Alban Bedel --- arch/mips/ath79/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index a73c93c..7fc8397 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips

[PATCH v2 00/12] MIPS: ath79: Add OF support and DTS for TL-WR1043ND

overkill. * Moved the patch to use the common clk API to the bug fix serie to keep this one cleaner. Alban Bedel (12): devicetree: Add bindings for the SoC of the ATH79 familly MIPS: ath79: Add basic device tree support devicetree: Add bindings for the ATH79 DDR controllers devicetree

[PATCH v2 02/12] MIPS: ath79: Add basic device tree support

Add the bare minimum to load a device tree. Signed-off-by: Alban Bedel --- arch/mips/Kconfig | 1 + arch/mips/ath79/Kconfig | 10 ++ arch/mips/ath79/machtypes.h | 1 + arch/mips/ath79/setup.c | 27 ++- 4 files changed, 38 insertions(+), 1

[PATCH v2 04/12] devicetree: Add bindings for the ATH79 interrupt controllers

Signed-off-by: Alban Bedel --- v2: * Fixed the node names to respect ePAPR * Removed the unneeded @0 on the node name --- .../interrupt-controller/qca,ath79-cpu-intc.txt| 44 ++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings

[PATCH v2 01/12] devicetree: Add bindings for the SoC of the ATH79 familly

Signed-off-by: Alban Bedel --- .../devicetree/bindings/mips/ath79-soc.txt | 21 + 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ath79-soc.txt diff --git a/Documentation/devicetree/bindings/mips/ath79-soc.txt b

[PATCH v2 03/12] devicetree: Add bindings for the ATH79 DDR controllers

The DDR controller of the ARxxx and AR9xxx famillies provides an interface to flush the FIFO between various devices and the DDR. This is mainly used by the IRQ controller to flush the FIFO before running the interrupt handler of such devices. Signed-off-by: Alban Bedel --- v2: * Fix the node

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