> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
>
> Switching the clock frequently will affect the data transmission efficiency,
> and
> prolong the timeout to reduce autosuspend times for lpi2c.
>
> Acked-by: Fugang Duan
> Signed-off-by: Clark Wang
Reviewed-by: Dong Aisheng
R
> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
>
> Add bus recovery feature for LPI2C.
> Need add gpio pinctrl, scl-gpios and sda-gpios configuration in dts.
>
Pls also update dt-binding first
> Signed-off-by: Clark Wang
> ---
> drivers/i2c/busses/i2c-imx-lpi2c.c | 83 +
> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
>
> The clkhi and clklo ratio was not very precise before that can make the time
> of
> START/STOP/HIGH LEVEL out of specification.
>
> Therefore, the calculation of these times has been modified in this patch.
> At the same time, the
> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
>
> Claim clkhi and clklo as integer type to avoid possible calculation errors
> caused
> by data overflow.
>
> Reviewed-by: Fugang Duan
> Signed-off-by: Clark Wang
Reviewed-by: Dong Aisheng
Regards
Aisheng
> ---
> drivers/i2c/
> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
>
> Add eDMA receive and send mode support.
> Support to read and write data larger than 256 bytes in one frame.
>
> Signed-off-by: Clark Wang
> Reviewed-by: Li Jun
> ---
> drivers/i2c/busses/i2c-imx-lpi2c.c | 291 ++
> > > +
> > > + lpi2c_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
> > > + if (IS_ERR(lpi2c_imx->clk_ipg)) {
> > > + dev_err(&pdev->dev, "can't get I2C ipg clock\n");
> > > + return PTR_ERR(lpi2c_imx->clk_ipg);
> > > }
> >
> > Will this break exist dts?
>
> It will not break t
> > > @@ -665,6 +659,14 @@ static int __maybe_unused
> > > lpi2c_runtime_resume(struct device *dev)
> > > dev_err(dev, "can't enable I2C ipg clock, ret=%d\n", ret);
> > > }
> > >
> > > + ret = devm_request_irq(dev, lpi2c_imx->irq, lpi2c_imx_isr,
> >
> > I guess unnecessary to use devm i
[...]
> > > > pm_runtime_set_autosuspend_delay(&pdev->dev,
> > > I2C_PM_TIMEOUT);
> > > > pm_runtime_use_autosuspend(&pdev->dev);
> > > > - pm_runtime_get_noresume(&pdev->dev);
> > > > - pm_runtime_set_active(&pdev->dev);
> > > > pm_runtime_enable(&pdev->dev);
>
> From: Chanwoo Choi
> Sent: Tuesday, March 23, 2021 12:11 PM
>
> Hi,
>
> On 3/23/21 12:25 PM, Dong Aisheng wrote:
> > Hi Chanwoo,
> >
> > On Tue, Mar 23, 2021 at 11:13 AM Dong Aisheng
> wrote:
> >>
> >> A few small fixes and improvements
> >>
> >> ChangeLog:
> >> v1->v2:
> >> * squash a few p
Hi Rob,
> From: Peng Fan (OSS)
> Sent: Thursday, February 25, 2021 11:10 AM
>
> From: Peng Fan
>
> Add clock bindings for fsl-imx-esdhc yaml
>
> Signed-off-by: Peng Fan
> ---
> .../devicetree/bindings/mmc/fsl-imx-esdhc.yaml| 11 +++
> 1 file changed, 11 insertions(+)
>
> di
Hi Greg,
> From: Greg Kroah-Hartman
> Sent: Monday, November 9, 2020 8:48 PM
>
> On Mon, Nov 09, 2020 at 12:26:55PM +0000, Aisheng Dong wrote:
> > > From: Greg Kroah-Hartman
> > > Sent: Monday, November 9, 2020 8:05 PM
> > >
> > > On Mon, Nov
> From: Greg Kroah-Hartman
> Sent: Wednesday, November 18, 2020 6:46 PM
>
> On Wed, Nov 18, 2020 at 10:23:42AM +0000, Aisheng Dong wrote:
> > Hi Greg,
> >
> > > From: Greg Kroah-Hartman
> > > Sent: Monday, November 9, 2020 8:48 PM
> > >
>
> From: Saravana Kannan
> Sent: Thursday, November 19, 2020 6:22 AM
>
> On Wed, Nov 18, 2020 at 7:40 AM Aisheng Dong
> wrote:
> >
> > > From: Greg Kroah-Hartman
> > > Sent: Wednesday, November 18, 2020 6:46 PM
> > >
> > > On Wed, Nov 18,
> From: Greg Kroah-Hartman
> Sent: Thursday, November 19, 2020 9:10 PM
>
> On Thu, Nov 19, 2020 at 04:13:34AM +0000, Aisheng Dong wrote:
> > > Long story short, either
> > >
> > > * Don't care about the power domain in your clock driver.
> > >
> From: Greg Kroah-Hartman
> Sent: Thursday, November 19, 2020 10:26 PM
>
> On Thu, Nov 19, 2020 at 02:09:42PM +0000, Aisheng Dong wrote:
> > > From: Greg Kroah-Hartman
> > > Sent: Thursday, November 19, 2020 9:10 PM
> > >
> > > On Thu, Nov
> From: Rafael J. Wysocki
> Sent: Thursday, November 19, 2020 8:12 PM
>
> On Thu, Nov 19, 2020 at 12:18 PM Dong Aisheng
> wrote:
> >
> > It's possible that the same device link may be added by parsing the
> > function dependecy in DT. e.g. clock/gpio/regulators.
> > Simply go out for this case.
> From: Mirela Rabulea (OSS)
> Sent: Thursday, March 11, 2021 8:29 AM
>
> Add jpeg decoder/encoder nodes, for now on imx8qxp only.
> The same should work on imx8qm, but it was not tested.
>
> Signed-off-by: Mirela Rabulea
Please rebase to latest shawn/for-next branch and add
the necessary cloc
> From: Rob Herring
> Sent: Friday, March 5, 2021 10:14 PM
>
> On Fri, Mar 5, 2021 at 8:09 AM Aisheng Dong
> wrote:
> >
> > Hi Rob,
> >
> > > From: Peng Fan (OSS)
> > > Sent: Thursday, February 25, 2021 11:10 AM
> > >
> > >
> From: Randy Dunlap
> Sent: Saturday, January 16, 2021 11:33 AM
> Subject: [PATCH] imx: select SOC_BUS to fix firmware build
Patch title probably is better to be:
firmware: imx: x
Otherwise:
Reviewed-by: Dong Aisheng
Regards
Aisheng
>
> Fix build error in firmware/imx/ selecting SOC_BUS
> From: Jonathan Neuschäfer [mailto:j.neuschae...@gmx.net]
>
> There are a few differences between the i.MX50 clock tree and those of
> i.MX51 and i.MX53 that are not yet handled in clk-imx51-imx53.c.
> This patch handles the following differences:
>
> - i.MX50 does not have a periph_apm clock. I
> From: Stephen Boyd [mailto:sb...@kernel.org]
>
> Quoting Eric Nelson (2019-03-11 13:48:55)
> > > On March 11, 2019, 6:35 p.m. UTC, Stephen Boyd wrote:
> > > Quoting Eric Nelson (2019-03-11 08:59:56)
> > >> + *
> > >> + * Renamed to _BROKEN to prevent inadvertent use,
> > >> + * but reserved the
> From: Peng Fan
>
> > > > > Follow other i.MX6/7 machince code to check return value of
> > > > > imx_soc_device_init and warn when fail.
> > > > >
> > > > > Also drop of_platform_default_populate, because
> > > > > "arch_initcall_sync(of_platform_default_populate_init);" could
> > > > > be used t
> From: anson.hu...@nxp.com
> Sent: Wednesday, July 17, 2019 4:40 PM
>
> Use the new helper devm_platform_ioremap_resource() which wraps the
> platform_get_resource() and devm_ioremap_resource() together, to simplify
> the code.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
Regard
> From: Manivannan Sadhasivam
> Sent: Wednesday, July 17, 2019 2:11 PM
>
> Add devicetree vendor prefix for Einfochips.
>
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Dong Aisheng
Regards
Aisheng
> From: anson.hu...@nxp.com
> Sent: Wednesday, July 17, 2019 4:53 PM
>
> Use the new helper devm_platform_ioremap_resource() which wraps the
> platform_get_resource() and devm_ioremap_resource() together, to simplify
> the code.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
Regard
> From: anson.hu...@nxp.com
> Sent: Wednesday, July 17, 2019 4:40 PM
>
> Use the new helper devm_platform_ioremap_resource() which wraps the
> platform_get_resource() and devm_ioremap_resource() together, to simplify
> the code.
>
> Signed-off-by: Anson Huang
Acked-by: Dong Aisheng
Regards
A
> From: Manivannan Sadhasivam
> Sent: Wednesday, July 17, 2019 2:11 PM
>
> Document devicetree binding of i.MX8QXP AI_ML board from Einfochips.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Dong Aisheng
Regards
Aisheng
> From: Manivannan Sadhasivam
> Sent: Wednesday, July 17, 2019 2:11 PM
>
> Add support for i.MX8QXP AI_ML board from Einfochips. This board is one of
> the Consumer Edition boards of the 96Boards family based on i.MX8QXP SoC
> from NXP/Freescale.
>
> The initial support includes following periph
> From: anson.hu...@nxp.com
> Sent: Tuesday, July 16, 2019 3:19 PM
>
> The RTC IRQ is requested before the struct rtc_device is allocated, this may
> lead to a NULL pointer dereference in IRQ handler.
>
> To fix this issue, allocating the rtc_device struct before requesting the RTC
> IRQ
> usin
> From: Daniel Baluta
> Sent: Thursday, July 4, 2019 3:04 AM
> Subject: [PATCH 1/3] firmware: imx: scu-pid: Rename mu PD range to mu_a
s/pid/pd
>
> The Messaging Unit module enables two processors within the SoC to
> communicate and coordinate by passing messages through the MU interface.
>
>
> From: Daniel Baluta
> Sent: Tuesday, July 2, 2019 11:20 PM
>
> i.MX8QXP contains Hifi4 DSP. There are four clocks associated with DSP:
> * dsp_lpcg_core_clk
> * dsp_lpcg_ipg_clk
> * dsp_lpcg_adb_aclk
> * ocram_lpcg_ipg_clk
>
> Signed-off-by: Daniel Baluta
Reviewed-by: Dong Aisheng
> From: Anson Huang
> Sent: Wednesday, July 17, 2019 9:58 PM>
> Hi, Aisheng
>
> > > From: anson.hu...@nxp.com
> > > Sent: Tuesday, July 16, 2019 3:19 PM
> > >
> > > The RTC IRQ is requested before the struct rtc_device is allocated,
> > > this may lead to a NULL pointer dereference in IRQ handle
> > > +&adma_lpuart1 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_lpuart1>;
> > > + status = "okay";
> > > +};
> > > +
> > > +/* Debug */
> > > +&adma_lpuart2 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_lpuart2>;
> > > + status = "okay";
> > > +};
> > >
> From: Daniel Baluta
> Sent: Thursday, July 4, 2019 3:04 AM
> Subject: [PATCH 2/3] firmware: imx: scu-pd: Add mu_b side PD range
>
> LSIO subsystem contains 14 MU instances.
>
> 5 MUs to communicate between AP <-> SCU
> - side-A PD range managed by AP
> - side-B PD range managed by SCU
>
>
> From: Daniel Baluta
> Sent: Thursday, July 4, 2019 3:04 AM
>
> The DSP interrupt steer gathers interrupts from the system and can be used to
> steer them to DSP.
>
> Signed-off-by: Daniel Baluta
Reviewed-by: Dong Aisheng
Regards
Aisheng
> From: anson.hu...@nxp.com
> Sent: Thursday, July 18, 2019 9:32 AM
>
> Use the new helper devm_platform_ioremap_resource() which wraps the
> platform_get_resource() and devm_ioremap_resource() together, to simplify
> the code.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
Regards
> From: Daniel Baluta
> Sent: Thursday, July 18, 2019 6:25 PM
>
> LSIO subsystem contains 14 MU instances.
>
> 5 MUs to communicate between AP <-> SCU
> - side-A PD range managed by AP
> - side-B PD range managed by SCU
>
> 9 MUs to communicate between all cores (AP/M4/DSP).
> - side-A PD
> From: Abel Vesa
> Sent: Thursday, April 30, 2020 6:11 PM
>
> On 20-04-28 08:15:51, Aisheng Dong wrote:
> > > From: Abel Vesa
> > > Sent: Monday, April 27, 2020 11:11 PM
> > >
> > > Instead of ipg_root, the parent needs to be ipg_audio_root.
>
> From: Abel Vesa
> Sent: Thursday, April 30, 2020 6:04 PM
> To: Lee Jones
> On 20-04-24 07:27:27, Lee Jones wrote:
> > On Thu, 23 Apr 2020, Aisheng Dong wrote:
> >
> > > > From: Abel Vesa
> > > > Sent: Wednesday, April 22, 2020 5:19
> From: Abel Vesa
> Sent: Monday, April 27, 2020 11:11 PM
>
> Instead of ipg_root, the parent needs to be ipg_audio_root.
>
> Signed-off-by: Abel Vesa
I have a few doubts about this patch:
1. From latest RM, it seems CCGR101 (0x4650) is a shared gate for many audio
instances.
2. If this patch
> From: Andy Duan
> Sent: Wednesday, April 29, 2020 6:04 PM
>
> Add "fsl,imx6sx-fec" compatible string for fec node, then i.MX8MP EVK ethernet
> function can work now.
>
> Signed-off-by: Fugang Duan
Reviewed-by: Dong Aisheng
Regards
Aisheng
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi
> From: Anson Huang
> Sent: Thursday, February 7, 2019 5:53 PM
[...]
>
> NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> controller, the system controller is in charge of system power, clock and
> thermal sensors etc. management, Linux kernel has to communicate with
> system
> From: Anson Huang
> Sent: Tuesday, February 19, 2019 5:01 PM
> Subject: [PATCH] dt-bindings: imx: update scu resource id headfile
>
> Update i.MX SCU resource ID table according to latest system controller
> firmware.
>
You need at least explain what changes made like
what new features added?
[...]
> > I don't like droping some ID's (e.g. IMX_SC_R_DC_0_CAPTURE0) by mark
> > them as unused or even worse give them a other meaning. IMHO the
> > scu-api should be stable since day 1 and the ID's should only be extended.
> > Marking ID's as deprecated is much better than moving them around.
> >
> > You need at least explain what changes made like what new features added?
> > What removed? Side affect if any?
>
> No new features added, looks like SCFW just remove some unused resources.
> No side-effect, as they are NOT used by anyone.
>
That seems not true.
I see some new IDs added.
> From: Anson Huang
> Sent: Tuesday, February 19, 2019 11:11 AM
> Subject: [PATCH V3 1/4] dt-bindings: fsl: scu: add general interrupt support
>
> Add scu general interrupt function support.
>
> Signed-off-by: Anson Huang
> Reviewed-by: Rob Herring
> ---
> No change since V2.
> ---
> .../devic
> From: Anson Huang
> Sent: Tuesday, February 19, 2019 11:11 AM
>
> The System Controller Firmware (SCFW) controls RTC, thermal and WDOG etc.,
> these resources' interrupt function are managed by SCU. When any IRQ
> pending, SCU will notify Linux via MU general interrupt channel #3, and Linux
> ke
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Thursday, February 14, 2019 6:27 AM>
> On Mon, Feb 11, 2019 at 03:35:40PM +, Marc Zyngier wrote:
> > On 31/01/2019 08:03, Aisheng Dong wrote:
> > > Not all 64 interrupts may be used in one group. e.g. most ir
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Thursday, February 14, 2019 6:30 AM
> On Mon, Feb 11, 2019 at 03:34:23PM +, Marc Zyngier wrote:
> > On 31/01/2019 08:03, Aisheng Dong wrote:
> > > One irqsteer channel can support up to 8 output interrupts.
>
> From: Anson Huang
> Sent: Wednesday, February 20, 2019 2:54 PM
>
> NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> controller, the system controller is in charge of system power, clock and
> thermal sensors etc. management, Linux kernel has to communicate with
> system cont
> From: Marco Felsch [mailto:m.fel...@pengutronix.de]
> Sent: Wednesday, February 20, 2019 4:17 PM
> On 19-02-20 03:38, Aisheng Dong wrote:
> > [...]
> >
> > > > I don't like droping some ID's (e.g. IMX_SC_R_DC_0_CAPTURE0) by
> > > > mark
Hi Marco,
> From: Marco Felsch [mailto:m.fel...@pengutronix.de]
> Sent: Wednesday, February 20, 2019 6:53 PM
>
> Hi Aisheng,
>
> On 19-02-20 09:49, Aisheng Dong wrote:
> > > From: Marco Felsch [mailto:m.fel...@pengutronix.de]
> > > Sent: Wednesday, Februar
One group can manage 64 interrupts by using two registers (e.g. STATUS/SET).
However, the integrated irqsteer may support only 32 interrupts which
needs only one register in a group. But the current driver assume there's
a mininum of two registers in a group which result in a wrong register map
for
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Rob Herring
Cc: Shawn Guo
Cc: devicet...@vger.kernel.org
Reviewed-by: Lucas Stach
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* fix a typo
v1->v2:
* remove one unnecessary note.
---
Not all 64 interrupts may be used in one group. e.g. most irqsteer in
imx8qxp and imx8qm subsystems supports only 32 interrupts.
And one irqsteer channel can support up to 8 output interrupts.
This patch series aims to support 32 interrupts chan and multi output
interrupts.
Tested on:
iMX8QXP MEK
Not all 64 interrupts may be used in one group. e.g. most irqsteer in
imx8qxp and imx8qm subsystems supports only 32 interrupts.
As the IP integration parameters are Channel number and interrupts number,
let's use fsl,irqs-num to represents how many interrupts supported
by this irqsteer channel.
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Lucas Stach
Cc: Shawn Guo
Reviewed-by: Lucas Stach
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* add error check for imx_irqsteer_get_hwirq_base
* use DIV_ROUND_UP
* merge 'hwirq +
> From: Lucas Stach [mailto:l.st...@pengutronix.de]
> Sent: Wednesday, February 20, 2019 8:11 PM
>
> Am Mittwoch, den 20.02.2019, 11:21 +0000 schrieb Aisheng Dong:
> > Hi Marco,
> >
> > > From: Marco Felsch [mailto:m.fel...@pengutronix.de]
> > >
> From: Marco Felsch [mailto:m.fel...@pengutronix.de]
> Sent: Wednesday, February 20, 2019 9:53 PM
>
> On 19-02-20 13:11, Lucas Stach wrote:
> > Am Mittwoch, den 20.02.2019, 11:21 +0000 schrieb Aisheng Dong:
> > > Hi Marco,
> > >
> > > > Fr
> From: Lucas Stach [mailto:l.st...@pengutronix.de]
> Sent: Friday, January 18, 2019 6:23 PM
[...]
> > > This has been discussed when upstreaming the driver. The controller
> > > may support multiple output IRQs, but only one them is actually used
> > > depending on the CHANCTRL config. There is no
Freitag, den 18.01.2019, 07:53 + schrieb Aisheng Dong:
> >>>> Not all 64 interrupts may be used in one group. e.g. most irqsteer
> >>>> in imx8qxp and imx8qm subsystems supports only 32 interrupts.
> >>>>
> >>>> As the IP integration param
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Friday, January 18, 2019 6:10 PM
[...]
> >>>
> >>> config IMX_GPCV2
> >>> - bool
> >>> + bool "i.MX GPCv2 IRQ chip"
> >>> + depends on ARCH_MXC || (COMPILE_TEST && OF)
> >>> select IRQ_DOMAIN
> >>> help
> >>> Enables the wakeup I
> From: Anders Roxell [mailto:anders.rox...@linaro.org]
> Sent: Tuesday, January 22, 2019 4:38 PM
>
> Subject: [PATCH v3] pinctrl: freescale: fix link errors
Please change to:
pinctrl: imx: fix scu link errors
> Fix link errors when PINCTRL_IMX_SCU, PINCTRL_IMX8QM or
> PINCTRL_IMXBQXP is enabled
> From: Lucas Stach [mailto:l.st...@pengutronix.de]
> Sent: Tuesday, January 22, 2019 6:59 PM
>
> Am Dienstag, den 22.01.2019, 10:39 +0000 schrieb Aisheng Dong:
> > > > > From: Lucas Stach [mailto:l.st...@pengutronix.de]
> > > Sent: Friday, January 18, 2019
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Tuesday, January 22, 2019 7:40 PM
> On Tue, 22 Jan 2019 11:04:48 +,
> Aisheng Dong wrote:
> >
> >
> >
> > > From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>
> From: Lucas Stach [mailto:l.st...@pengutronix.de]
> Sent: Tuesday, January 22, 2019 6:59 PM
> To: Aisheng Dong ; linux-kernel@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org; shawn...@kernel.org; dl-linux-imx
> ; robh...@kernel.org; devicet...@vger.kernel.org;
>
> From: Lucas Stach [mailto:l.st...@pengutronix.de]
> Sent: Tuesday, January 22, 2019 8:52 PM
> To: Aisheng Dong ; linux-kernel@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org; shawn...@kernel.org; dl-linux-imx
> ; robh...@kernel.org; devicet...@vger.kernel.org;
>
Not all 64 interrupts may be used in one group. e.g. most irqsteer in
imx8qxp and imx8qm subsystems supports only 32 interrupts.
And one irqsteer channel can support up to 8 output interrupts.
This patch series aims to support 32 interrupts chan and multi output
interrupts.
Tested on:
iMX8QXP MEK
Not all 64 interrupts may be used in one group. e.g. most irqsteer in
imx8qxp and imx8qm subsystems supports only 32 interrupts.
As the IP integration parameters are Channel number and interrupts number,
let's use fsl,num-irqs to represents how many interrupts supported
by this irqsteer channel.
One group can manage 64 interrupts by using two registers (e.g. STATUS/SET).
However, the integrated irqsteer may support only 32 interrupts which
needs only one register in a group. But the current driver assume there's
a mininum of two registers in a group which result in a wrong register map
for
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Lucas Stach
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* calculate irq_count by fsl,num-irqs instead of parsing interrupts
property from devicetree to match the input interrupts and outpu
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Rob Herring
Cc: Lucas Stach
Cc: Shawn Guo
Cc: devicet...@vger.kernel.org
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* remove one unnecessary note.
---
.../devicetree/bindings/interrupt-controller/fsl,ir
Hi Abel,
> -Original Message-
> From: Abel Vesa
> Sent: Saturday, January 12, 2019 6:05 PM
> Subject: [RESEND] arm64: defconfig: Add i.MX8MQ boot necessary configs
>
> Enable all the i.MX8MQ configs necessary to boot.
>
> Signed-off-by: Abel Vesa
Would you rebase and resend with GPCV2
> From: Daniel Baluta
> Sent: Wednesday, January 16, 2019 1:05 AM
> Subject: [PATCH] arm64: dts: imx: Fix MU4_INT number
>
> MU4_INT correct number is 180, while 179 is for MU3_INT.
>
> Signed-off-by: Daniel Baluta
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> From: Abel Vesa
> Sent: Wednesday, January 16, 2019 5:42 PM
> Subject: [PATCH v3] arm64: defconfig: Add i.MX8MQ boot necessary configs
>
> Enable all the i.MX8MQ configs necessary to boot.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Shawn Guo
> Cc: Sascha Hauer
> Cc: Fabio Estevam
> Si
Make GPCv2 config option visible, then user can select it in defconfig
for ARMv8 platforms.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Shawn Guo
Cc: Lucas Stach
Cc: Andrey Smirnov
Signed-off-by: Dong Aisheng
---
drivers/irqchip/Kconfig | 3 ++-
1 file changed, 2 insertions(+
Not all 64 interrupts may be used in one group. e.g. most irqsteer in
imx8qxp and imx8qm subsystems supports only 32 interrupts.
And one irqsteer channel can support up to 8 output interrupts.
This patch series aims to support 32 interrupts chan and multi output
interrupts.
Tested on:
iMX8QXP MEK
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Lucas Stach
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
drivers/irqchip/irq-imx-irqsteer.c | 39 +++---
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/drivers/ir
Not all 64 interrupts may be used in one group. e.g. most irqsteer in
imx8qxp and imx8qm subsystems supports only 32 interrupts.
As the IP integration parameters are Channel number and interrupts number,
let's use fsl,irqs-per-chan to represents how many interrupts supported
by this irqsteer chann
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Rob Herring
Cc: Lucas Stach
Cc: Shawn Guo
Cc: devicet...@vger.kernel.org
Signed-off-by: Dong Aisheng
---
.../devicetree/bindings/interrupt-controller/fsl,irqsteer.txt| 5 +++--
1 file changed, 3 insertio
One group can manage 64 interrupts by using two registers (e.g. STATUS/SET).
However, the integrated irqsteer may support only 32 interrupts which
needs only one register in a group. But the current driver assume there's
a mininum of two registers in a group which result in a wrong register map
for
> From: Shawn Guo [mailto:shawn...@kernel.org]
> Sent: Saturday, January 12, 2019 11:09 AM
> On Sun, Dec 23, 2018 at 01:20:34PM +, Abel Vesa wrote:
> > Since this is going to be used on more SoCs than just i.MX8MQ, make
> > the dependency here more generic.
> >
> > Signed-off-by: Abel Vesa
> >
> From: Anders Roxell [mailto:anders.rox...@linaro.org]
> Sent: Monday, January 14, 2019 7:13 PM
> Subject: [PATCH v2] pinctrl: freescale: fix link errors
>
> Fix link errors when PINCTRL_IMX_SCU, PINCTRL_IMX8QM or
> PINCTRL_IMXBQXP is enabled as a module and the dependent module is
> built-in.
>
> -Original Message-
> From: Mika Penttilä [mailto:mika.pentt...@nextfour.com]
> Sent: Tuesday, January 15, 2019 1:18 AM
>
> Hi!
>
> On 14.1.2019 18.58, Fabio Estevam wrote:
> > Hi Mika,
> >
> > On Mon, Jan 14, 2019 at 8:21 AM Mika Penttilä
> > wrote:
> >> Hello,
> >>
> >>
> >> The patch
> -Original Message-
> From: Lucas Stach [mailto:l.st...@pengutronix.de]
> Sent: Friday, January 18, 2019 4:48 PM
>
> Am Freitag, den 18.01.2019, 07:53 + schrieb Aisheng Dong:
> > Not all 64 interrupts may be used in one group. e.g. most irqsteer in
> > im
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Friday, January 18, 2019 5:39 PM
> On 18/01/2019 08:48, Lucas Stach wrote:
> > Am Freitag, den 18.01.2019, 07:53 + schrieb Aisheng Dong:
> >> Not all 64 interrupts may be used in one group. e.g. most irqsteer in
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Friday, January 18, 2019 5:13 PM
> On 18/01/2019 07:41, Aisheng Dong wrote:
> > Make GPCv2 config option visible, then user can select it in defconfig
> > for ARMv8 platforms.
> >
> > Cc: Thomas Gleixner
&
> From: Lucas Stach [mailto:l.st...@pengutronix.de]
> Sent: Friday, January 18, 2019 4:53 PM
> Am Freitag, den 18.01.2019, 07:53 + schrieb Aisheng Dong:
> > One irqsteer channel can support up to 8 output interrupts.
>
> This has been discussed when upstreaming the drive
oc for i.MX8
> SCU OCOTP driver.
>
> Cc: Rob Herring
> Cc: Mark Rutland
> Cc: Aisheng Dong
> Cc: Shawn Guo
> Cc: Ulf Hansson
> Cc: Stephen Boyd
> Cc: Anson Huang
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Peng Fan
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> From: Peng Fan
> Sent: Wednesday, May 8, 2019 10:56 AM
>
> This patch adds i.MX8 nvmem ocotp driver to access fuse via RPC to i.MX8
> system controller.
>
> Cc: Srinivas Kandagatla
> Cc: Shawn Guo
> Cc: Sascha Hauer
> Cc: Pengutronix Kernel Team
> Cc: Fabio Estevam
> Cc: NXP Linux Team
>
> From: Peng Fan
> Sent: Wednesday, May 8, 2019 10:56 AM
>
> Add i.MX8QXP ocotp node
>
> Cc: Rob Herring
> Cc: Mark Rutland
> Cc: Shawn Guo
> Cc: Sascha Hauer
> Cc: Pengutronix Kernel Team
> Cc: Fabio Estevam
> Cc: NXP Linux Team
> Cc: Aisheng Dong
> From: Anson Huang
> Sent: Thursday, April 11, 2019 2:49 PM
>
> i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller inside,
> the system controller is in charge of controlling power, clock and fuse etc..
>
> This patch adds i.MX system controller soc driver support, Linux kernel has
> From: Anson Huang
> Sent: Wednesday, May 22, 2019 2:24 PM
>
> Add i.MX SCU SoC info driver to support i.MX8QXP SoC, introduce driver
> dependency into Kconfig as CONFIG_IMX_SCU must be selected to support
> i.MX SCU SoC driver, also need to use platform driver model to make sure
> IMX_SCU driver
> From: Anson Huang
> Sent: Wednesday, May 22, 2019 2:24 PM
>
> This patch selects CONFIG_IMX_SCU_SOC by default to support i.MX system
> controller unit SoC info driver.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> From: Abel Vesa
> Sent: Monday, March 25, 2019 10:00 PM
>
> Add suspend/resume pm ops to the pinctrl i.MX8MQ driver.
> Make the suspend late and the resume early since some of the pins might be
> needed active very late.
> These call the pinctrl-imx generic handlers.
>
> Signed-off-by: Abel Ves
> From: Angus Ainslie (Purism) [mailto:an...@akkea.ca]
> Sent: Thursday, March 28, 2019 9:38 PM
>
> Fix a typo in the compatible string
>
> Signed-off-by: Angus Ainslie (Purism)
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff -
> From: Christina Quast [mailto:cqu...@hanoverdisplays.com]
> Sent: Wednesday, March 13, 2019 10:21 PM
>
> In the iMX7d datasheet, the PAD_CTL_DSE_X* values are different from the
> documentation.
>
> Changes since v2:
> * Changed patch title to 'dt-bindings: pinctrl: imx7d:'
>
> Signed-off-by:
> From: Daniel Baluta
> Sent: Sunday, March 31, 2019 1:08 AM
>
> lpuart nodes are part of the ADMA subsystem. See Audio DMA memory map in
> iMX8 QXP RM [1]
>
> This patch is based on the dtsi file initially submitted by Teo Hall in i.MX
> NXP
> internal tree.
>
> [1] https://www.nxp.com/docs/en
> From: Stephen Boyd [mailto:sb...@kernel.org]
> Sent: Saturday, May 4, 2019 12:01 AM
> Subject: RE: [PATCH V2] clk: imx: pllv4: add fractional-N pll support
>
> Quoting Aisheng Dong (2019-05-02 19:38:34)
> > > From: Stephen Boyd [mailto:sb...@kernel.org]
> > > Se
> From: Anson Huang
> Sent: Sunday, May 5, 2019 2:19 PM
> Subject: [PATCH 1/2] clk: imx: Add common API for masking MMDC handshake
>
> All i.MX6 SoCs need to mask unused MMDC channel's handshake for low
> power modes, this patch provides common API for masking the MMDC
> channel passed from caller
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