> -Original Message-
> From: Joakim Zhang
> Sent: Friday, November 23, 2018 4:35 PM
> To: linux-...@vger.kernel.org; m...@pengutronix.de; robh...@kernel.org
> Cc: w...@grandegger.com; mark.rutl...@arm.com; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; dl-linux-imx ; Joakim
> Z
> -Original Message-
> From: Joakim Zhang
[...]
>
> If wakeup is enabled, enter stop mode, else enter disabled mode.Self wake can
> only work on stop mode.
>
> Starting from IMX6, the flexcan stop mode control bits is SoC specific, move
> it
> out of IP driver and parse it from devicetre
This mostly looks good to me.
A few minor comments
> -Original Message-
> From: Joakim Zhang
> Sent: Wednesday, November 21, 2018 8:32 PM
> To: linux-...@vger.kernel.org; m...@pengutronix.de
> Cc: w...@grandegger.com; linux-kernel@vger.kernel.org; dl-linux-imx
> ; Ais
> -Original Message-
> From: Aisheng DONG
> Sent: Wednesday, November 21, 2018 9:00 PM
> To: Joakim Zhang ; linux-...@vger.kernel.org;
> m...@pengutronix.de
> Cc: w...@grandegger.com; linux-kernel@vger.kernel.org; dl-linux-imx
>
> Subject: RE: [PATCH V4 1/1] can:
[...]
> +
> +static int __maybe_unused flexcan_noirq_suspend(struct device *device)
> +{
> + struct net_device *dev = dev_get_drvdata(device);
> + struct flexcan_priv *priv = netdev_priv(dev);
> +
> + if (netif_running(dev) && device_may_wakeup(device))
> + flexcan_enable_w
[...]
> >> @@
> >> -1437,10 +1552,18 @@ static int __maybe_unused flexcan_suspend(struct
> >> device *device)
> >>int err = 0;
> >>
> >>if (netif_running(dev)) {
> >> - err = flexcan_chip_disable(priv);
> >> - if (err)
> >> - return err;
> >> - er
> diff --git a/Documentation/devicetree/bindings/rtc/rtc-imx-sc.txt
> b/Documentation/devicetree/bindings/rtc/rtc-imx-sc.txt
> new file mode 100644
> index 000..d6e2353
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/rtc-imx-sc.txt
This should belong to scu binding doc.
Regards
[...]
> Subject: [PATCH V3 4/4] ARM64: dts: imx: add i.MX8QXP system controller RTC
> support
>
> Add i.MX8QXP system controller RTC support.
>
> Signed-off-by: Anson Huang
> ---
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm6
> -Original Message-
> From: Anson Huang
> Sent: Wednesday, November 28, 2018 5:57 PM
[...]
> Subject: [PATCH V3 2/4] rtc: add i.MX system controller RTC support
>
> i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller inside,
> the system controller is in charge of controlling
> -Original Message-
> From: Stephen Boyd [mailto:sb...@kernel.org]
[...]
> >
> > Changes since v12:
> > * replaced the division in clk_pll_recalc_rate in clk-frac
> >with do_div as suggested by Stephen
> >
> > Abel Vesa (2):
> > clk: imx: Add imx composite clock
> > clk: imx: Add
> -Original Message-
> From: Stephen Boyd [mailto:sb...@kernel.org]
> Sent: Tuesday, December 4, 2018 3:32 AM
> To: Aisheng DONG ; linux-...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> mturque...@baylibre.com; shawn...@kerne
> -Original Message-
> From: Abel Vesa
> Sent: Thursday, December 13, 2018 9:18 PM
> Subject: [PATCH 2/3] clk: imx: Build imx8mq clocks on arm64 only
>
> The composite-8m, frac and sccg clocks are not used by any arm32 IMX SoC,
> therefore build them only on arm64. CONFIG_ARCH_MXC is arm64
[...]
> > --- a/drivers/clk/imx/Makefile
> > +++ b/drivers/clk/imx/Makefile
> > @@ -34,5 +34,6 @@ obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
> > obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
> > obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
> > obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o
> > -obj-$(CONFIG_SO
[...]
> >
> > I applied it on my test branch and this makes sparc64-allyesconfig
> > fail
> > with:
> >
> >drivers/rtc/rtc-imx-sc.o: In function `imx_sc_rtc_read_time':
> >rtc-imx-sc.c:(.text+0x34): undefined reference to `imx_scu_call_rpc'
> >drivers/rtc/rtc-imx-sc.o: In function `imx_
> -Original Message-
> From: Anson Huang
> Sent: Thursday, November 29, 2018 9:50 AM
[...]
> i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller inside,
> the system controller is in charge of controlling power, clock and secure rtc
> etc..
>
> This patch adds i.MX system cont
x.de; Leonard Crestez ; Aisheng
> Dong ; Richard Zhu ; Rob
> Herring ; devicet...@vger.kernel.org; dl-linux-imx
> ; linux-arm-ker...@lists.infradead.org
> Subject: [PATCH v3 3/3] reset: imx7: Add support for i.MX8MQ IP block variant
>
> Add bits and pieces needed to support IP block v
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Friday, December 21, 2018 4:23 AM
>
> On Thu, Dec 13, 2018 at 07:07:57AM +, Joakim Zhang wrote:
> > From: Dong Aisheng
> >
> > The FlexCAN controller can parse clock source property from DTS file
> > to select P
> -Original Message-
> From: Abel Vesa
> Sent: Sunday, December 23, 2018 3:09 PM
>
> The CONFIG_SOC_IMX8MQ will go away, so the dependency can be based on
> ARCH_MXC && ARM64.
>
> Signed-off-by: Abel Vesa
Acked-by: Dong Aisheng
Regards
Dong Aisheng
> -Original Message-
> From: Abel Vesa
> Sent: Sunday, December 23, 2018 3:04 PM
> To: Kishon Vijay Abraham I ; Jun Li ; Lucas
> Stach
> Cc: dl-linux-imx ; Linux Kernel Mailing List
> ; Abel Vesa
> Subject: [PATCH] phy: freescale: Break dependency on SOC_IMX8MQ for USB
> PHY
>
> Since th
> -Original Message-
> From: Abel Vesa
> Sent: Sunday, December 23, 2018 3:00 PM
> To: Shawn Guo ; Sascha Hauer
> ; Fabio Estevam
> Cc: dl-linux-imx ; linux-arm-ker...@lists.infradead.org;
> Linux Kernel Mailing List ; Abel Vesa
>
> Subject: [PATCH] soc: imx: Break dependency on SOC_IMX8M
> -Original Message-
> From: Ulf Hansson [mailto:ulf.hans...@linaro.org]
> Sent: Wednesday, January 2, 2019 6:49 PM
>
> On Sat, 29 Dec 2018 at 07:43, Aisheng Dong wrote:
> >
> > > From: Ulf Hansson [mailto:ulf.hans...@linaro.org]
> > > S
> From: Abel Vesa
> Sent: Friday, January 4, 2019 12:58 AM
> Subject: [PATCH] clk: imx: Remove Kconfig duplicate include
>
> Commit d360b130e210f2 ("clk: imx: Make the i.MX8MQ CCM clock driver
> CLK_IMX8MQ dependant") introduced this dupplicate (and wrongfuly
> ordered).
>
> Fixes: d360b130e210f2
> From: Ulf Hansson [mailto:ulf.hans...@linaro.org]
> Sent: Friday, January 4, 2019 5:11 AM
> On Wed, 2 Jan 2019 at 17:29, Aisheng Dong wrote:
> >
> > > -Original Message-
> > > From: Ulf Hansson [mailto:ulf.hans...@linaro.org]
> > > Sent: Wednesd
> -Original Message-
> From: Gustavo A. R. Silva [mailto:gust...@embeddedor.com]
> Sent: Monday, December 24, 2018 2:40 PM
>
> One of the more common cases of allocation size calculations is finding the
> size of a structure that has a zero-sized array at the end, along with memory
> for s
Currently attach_dev() in power domain infrastructure still does
not support multi domains case as the struct device *dev passed
down from genpd_dev_pm_attach_by_id() is a virtual PD device, it
does not help for parsing the real device information from device
tree, e.g. Device/Power IDs, Clocks and
> From: Ulf Hansson [mailto:ulf.hans...@linaro.org]
> Sent: Friday, December 28, 2018 11:37 PM
>
> On Thu, 27 Dec 2018 at 18:14, Aisheng Dong
> wrote:
> >
> > Currently attach_dev() in power domain infrastructure still does not
> > support multi domains case as t
> From: Anson Huang
> Sent: Wednesday, April 17, 2019 10:00 AM
>
> The way of getting private imx_i2c_struct in i2c_imx_clk_notifier_call() is
> incorrect, should use clk_change_nb element to get correct address and avoid
> below kernel dump during POST_RATE_CHANGE notify by clk
> framework:
>
>
[...]
> >
> > Fixes: 90ad2cbe88c2("i2c: imx: use clk notifier for rate changes")
> > Signed-off-by: Anson Huang
>
> Please also provide how to reproduce it.
> And it seems not a new issue, should we CC stable?
Besides above comments:
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
>
> Regar
> From: Anson Huang
> Sent: Tuesday, April 16, 2019 11:22 AM
>
> NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> controller, the system controller is in charge of system power, clock and
> thermal sensors etc. management, Linux kernel has to communicate with
> system controll
> From: Anson Huang
> Sent: Tuesday, April 16, 2019 11:22 AM
>
> i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller inside,
> the system controller is in charge of controlling power, clock and thermal
> sensors etc..
>
> This patch adds i.MX system controller thermal driver support,
+Jacky and Leonard, Ranjani
Hi Alexandre,
> From: Alexandre Bailon [mailto:abai...@baylibre.com]
>
> This series implements busfreq, a framework used in MXP's tree to scale the
> interconnect and dram frequencies.
> In the vendor tree, device's driver request for a performance level, which is
>
> From: Peng Fan
>
> "arch_initcall_sync(of_platform_default_populate_init);" could be used to
> populate the device tree, there is no need to call
> of_platform_default_populate
> in machine code.
>
> Tested on i.MX6Q-SDB i.MX6SL-EVK i.MX6UL-EVK board.
>
> Signed-off-by: Peng Fan
> ---
> arc
> From: Peng Fan
>
> [PATCH 2/2] ARM: imx: mach-imx7ulp: warn when imx_soc_device_init fail
ARM: imx: imx7ulp: ...
> Follow other i.MX6/7 machince code to check return value of
> imx_soc_device_init and warn when fail.
>
> Also drop of_platform_default_populate, because
> "arch_initcall_sync(of_
> From: Peng Fan
>
> Add lsio_mu2 node which could be used communicate with SCU.
>
> Signed-off-by: Peng Fan
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> ---
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dt
> From: Peng Fan
>
> Subject: [PATCH] arm64: dts: imx8qxp: fix mbox-cells
>
> Currently lsio_mu1 is used by Linux Kernel with mbox-cells as 2, but actually
> mu0-4 could be used to communicate with SCU. So fix the mbox-cells.
>
> Signed-off-by: Peng Fan
Reviewed-by: Dong Aisheng
Regards
Dong
> From: Anson Huang
>
> Add scu general interrupt function support.
>
> Signed-off-by: Anson Huang
> Reviewed-by: Rob Herring
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> From: Anson Huang
>
> The System Controller Firmware (SCFW) controls RTC, thermal and WDOG etc.,
> these resources' interrupt function are managed by SCU. When any IRQ
> pending, SCU will notify Linux via MU general interrupt channel #3, and Linux
> kernel needs to call SCU APIs to get IRQ statu
> From: Anson Huang
>
> On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify user for
> IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox RX doorbell mode is
> used for this function, this patch adds support for it.
>
> Signed-off-by: Anson Huang
> ---
> Changes since V3:
>
> From: Stephen Boyd [mailto:sb...@kernel.org]
>
> Quoting Patrick Wildt (2019-03-12 00:36:54)
> > On Fri, Mar 08, 2019 at 07:29:05AM -0800, Stephen Boyd wrote:
> > > It's mostly about making sure that any existing dtbs don't have
> > > their numbers shifted around. So hopefully any overlapping
>
[...]
> > Originally devices are registered in arch_initcall. Now it will be a
> > bit later in arch_initcall_sync and this may cause a bit risk if the
> > code under the default_populate want to access the device service provided
> by early probe.
> >
> > Probably it's more safe to leave as it is
[...]
> > > Follow other i.MX6/7 machince code to check return value of
> > > imx_soc_device_init and warn when fail.
> > >
> > > Also drop of_platform_default_populate, because
> > > "arch_initcall_sync(of_platform_default_populate_init);" could be
> > > used to populate the device tree.
> > >
>
> From: Daniel Baluta
> Sent: Tuesday, March 26, 2019 5:43 PM
>
> i.MX8QXP contains a total of 4 EDMA controllers of which two are primarily
> for audio components and the other two are for non-audio periperhals.
>
> This patch adds the EDMA0/EDMA1 nodes used by audio peripherals.
>
> EDMA0 cont
> From: Daniel Baluta
> Sent: Thursday, March 28, 2019 3:03 AM
>
> i.MX8QXP contains a total of 4 EDMA controllers of which two are primarily
> for audio components and the other two are for non-audio periperhals.
>
> This patch adds the EDMA0/EDMA1 nodes used by audio peripherals.
>
> EDMA0 con
> From: Igor Plyatov [mailto:plya...@gmail.com]
>
> Dear developers,
>
> please, help to resolve two issues with SPI DMA transfers at i.MX6Q platform.
>
> First issue is
> [ 4465.008003] spi_master spi0: I/O Error in DMA RX
>
> Second issue is duplication for one of received bytes.
>
Copy X
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Monday, March 25, 2019 11:30 PM
>
> From: Laurentiu Tudor
>
> If the dma controller is not yet probed, defer i2c probe.
> The error path in probe was slightly modified (no functional change) to avoid
> triggering this WARN_
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > index 0cb939861a60..84c7c3eca1a1 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > @@ -182,6 +182,78 @@
> >
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Thursday, March 28, 2019 2:13 AM
> On 27/03/2019 17:00, Leonard Crestez wrote:
> > On Wed, 2019-03-27 at 17:06 +0100, Lucas Stach wrote:
> >> Am Mittwoch, den 27.03.2019, 15:57 + schrieb Marc Zyngier:
> >>> On 27/03/2019 15:44, Lucas St
[...]
> > > Anything that isn't visible to the GPC and requires the GIC
> > > wake_request signal to behave as specified is broken by this erratum.
> >
> > I really wonder how a timer interrupt (a PPI, hence not routed through
> > the GPC) can wake up the CPU in this case. It really feels like
> >
[...]
> > * All SPIs are connected to GPC in a 1:1 mapping
> > * This series deals with SGIs
> > * The timer PPIs are not required; covered by local-timer-stop
> > * LPIs are currently unused (I understand imx-pci uses SPI by default
> > from Lucas)
> >
> > Anything missing?
> >
> > My understandi
> From: Anson Huang
> Sent: Monday, March 18, 2019 11:10 AM
>
> The System Controller Firmware (SCFW) controls RTC, thermal and WDOG etc.,
> these resources' interrupt function are managed by SCU. When any IRQ
> pending, SCU will notify Linux via MU general interrupt channel #3, and Linux
> kernel
> From: Anson Huang
> Sent: Monday, March 18, 2019 11:10 AM
>
> Add i.MX system controller RTC alarm support, the RTC alarm is implemented
> via SIP(silicon provider) runtime service call and ARM-Trusted-Firmware will
> communicate with system controller via MU(message unit) IPC to set RTC
> alarm
> From: Abel Vesa
> Sent: Monday, April 8, 2019 6:43 PM
> Subject: [PATCH v2] pinctrl: pinctrl-imx8mq: Add suspend/resume ops
pinctrl: imx8mq:
> To support pinctl hog restore after LPSR resume back, add the generic
> suspend/resume in pinctrl-imx along with the generic pm opsto be used by
>
> From: Linus Walleij [mailto:linus.wall...@linaro.org]
> Sent: Monday, April 8, 2019 8:10 PM
> On Wed, Apr 3, 2019 at 10:43 AM Shawn Guo wrote:
>
> > I assume this will go via your tree. Let me know if you think
> > differently.
>
> OK I applied it, if you're not merging any device trees using
[...]
> so I will add another API in imx-scu-irq
> driver to provide function of enabling/disabling irq, each driver can just
> call the
> API to enable/disable its own IRQ, ONLY need to pass the corresponding
> arguments:
>
That's exactly what I mean.
> >
> > > + msg.group = SC_IRQ_GROUP_RTC;
> From: Anson Huang
> Sent: Tuesday, April 9, 2019 10:43 AM
> Subject: [PATCH V6 2/4] firmware: imx: enable imx scu general irq function
>
> The System Controller Firmware (SCFW) controls RTC, thermal and WDOG etc.,
> these resources' interrupt function are managed by SCU. When any IRQ
> pending,
> From: Anson Huang
> Sent: Tuesday, April 9, 2019 10:44 AM
> Subject: [PATCH V6 4/4] rtc: imx-sc: add rtc alarm support
>
> Add i.MX system controller RTC alarm support, the RTC alarm is implemented
> via SIP(silicon provider) runtime service call and ARM-Trusted-Firmware will
> communicate with
> From: Abel Vesa
> Sent: Tuesday, April 9, 2019 2:39 AM
>
> To support pinctl hog restore after LPSR resume back, add the generic
> suspend/resume in pinctrl-imx along with the generic pm ops to be used by
> platform specific drivers. Then make use of the newly added ops in i.MX8MQ
> platform spe
[...]
> > > +static int imx_sc_rtc_alarm_irq_enable(struct device *dev, unsigned
> > > +int
> > > +enable) {
> > > + imx_scu_irq_enable(SC_IRQ_GROUP_RTC, SC_IRQ_RTC, enable);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int imx_sc_rtc_read_alarm(struct device *dev, struct
> > > +rtc_wk
> From: Abel Vesa
> Sent: Tuesday, April 9, 2019 2:53 AM
>
> i.MX8MQ needs it for RTC support.
>
> Signed-off-by: Abel Vesa
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> From: Stephen Boyd [mailto:sb...@kernel.org]
> Sent: Tuesday, February 26, 2019 1:23 AM>
> Quoting Abel Vesa (2019-02-23 02:58:14)
> > On 19-02-22 09:46:23, Stephen Boyd wrote:
> > > Quoting Abel Vesa (2019-02-22 09:07:32)
> > > > Make the entire combination of plls to be one single clock. The
>
[...]
> > > > > > Tested-by: Lucas Stach
> > > > > > Acked-by: Lucas Stach
> > > > >
> > > > > I suspect these tested by and acked tags should have been
> > > > > dropped, unless you discussed and tested off-list?
> > > > >
> > > >
> > > > Oups, I forgot to drop them.
> > >
> > > Ok. Can Lucas r
> From: Guenter Roeck [mailto:groe...@gmail.com] On Behalf Of Guenter
> Roeck>
> On 2/22/19 11:52 AM, Rob Herring wrote:
> > On Mon, Feb 18, 2019 at 06:53:48AM +, Anson Huang wrote:
> >> Add i.MX8QXP system controller watchdog binding.
> >>
> >> Signed-off-by: Anson Huang
> >> ---
> >> Change
[...]
> > On Thu, Feb 21, 2019 at 06:38:30AM +, Anson Huang wrote:
> > > NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> > > controller, the system controller is in charge of system power,
> > > clock and thermal sensors etc. management, Linux kernel has to
> > > communica
> From: Anson Huang
> Sent: Saturday, February 23, 2019 11:20 AM
> To: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> ulf.hans...@linaro.org; Aisheng Dong ;
> devicet...@vger.kernel.
> From: Anson Huang
> Sent: Saturday, February 23, 2019 11:20 AM
>
> Add new resources as below according to latest system controller firmware for
> new features:
>
> IMX_SC_R_PERF
> IMX_SC_R_OCRAM
> IMX_SC_R_DMA_5_CH0
> IMX_SC_R_DMA_5_CH1
> IMX_SC_R_DMA_5_CH2
>
> > Subject: [PATCH V4 1/2] dt-bindings: imx: remove unused resources from
> > scu resource table
> >
> > Removes below resources which were defined during pre-silicon phase
> > and the real silicons do NOT have them, they have never been used,
> > latest system controller firmware also removed the
> From: Christina Quast [mailto:cqu...@hanoverdisplays.com]
> Sent: Saturday, February 23, 2019 1:01 AM
>
> In the iMX7d datasheet, the PAD_CTL_DSE_X* values are different from the
> documentation.
>
It's a doc problem.
Latest RM seems got updated.
As here it's a reference definition in binding
> From: Peng Fan
> Sent: Monday, June 1, 2020 11:43 AM
>
> Add i.MX8MQ/M/N/P compatible string to support i.MX8M SoCs
>
> Signed-off-by: Peng Fan
Reviewed-by: Dong Aisheng
BTW, Anson,
will you continue to help convert MU binding into json schemas?
Regards
Aisheng
> From: Peng Fan
> Sent: Monday, June 1, 2020 11:43 AM
>
> Add mu node to let A53 could communicate with M Core.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +
> arch/arm64/boot/dts/freescale
> From: Peng Fan
> Sent: Monday, June 1, 2020 4:20 PM
>
> Add mu node to let A53 could communicate with M Core.
>
> Signed-off-by: Peng Fan
Reviewed-by: Dong Aisheng
Regards
Aisheng
> From: Christophe JAILLET
> Sent: Sunday, May 31, 2020 4:50 AM
>
> 'pinctrl_unregister()' should not be called to undo
> 'devm_pinctrl_register_and_init()', it is already handled by the framework.
>
> This simplifies the error handling paths of the probe function.
> The 'imx_free_resources()' c
> From: Peng Fan
> Sent: Monday, June 1, 2020 8:40 PM
> >
> > > From: Peng Fan
> > > Sent: Friday, April 24, 2020 9:12 AM
> > > >
> > > > > From: Peng Fan
> > > > > Sent: Thursday, April 23, 2020 6:57 PM
> > > > > > > From: Peng Fan
> > > > > > > Sent: Thursday, April 23, 2020 3:00 PM
> > > > >
> From: Peng Fan
> Sent: Thursday, April 23, 2020 3:00 PM
>
> Add resource management API, when we have multiple partition running
> together, resources not owned to current partition should not be used.
>
> Reviewed-by: Leonard Crestez
> Signed-off-by: Peng Fan
> ---
> drivers/firmware/imx/M
> From: Anson Huang
> Sent: Monday, May 18, 2020 8:54 PM
>
> Interrupt is a required property according to SRC binding, add it for SRC
> node.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
Regards
Aisheng
> From: Anson Huang
> Sent: Monday, May 18, 2020 8:54 PM
> To: robh...@kernel.org; shawn...@kernel.org; s.ha...@pengutronix.de;
> ker...@pengutronix.de; feste...@gmail.com; devicet...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: dl-linux-imx
> Subjec
> From: Anson Huang
> Sent: Monday, May 18, 2020 10:53 PM
>
> Convert the i.MX7D clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
> ---
> Changes since V1:
> - Update maintainer's e-mail address.
> ---
> .../devicetree/bindings/clock/imx7d-clock.txt
> From: Anson Huang
> Sent: Monday, May 18, 2020 10:48 PM
>
> Convert the i.MX GPT binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
> ---
> .../devicetree/bindings/timer/fsl,imxgpt.txt | 45 -
> .../devicetree/bindings/timer/fsl,imxgpt.yaml | 10
> From: Anson Huang
> Sent: Monday, May 18, 2020 10:48 PM
>
> Convert the i.MX TPM binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
> ---
> .../devicetree/bindings/timer/nxp,tpm-timer.txt| 28 --
> .../devicetree/bindings/timer/nxp,tpm-timer.yaml | 63
> From: Anson Huang
> Sent: Monday, May 18, 2020 10:48 PM
>
> Convert the i.MX SYSCTR binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
Regards
Aisheng
> From: Anson Huang
> Sent: Monday, May 18, 2020 8:40 PM
>
> Node name should be generic, use "reset-controller" instead of "src" for
> i.MX6/i.MX7 SoCs src nodes.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
Regards
Aisheng
> ---
> arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
> arch
> From: Anson Huang
> Sent: Monday, May 18, 2020 6:04 PM
>
> Convert the i.MX reset binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
> ---
> Changes since V1:
> - add the compatible strings per SoC;
> - use "reset-controller" as node name instead of src;
> From: Anson Huang
> Sent: Tuesday, May 19, 2020 11:56 AM
>
> Convert the i.MX GPT binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
Regards
Aisheng
> From: Peng Fan
> Sent: Wednesday, May 20, 2020 10:03 AM
>
> Minor patchset to update device tree aliases
>
> Peng Fan (4):
> arm64: dts: imx8mq: Add mmc aliases
> arm64: dts: imx8mq: Add ethernet alias
> arm64: dts: imx8mm: sort the aliases
> arm64: dts: imx8mp: add i2c aliases
For th
> From: Peng Fan
> Sent: Wednesday, May 20, 2020 10:05 AM
>
> Add mu node to let A53 could communicate with M Core.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +
> arch/arm64/boot/dts/freesc
> From: Peng Fan
> Sent: Wednesday, May 20, 2020 10:05 AM
>
> Add mu root clk for mu mailbox usage.
>
> Signed-off-by: Peng Fan
Reviewed-by: Dong Aisheng
Regards
Aisheng
> From: Fabio Estevam
> Sent: Wednesday, May 20, 2020 11:07 AM
>
> Hi Peng,
>
> On Wed, May 20, 2020 at 12:01 AM Peng Fan wrote:
>
> > Nothing specific in i.MX8MP for the mu part, so do we really need add
> > "fsl,imx8mp-mu"?
>
> It is good practice to add a more specific option.
>
> Let's s
> From: Anson Huang
> Sent: Wednesday, May 20, 2020 2:03 PM
>
> Convert the i.MX thermal binding to DT schema format using json-schema
>
> Signed-off-by: Anson Huang
> ---
> Changes since V1:
> - move tempmon node into its parent node anatop in example;
> - improve "fsl,tempmon" des
> From: Anson Huang
> Sent: Wednesday, May 20, 2020 2:30 PM
>
> i.MX6/7 SoCs' temperature sensor is inside anatop module from HW perspective,
> so it should be a child node of anatop.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
BTW, I think you also need a binding doc for this c
> From: Anson Huang
> Sent: Wednesday, May 20, 2020 3:47 PM
>
> > Subject: RE: [PATCH] ARM: dts: imx: Make tempmon node as child of
> > anatop node
> >
> > > From: Anson Huang
> > > Sent: Wednesday, May 20, 2020 2:30 PM
> > >
> > > i.MX6/7 SoCs' temperature sensor is inside anatop module from HW
> From: Anson Huang
> Sent: Wednesday, May 20, 2020 4:12 PM
>
> > Subject: RE: [PATCH] ARM: dts: imx: Make tempmon node as child of
> > anatop node
> >
> > > From: Anson Huang
> > > Sent: Wednesday, May 20, 2020 3:47 PM
> > >
> > > > Subject: RE: [PATCH] ARM: dts: imx: Make tempmon node as child
> From: Anson Huang
> Sent: Wednesday, May 20, 2020 4:17 PM
>
> Convert the i.MX thermal binding to DT schema format using json-schema
>
> Signed-off-by: Anson Huang
> ---
> Changes since V2:
> - remove unnecessary property in compatible;
> - add detail description for interrupts;
>
> From: Robin Gong
> Sent: Thursday, May 21, 2020 10:18 PM
>
> Correct ldo1 voltage range from wrong high group(3.0v~3.3v) to low group
> (1.6v~1.9v) because the ldo1 should be 1.8v. Actually, two voltage groups have
> been supported at bd718x7-regulator driver, hence, just corrrect the voltage
>
> From: Robin Gong
> Sent: Thursday, May 21, 2020 10:18 PM
>
> Correct ldo1 voltage range from wrong high group(3.0v~3.3v) to low group
> (1.6v~1.9v) because the ldo1 should be 1.8v. Actually, two voltage groups have
> been supported at bd718x7-regulator driver, hence, just corrrect the voltage
>
Hi Ulf,
> From: Ulf Hansson
> Sent: Wednesday, March 17, 2021 5:31 PM
>
> Since the introduction of the PM domain support for the scu-pd, the genpd
> framework has been continuously improved. More preciously, using a single
> global power domain can quite easily be deployed for imx platforms.
>
> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
>
> A NACK flag in ISR means i2c bus error. In such codition, there is no need to
> do
> read/write operation. It's better to return ISR directly and then stop i2c
> transfer.
>
> Signed-off-by: Gao Pan
> Signed-off-by: Clark Wang
> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
> Subject: [PATCH 02/11] i2c: imx-lpi2c: add runtime pm support
>
> - Add runtime pm support to dynamicly manage the clock.
> - Put the suspend to suspend_noirq.
> - Call .pm_runtime_force_suspend() to force runtime pm suspended
> in
> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
>
> The lpi2c IP needs two clks: ipg clk and per clk. The old lpi2c driver missed
> ipg
> clk. This patch adds ipg clk for lpi2c driver.
>
Pleas also update dt-binding and sent along with this patchset.(before this one)
> Signed-off
> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
>
> Manage irq resource request/release in runtime pm to save irq domain's
> power.
>
> Signed-off-by: Frank Li
> Signed-off-by: Fugang Duan
> Reviewed-by: Frank Li
> ---
> drivers/i2c/busses/i2c-imx-lpi2c.c | 26 ++
> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
>
> add debug message when i2c peripheral clk rate is 0, then directly return
> -EINVAL.
>
> Signed-off-by: Gao Pan
> Reviewed-by: Andy Duan
Drop old review when patch is changed
> ---
> drivers/i2c/busses/i2c-imx-lpi2c.c | 7
> From: Clark Wang
> Sent: Wednesday, March 17, 2021 2:54 PM
>
> use subsys_initcall for i2c driver to improve i2c driver probe priority
Will this affect DMA support which will be probed much later compared with
subsys_initcall?
>
> Signed-off-by: Gao Pan
Add your sign-off
> ---
> drivers
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