From: Balasubramani Vivekanandan
In case of remote display, touch controller will be also remote.
In such cases, the reset pin of the touch controller will be
controlled through bridging ICs like Deserilizer and Serializer.
Therefore accessing the gpio pins require transactions with the
external
From: Naveen Chakka
Atmel touch controller contains T38 object where a user can store its own
data of length 64 bytes. T38 data will not be part of checksum
calculation on executing T6 BACKUP command.
format used to update the T38 data is given below:
offset: offset address of the data to b
From: Deepak Das
Currently Driver probe continues with a warning message when it fails to
get the proper multitouch object configurations like TouchScreen resolution.
But Driver probe should fail in case of above scneario because it will not
behave
as expected without the proper touchscreen conf
From: Deepak Das
Currently mxt_initialize() tries to probe bootloader mode
even if valid bootloader address is not specified.
This commit modifies mxt_initialize() to return error
if Device is not in appmode and bootloader address is
not specified.
This commit also returns error code from mxt_s
From: Deepak Das
ReportID "0x00" is reserved by Atmel and should not be used by any
Atmel touch controller.
reportID is the first byte retrieved from T5 message payload.
Currently Atmel driver continues to process the T5 messages even if
the reportID "0x00" is returned by Touch Controller.
This
From: Deepak Das
T44 object returns the count of valid T5 messages in the buffer. According
to atmel, this count should be the main criteria to read the number of T5
messages.
Following is the statement from atmel confirming the same :-
"For the readout of messages we recommend to stop after the
From: Deepak Das
mxt_update_cfg() failed to propagate the error
code from mxt_init_t7_power_cfg() so return the error code.
Signed-off-by: Deepak Das
Signed-off-by: George G. Davis
Signed-off-by: Jiada Wang
---
drivers/input/touchscreen/atmel_mxt_ts.c | 4 +++-
1 file changed, 3 insertions(+
From: Naveen Chakka
To know the current communication status of the touch controller during
runtime, sysfs interface is added
sysfs interface: /sys/class/i2c-dev/i2c-*/device/*/touch_dev_stat
Executing the above sysfs interface provides two output values
1)Status of the touch device
val
From: Sanjeev Chugh
There could be scope of race conditions when sysfs is being handled
and at the same time, device removal is occurring. For example,
we don't want the device removal to begin if the Atmel device
cfg update is going on or firmware update is going on. In such
cases, wait for devi
fix "make W=1" compilation warnings from Atmel driver
as per the compilation logs.
Signed-off-by: Jiada Wang
---
drivers/input/touchscreen/atmel_mxt_ts.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c
b/drivers/input/touchscreen/atme
On Tue, 27 Aug 2019 at 04:42, Jan Stancek wrote:
>
>
> - Original Message -
> > On Mon, 2019-08-26 at 10:38 -0400, Jan Stancek wrote:
>
> No change with that patch,
Same for me.
> but following one fixes it for me:
Works for me.
Thanks for the fix patch.
>
> diff --git a/fs/nfs/pagelis
On 26/08/19 5:38 PM, tudor.amba...@microchip.com wrote:
> From: Boris Brezillon
>
> Add the SNOR_F_HAS_LOCK flag and set it when SPI_NOR_HAS_LOCK is set
> in the flash_info entry or when it's a Micron or ST flash.
>
> Move the locking hooks in a separate struct so that we have just
> one fiel
Kbuild provides per-file compiler flag addition/removal:
CFLAGS_.o
CFLAGS_REMOVE_.o
AFLAGS_.o
AFLAGS_REMOVE_.o
CPPFLAGS_.lds
HOSTCFLAGS_.o
HOSTCXXFLAGS_.o
The is the filename of the target with its directory and
suffix stripped.
This syntax comes into a trouble when two files with
On Tue, 2019-08-27 at 08:28 +0200, Michal Hocko wrote:
> On Tue 27-08-19 15:20:46, Alastair D'Silva wrote:
> > From: Alastair D'Silva
> >
> > It is possible for firmware to allocate memory ranges outside
> > the range of physical memory that we support (MAX_PHYSMEM_BITS).
>
> Doesn't that count
kbuild test robot writes:
> tree: https://kernel.googlesource.com/pub/scm/linux/kernel/git/tip/tip.git
> x86/urgent
> head: cfa16294b1c5b320c0a0e1cac37c784b92366c87
> commit: cfa16294b1c5b320c0a0e1cac37c784b92366c87 [3/3] x86/apic: Include the
> LDR when clearing out APIC registers
> config
When I inject a PCIE Fatal error into a mellanox netdevice, 'dmesg' shows
the device is recovered successfully, but 'lspci' didn't show the
device. I checked the configuration space of the slot where the netdevice
is inserted and found out the bit 'PCI_BRIDGE_CTL_BUS_RESET' is set.
Later, I found o
On Tue, 27 Aug 2019, Bandan Das wrote:
> kbuild test robot writes:
>
> > tree:
> > https://kernel.googlesource.com/pub/scm/linux/kernel/git/tip/tip.git
> > x86/urgent
> > head: cfa16294b1c5b320c0a0e1cac37c784b92366c87
> > commit: cfa16294b1c5b320c0a0e1cac37c784b92366c87 [3/3] x86/apic: Incl
On 21.08.19 15:25, Martin Kepplinger wrote:
> Move some register definitions to the per-device array of struct
> st_lsm6dsx_sensor_settings in order to simplify adding new sensor
> devices to the driver.
>
> Also, remove completely unused register definitions.
>
> Signed-off-by: Martin Kepplinger
The type of reg_direction needs to match the type of the regmap, which is
u8.
Signed-off-by: David Jander
---
drivers/gpio/gpio-pca953x.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 378b206d2dc9..30072a
The register number needs to be translated for chips with more than 8
ports. This patch fixes a bug causing all chips with more than 8 GPIO pins
to not work correctly.
Signed-off-by: David Jander
---
drivers/gpio/gpio-pca953x.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff
Thomas Gleixner writes:
> On Tue, 27 Aug 2019, Bandan Das wrote:
>> kbuild test robot writes:
>>
>> > tree:
>> > https://kernel.googlesource.com/pub/scm/linux/kernel/git/tip/tip.git
>> > x86/urgent
>> > head: cfa16294b1c5b320c0a0e1cac37c784b92366c87
>> > commit: cfa16294b1c5b320c0a0e1cac3
On 08/27/2019 09:36 AM, Vignesh Raghavendra wrote:
>> +nor->flags = SNOR_F_HAS_LOCK;
> This is okay for now. But Perhaps its safer to do:
>
> nor->flags |= SNOR_F_HAS_LOCK;
>
> so that we don't override flags if set earlier than
> spi_nor_manufacturer_init_params(). I see that patch 2
sched_clock(), used by printk(), calls __USE_RTC() to know
whether to use realtime clock or timebase.
__USE_RTC() uses cpu_has_feature() which is initialised by
machine_init(). Before machine_init(), __USE_RTC() returns true,
leading to a program check exception on CPUs not having realtime
clock.
From: Guo Ren
610 has vipt aliasing issue, so we need to finish the cache flush
apis mentioned in cachetlb.rst to avoid data corruption.
Here is the list of modified apis in the patch:
- flush_kernel_dcache_page (new add)
- flush_dcache_mmap_lock(new add)
- flush_dcache_mmap_unl
On 8/23/2019 6:09 PM, Philipp Zabel wrote:
On Fri, 2019-08-23 at 17:47 +0800, Dilip Kota wrote:
[...]
Thanks for pointing it out.
Reset is not supported on LGM platform.
I will update the reset_device() definition to "return -EOPNOTSUPP"
In that case you can just drop intel_reset_device() com
On Thu 22-08-19 23:54:19, Pankaj Suryawanshi wrote:
> On Thu, Aug 22, 2019 at 6:22 PM Michal Hocko wrote:
> >
> > On Wed 21-08-19 22:23:44, Pankaj Suryawanshi wrote:
> > > Hello,
> > >
> > > 1. What are Pageblocks and migrate types(MIGRATE_CMA) in Linux memory ?
> >
> > Pageblocks are a simple gro
Let's add Stefan to the conversation.
He is the author of this commit.
Quoting Mao Wenan :
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function mtk_handle_irq:
drivers/net/ethernet/mediatek/mtk_eth_soc.c:1951:6: warning:
variable status set b
Hi Ricardo,
On Fri, Aug 23, 2019 at 02:37:31PM +0200, Ricardo Ribalda Delgado wrote:
> This control returns the unit cell size in nanometres. The struct provides
> the width and the height in separated fields to take into consideration
> asymmetric pixels and/or hardware binning.
> This control is
There is a mass of jobs between spin lock and unlock in the hardware
IRQ which will occupy much time originally. To make system work more
efficiently, this patch moves the jobs to the soft IRQ (bottom half) to
reduce the time in hardware IRQ.
Signed-off-by: Jian-Hong Pan
---
v2:
Change the spin_
On Sun, Aug 25, 2019 at 10:33:15PM -0500, Gustavo A. R. Silva wrote:
> Hi all,
>
> On 8/19/19 9:16 AM, tip-bot for Kirill A. Shutemov wrote:
> [..]
> >
> > diff --git a/arch/x86/boot/compressed/pgtable_64.c
> > b/arch/x86/boot/compressed/pgtable_64.c
> > index 5f2d03067ae5..2faddeb0398a 100644
>
Since commit 18dfef9c7f87 ("serial: atmel: convert to irq handling
provided mctrl-gpio"), the GPIOs interrupts are handled by
mctrl_gpio_irq_handle().
So, atmel_get_lines_status() can be completely killed and replaced by :
atmel_uart_readl(port, ATMEL_US_CSR);
Suggested-by: Uwe Kleine-König
Acked
Sasha Levin writes:
> On Thu, Aug 22, 2019 at 10:39:46AM +0200, Vitaly Kuznetsov wrote:
>>lantianyu1...@gmail.com writes:
>>
>>> From: Tianyu Lan
>>>
>>> Both Hyper-V tsc page and Hyper-V tsc MSR code use variable
>>> hv_sched_clock_offset for their sched clock callback and so
>>> define the var
Tony Chuang 於 2019年8月21日 週三 下午4:16寫道：
>
> Hi,
>
> > From: Jian-Hong Pan [mailto:jian-h...@endlessm.com]
> >
> > There is a mass of jobs between spin lock and unlock in the hardware
> > IRQ which will occupy much time originally. To make system work more
> > efficiently, this patch moves the jobs t
The __ethtool_get_link_ksettings symbol will be exported,
and external users may use an illegal address.
We should check the parameters before using them,
otherwise the system will crash.
[ 8980.991134] BUG: unable to handle kernel NULL pointer dereference at
(null)
[ 8980.993049] IP: [
Hi Mason,
masonccy...@mxic.com.tw wrote on Mon, 26 Aug 2019 10:52:31 +0800:
> Hi Miquel,
> >
> > Mason Yang wrote on Tue, 20 Aug 2019 13:53:48
> > +0800:
> >
> > > Macronix NANDs support randomizer operation for user data scrambled,
> > > which can be enabled with a SET_FEATURE.
> > >
> > >
On Fri 23-08-19 00:17:22, Pankaj Suryawanshi wrote:
> On Thu, Aug 22, 2019 at 6:32 PM Michal Hocko wrote:
> >
> > On Wed 21-08-19 22:58:03, Pankaj Suryawanshi wrote:
> > > Hello,
> > >
> > > Hard time to understand cma allocation how differs from normal
> > > allocation ?
> >
> > The buddy allocat
This enables DVFS for the Amlogic SM1 based SEI610 board by:
- Adding the SM1 SoC OPPs taken from the vendor tree
- Selecting the SM1 Clock controller instead of the G12A one
- Adding the CPU rail regulator, PWM and OPPs for each CPU nodes.
Each power supply can achieve 0.69V to 1.05V using a sing
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to the
CPU clock tree with a supplementaty mux to select the CPU0 clock instead.
Leave this as read-only since it's set up by the early boot stages.
Signed-off-by: Neil Armstrong
---
drivers/clk/meson/g12a.c | 184 ++
Add the new GP1 PLL for the Amlogic SM1 SoC, used to feed the new
DynamIQ Shared Unit of the ARM Cores Complex.
This also adds a dedicated set of clock and compatible for SM1.
Signed-off-by: Neil Armstrong
---
drivers/clk/meson/g12a.c | 300 +++
drivers/clk/m
Update the documentation to support clock driver for the Amlogic SM1 SoC
and expose the GP1, DSU and the CPU 1, 2 & 3 clocks.
SM1 clock tree is very close, the main differences are :
- each CPU core can achieve a different frequency, albeit a common PLL
- a similar tree as the clock tree has been
Following DVFS support for the Amlogic G12A and G12B SoCs, this serie
enables DVFS on the SM1 SoC for the SEI610 board.
The SM1 Clock structure is slightly different because of the Cortex-A55
core used, having the capability for each core of a same cluster to run
at a different frequency thanks to
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by
having a dedicate tree for each core similar to the CPU0 tree.
Like the DSU tree, a supplementaty mux has been added to use the CPU0
frequency instead.
But since the cluster only has a single power rail and shares a single PL
On 26/08/2019 09:25, Neil Armstrong wrote:
> This enables DVFS for the Amlogic SM1 based SEI610 board by:
> - Adding the SM1 SoC OPPs taken from the vendor tree
> - Selecting the SM1 Clock controller instead of the G12A one
> - Adding the CPU rail regulator, PWM and OPPs for each CPU nodes.
>
> Ea
Hi!
On 26.08.19 09:10, René van Dorst wrote:
Let's add Stefan to the conversation.
He is the author of this commit.
Thanks Rene.
Quoting Mao Wenan :
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function mtk_handle_irq:
drivers/net/ethernet
From: Ramuthevar Vadivel Murugan
Add a new compatible to use the sdhc-arasan host controller driver
with the eMMC PHY on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 17 +
1 file changed,
From: Ramuthevar Vadivel Muruganx
The current arasan sdhci PHY configuration isn't compatible
with the PHY on Intel's LGM(Lightning Mountain) SoC devices.
Therefore, add a new compatible, to adapt the Intel's LGM
eMMC PHY with arasan-sdhc controller to configure the PHY.
Signed-off-by: Ramuthev
Hi Ricardo,
On Fri, Aug 23, 2019 at 02:37:31PM +0200, Ricardo Ribalda Delgado wrote:
> This control returns the unit cell size in nanometres. The struct provides
> the width and the height in separated fields to take into consideration
> asymmetric pixels and/or hardware binning.
> This control is
From: Chunyan Zhang
Use console_initcall to save the console index we selected on the
command line to sprd_console before probe finished. Thus we can
make different processes to the uart devices during initialization
according to whether it is used for console.
Signed-off-by: Chunyan Zhang
Sign
From: Chunyan Zhang
When calling sprd_console_setup(), sprd_uart_port probably is NULL,
we should check that first instead of checking its items directly.
Also we should check membase to avoid accessing uart device before
its initialization finished.
Signed-off-by: Chunyan Zhang
Signed-off-by:
From: Chunyan Zhang
The sprd serial console can work with only 26M fixed clock,
but the probe() is returning fail if the clock "enable" is not
configured in device tree.
This patch will fix the problem to let the uart device which is
used for console can be initialized even missing "enable" cloc
From: Chunyan Zhang
After the commit 4007098f4ce4 (serial: sprd: Add power management for the
Spreadtrum serial controller),
the 'enable' clock was forced to be configured in device tree, otherwise the
uart devices couldn't be
probed successfully.
With this patch-set, the uart device which is
When insert and delete a vma, it will compute and propagate related subtree
gap. After some investigation, we can reduce subtree gap propagation a little.
[1]: This one reduce the propagation by update *next* gap after itself, since
*next* must be a parent in this case.
[2]: This one achieve
Since we link a vma to the leaf of a rb_tree, *next* must be a parent of
vma if *next* is not NULL. This means if we update *next* gap first, it
will be re-update again if vma's gap is bigger.
For example, we have a vma tree like this:
a
[0x9000, 0x1]
Current sequence to remove a vma is:
vma_rb_erase_ignore()
__vma_unlink_list()
vma_gap_update()
This may do some extra subtree_gap propagation due the vma is unlink
from list after rb_erase.
For example, we have a tree:
a
[0x9000, 0x1]
Add support to configure PCIe C5's sideband signals PERST# and CLKREQ#
as output and bi-directional signals respectively which unlike other
PCIe controllers sideband signals are not configured by default.
Signed-off-by: Vidya Sagar
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 ++
Add 3.3V and 12V supplies regulators information of x16 PCIe slot in
p2972- platform which is owned by C5 controller and also enable C5
controller.
Signed-off-by: Vidya Sagar
---
.../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++
.../boot/dts/nvidia/tegra194-p2972-.d
This patch series enables Tegra194's C5 controller which owns x16 slot in
p2972- platform. C5 controller's PERST# and CLKREQ# are not configured as
output and bi-directional signals by default and hence they need to be
configured explicitly. Also, x16 slot's 3.3V and 12V supplies are controlled
Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin
configuration information of a particular PCIe controller.
Signed-off-by: Vidya Sagar
---
.../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devi
Add optional bindings "vpcie3v3-supply" and "vpcie12v-supply" to describe
regulators of a PCIe slot's supplies 3.3V and 12V provided the platform
is designed to have regulator controlled slot supplies.
Signed-off-by: Vidya Sagar
---
.../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8 +
Add support to get regulator information of 3.3V and 12V supplies of a PCIe
slot from the respective controller's device-tree node and enable those
supplies. This is required in platforms like p2972- where the supplies
to x16 slot owned by C5 controller need to be enabled before attempting to
e
Add support to configure sideband signal pins when information is present
in respective controller's device-tree node.
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
b
On Sat 24-08-19 13:53:39, Andrew Morton wrote:
> On Fri, 23 Aug 2019 00:33:51 + Roman Gushchin wrote:
>
> > On Thu, Aug 22, 2019 at 04:27:09PM -0700, Andrew Morton wrote:
> > > On Mon, 19 Aug 2019 16:00:51 -0700 Roman Gushchin wrote:
> > >
> > > > v3:
> > > > 1) rearranged patches [2/3] a
On 6/20/19 7:03 AM, Alexandre Ghiti wrote:
This series fixes the fallback of the top-down mmap: in case of
failure, a bottom-up scheme can be tried as a last resort between
the top-down mmap base and the stack, hoping for a large unused stack
limit.
Lots of architectures and even mm code start t
On 25/08/2019 21:41, Martin Blumenstingl wrote:
> On Fri, Aug 23, 2019 at 10:15 AM Neil Armstrong
> wrote:
>>
>> To prepare support of the Amlogic SM1 based Khadas VIM3, move the non-G12B
>> specific nodes (all except DVFS and Audio) to a new meson-khadas-vim3.dtsi
> out of curiosity: is audio be
Hi Ricardo,
On Fri, Aug 23, 2019 at 02:37:33PM +0200, Ricardo Ribalda Delgado wrote:
> A struct v4l2_area containing the width and the height of a rectangular
> area.
>
> Signed-off-by: Ricardo Ribalda Delgado
> Suggested-by: Hans Verkuil
> ---
> Documentation/media/uapi/v4l/vidioc-queryctrl.rs
On Thu 22-08-19 18:29:34, Kirill A. Shutemov wrote:
> On Thu, Aug 22, 2019 at 02:56:56PM +0200, Vlastimil Babka wrote:
> > On 8/22/19 10:04 AM, Michal Hocko wrote:
> > > On Thu 22-08-19 01:55:25, Yang Shi wrote:
> > >> Available memory is one of the most important metrics for memory
> > >> pressure
Hi Ricardo,
On Fri, Aug 23, 2019 at 03:13:36PM +0200, Philipp Zabel wrote:
> On Fri, 2019-08-23 at 15:05 +0200, Ricardo Ribalda Delgado wrote:
> > On Fri, Aug 23, 2019 at 2:56 PM Philipp Zabel
> > wrote:
> > >
> > > On Fri, 2019-08-23 at 14:37 +0200, Ricardo Ribalda Delgado wrote:
> > > > Adding
On 25/08/2019 21:51, Martin Blumenstingl wrote:
> Hi Neil,
>
> the subject should be: dt-bindings: arm: amlogic: ...
damn sure
>
> On Fri, Aug 23, 2019 at 10:15 AM Neil Armstrong
> wrote:
>>
>> The Khadas VIM3 is also available with the Pin-to-pin compatible
>> Amlogic SM1 SoC in the S905D3 v
On 25/08/2019 21:55, Martin Blumenstingl wrote:
> On Fri, Aug 23, 2019 at 10:15 AM Neil Armstrong
> wrote:
>>
>> Add the Amlogic SM1 based Khadas VIM3, sharing all the same features
>> as the G12B based one, but:
>> - a different DVFS support since only a single cluster is available
>> - audio is
On Sun, Aug 25, 2019 at 09:23:22PM +0800, Changbin Du wrote:
> Add generic DWARF constant definitions. We will use it later.
>
> Signed-off-by: Changbin Du
> ---
> include/asm-generic/dwarf.h | 199
> 1 file changed, 199 insertions(+)
> create mode 100644 in
On Thu 22-08-19 08:33:40, Yang Shi wrote:
>
>
> On 8/22/19 1:04 AM, Michal Hocko wrote:
> > On Thu 22-08-19 01:55:25, Yang Shi wrote:
[...]
> > > And, they seems very common with the common workloads when THP is
> > > enabled. A simple run with MariaDB test of mmtest with THP enabled as
> > > al
I'm Seunghun Han and work at the Affiliated Institute of ETRI. I found
a bug related to improper buffer size calculation in crb_fixup_cmd_size
function.
When the TPM CRB regions are two or more, the crb_map_io function calls
crb_fixup_cmd_size twice to calculate command buffer size and response
bu
Hi Ricardo,
On Fri, Aug 23, 2019 at 02:37:36PM +0200, Ricardo Ribalda Delgado wrote:
> Helper for creating area controls.
>
> Signed-off-by: Ricardo Ribalda Delgado
With this squashed on 5/7 or separated if we want documentation
changes to get in separately
Reviewed-by: Jacopo Mondi
Thanks
On 24.08.19 00:52, Nadav Amit wrote:
__flush_tlb_one_user() currently flushes a single entry, and flushes it
both in the kernel and user page-tables, when PTI is enabled.
Change __flush_tlb_one_user() and related interfaces into
__flush_tlb_range() that flushes a range and does not flush the use
Hi Ricardo,
On Fri, Aug 23, 2019 at 02:37:37PM +0200, Ricardo Ribalda Delgado wrote:
> Instead of creating manually the V4L2_CID_UNIT_CELL_SIZE control, lets
> use the helper.
>
I think you should drop 4/7 and use directly the new helper here.
Thanks
j
> Signed-off-by: Ricardo Ribalda Delgado
On Fri, Aug 16, 2019 at 11:02:22PM +0800, Pingfan Liu wrote:
> On Thu, Aug 15, 2019 at 01:22:22PM -0400, Jerome Glisse wrote:
> > On Tue, Aug 06, 2019 at 04:00:10PM +0800, Pingfan Liu wrote:
> > > MIGRATE_PFN_MIGRATE marks a valid pfn, further more, suitable to migrate.
> > > As for hole, there is
On Mon, Aug 26, 2019 at 6:25 AM Gustavo A. R. Silva
wrote:
>
> Hi Rafael,
>
> On 4/23/19 3:23 AM, Rafael J. Wysocki wrote:
> > On Mon, Apr 22, 2019 at 5:55 PM Gustavo A. R. Silva
> > wrote:
> >>
> >> Hi all,
> >>
> >> Friendly ping:
> >>
> >> Who can take this?
> >
> > I've been waiting for Len t
No module currently messed with clearing or setting the execute
permission of kernel memory, and none really should.
Signed-off-by: Christoph Hellwig
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/mm/pageattr.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/x86/mm/pageattr.c b/arch/x8
Hi all,
while looking into implementing a DMA memory allocator for PCIe unsnooped
transactions I've started looking at the set_memory_* and related APIs,
and it turns out that many of them are unused. Fix for that below.
Changes since v2:
- dropped the already merged arm64 patch
- fix a subjec
Signed-off-by: Christoph Hellwig
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/include/asm/set_memory.h | 1 -
arch/x86/mm/pageattr.c| 17 -
2 files changed, 18 deletions(-)
diff --git a/arch/x86/include/asm/set_memory.h
b/arch/x86/include/asm/set_memory.h
index fd
Signed-off-by: Christoph Hellwig
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/include/asm/set_memory.h | 1 -
arch/x86/mm/pageattr.c| 6 --
2 files changed, 7 deletions(-)
diff --git a/arch/x86/include/asm/set_memory.h
b/arch/x86/include/asm/set_memory.h
index 2ee8e469dcf5..cf
Greg KH schreef op ma 26-08-2019 om 06:34 [+0200]:
> It's on that key already, have you refreshed your version of it?
I have now. sas...@kernel.org (and another identity) is now on that key.
Thanks,
Paul Bolle
These wrappers don't provide a real benefit over just using
set_memory_x and set_memory_nx.
Signed-off-by: Christoph Hellwig
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/include/asm/set_memory.h | 2 --
arch/x86/kernel/machine_kexec_32.c | 4 ++--
arch/x86/mm/init_32.c | 2 +-
Signed-off-by: Christoph Hellwig
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/include/asm/set_memory.h | 5 ---
arch/x86/mm/pageattr.c| 75 ---
2 files changed, 80 deletions(-)
diff --git a/arch/x86/include/asm/set_memory.h
b/arch/x86/include/asm/set_m
On 24.08.2019 17:03, Heiner Kallweit wrote:
>
> On 22.08.2019 09:18, Christian Herber wrote:
>> On 21.08.2019 20:57, Andrew Lunn wrote:
>>>
The current patch set IMO is a little bit hacky. I'm not 100% happy
with the implicit assumption that there can't be devices supporting
T1 and
The dirty_log_test is failing on some old machines like Xeon E3-1220
with tripple faults when writting to the tracked memory region:
Test iterations: 32, interval: 10 (ms)
Testing guest mode: PA-bits:52, VA-bits:48, 4K pages
guest physical test memory offset: 0x7fbffef000
Test Asserti
On Mon, Aug 26, 2019 at 08:56:39AM +0200, Christoph Hellwig wrote:
> On Thu, Aug 22, 2019 at 12:10:23PM -0700, Sagi Grimberg wrote:
> >> You are correct that this information can be derived from sysfs, but the
> >> main reason why we add these here, is because in udev rule we can't
> >> just go ahe
On 2019.08.16 10:35:26 +0800, Tina Zhang wrote:
> Deliver the display refresh events to the user land. Userspace can use
> the irq mask/unmask mechanism to disable or enable the event delivery.
>
> As we know, delivering refresh event at each vblank safely avoids
> tearing and unexpected event ove
On Mon, Aug 26, 2019 at 12:08:38PM +0530, Bhaskar Chowdhury wrote:
Due, learn to properly trim emails...
> For some unknown reason kernel.org still showing me 5.2.9 ..Please refer
> to the attached screenshot.
What mirror are you hitting here? There is a way somehow to see that on
your end, I
Hi Guo,
Guo Ren 於 2019年8月24日 週六 上午8:54寫道：
>
> Please check CONFIG_FRAME_POINTER
>
> 1 *frame = *((struct stackframe *)frame->fp - 1);
> This code is origionally from riscv/kernel/stacktrace.c: walk_stackframe
>
> In linux/Makefile it'll involve the options for gcc to definitely
> store ra & prev_
On Fri, 2019-08-23 at 19:14 +, Forrest Fleming wrote:
> suggested by checkpatch
>
> Signed-off-by: Forrest Fleming
> ---
> .../net/ethernet/intel/e1000/e1000_param.c| 28 +--
> 1 file changed, 14 insertions(+), 14 deletions(-)
While I do not see an issue with this change
On 25/08/2019 23:10, Martin Blumenstingl wrote:
> Hi Neil,
>
> thank you for this update
> I haven't tried this on the 32-bit SoCs yet, but I am confident that I
> can make it work by "just" adding the SoC specific bits!
>
> On Fri, Aug 23, 2019 at 11:06 AM Neil Armstrong
> wrote:
> [...]
>> +/
On 26/08/2019 09.57, Peter Xu wrote:
> The dirty_log_test is failing on some old machines like Xeon E3-1220
> with tripple faults when writting to the tracked memory region:
>
> Test iterations: 32, interval: 10 (ms)
> Testing guest mode: PA-bits:52, VA-bits:48, 4K pages
> guest physical tes
On 2019/8/23 22:05, Alexandre Belloni wrote:
> On 23/08/2019 20:45:53+0800, YueHaibing wrote:
>> If WATCHDOG_CORE is not set, build fails:
>>
>> drivers/rtc/rtc-pcf2127.o: In function `pcf2127_probe.isra.6':
>> drivers/rtc/rtc-pcf2127.c:478: undefined reference to
>> `devm_watchdog_register_dev
Hi Eric,
On 2019/8/26 1:28, Eric Biggers wrote:
> On Sat, Aug 24, 2019 at 11:25:24PM -0400, Theodore Y. Ts'o wrote:
>> On Fri, Aug 23, 2019 at 10:47:34AM +0800, Shaokun Zhang wrote:
>>> From: Yang Guo
>>>
>>> @es_stats_cache_hits and @es_stats_cache_misses are accessed frequently in
>>> ext4_es_l
On Mon, Aug 26, 2019 at 10:02 AM Artem Bityutskiy wrote:
>
> On Mon, 2019-08-26 at 09:55 +0200, Rafael J. Wysocki wrote:
>
> Technically, Len Brown is the turbostat maintainer and I have been
>
> waiting for him to review the patch at least. Let me talk to Len.
>
>
>
> Hi Rafael,
>
>
> I also sen
On Thu, 22 Aug 2019 15:22:19 +0200
Mario Tesi wrote:
> From: mario tesi
>
> According to the latest version of datasheet the mask
> for number of unread sensor data in FIFO_STATUS registers
> has been extended to 10 bits
>
> The devices involved are:
>- LSM6DSO
On 8/26/19 9:23 AM, Dongxu Liu wrote:
> The __ethtool_get_link_ksettings symbol will be exported,
> and external users may use an illegal address.
> We should check the parameters before using them,
> otherwise the system will crash.
>
> [ 8980.991134] BUG: unable to handle kernel NULL pointer
I'm Seunghun Han and work at the Affiliated Institute of ETRI. I got
an AMD system which had a Ryzen Threadripper 1950X and MSI mainboard, and
I had a problem with AMD's fTPM. My machine showed an error message below,
and the fTPM didn't work because of it.
[ 5.732084] tpm_crb MSFT0101:00: can't
On Mon, Aug 26, 2019 at 10:11:34AM +0200, Thomas Huth wrote:
> On 26/08/2019 09.57, Peter Xu wrote:
> > The dirty_log_test is failing on some old machines like Xeon E3-1220
> > with tripple faults when writting to the tracked memory region:
> >
> > Test iterations: 32, interval: 10 (ms)
> > Te
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