On April 11, 2019 6:50:47 PM GMT+02:00, Linus Torvalds
wrote:
>On Wed, Apr 10, 2019 at 4:43 PM Christian Brauner
> wrote:
>>
>> RFC-2:
>> This alternative patchset uses anonymous file descriptors instead of
>> file descriptors from /proc/.
>
>I think I prefer this one. Your diffstat makes it look
On Thu 11-04-19 12:18:33, Joel Fernandes wrote:
> On Thu, Apr 11, 2019 at 6:51 AM Michal Hocko wrote:
> >
> > On Wed 10-04-19 18:43:51, Suren Baghdasaryan wrote:
> > [...]
> > > Proposed solution uses existing oom-reaper thread to increase memory
> > > reclaim rate of a killed process and to make
From: Jérôme Glisse
Just fixed Kconfig and build when ODP was not enabled, other than that
this is the same as v3. Here is previous cover letter:
Git tree with all prerequisite:
https://cgit.freedesktop.org/~glisse/linux/log/?h=rdma-odp-hmm-v4
This patchset convert RDMA ODP to use HMM underneat
From: Jérôme Glisse
Convert ODP to use HMM so that we can build on common infrastructure
for different class of devices that want to mirror a process address
space into a device. There is no functional changes.
Changes since v3:
- fix Kconfig to properly depends on HMM, also make sure things
On 4/10/19 11:59 PM, Christoph Hellwig wrote:
On Wed, Apr 10, 2019 at 04:04:41PM -0700, Atish Patra wrote:
of_get_cpu_node expects a logical cpu id not a hartid.
But only because you changed that with your patch 1, so it should
be folded into that.
Yes. I should merge this to patch 1. Other
On 4/11/2019 1:48 AM, Masahiro Yamada wrote:
I was going by what Kconfig tells me
Symbol: KALLSYMS_ALL [=n]
Depends on: DEBUG_KERNEL [=n] && KALLSYMS [=y]
Lots of features have 'depends on DEBUG_KERNEL'.
What is special about KALLSYMS_ALL here?
I had to do some learning about KALLSYSM_ALL.
After some preceding changes, PM domains managed by genpd may contain
CPU devices, so idle state residency values should be taken into
account during the state selection process. [The residency value is
the minimum amount of time to be spent by a CPU (or a group of CPUs)
in an idle state in order t
On Thu, Apr 11, 2019 at 2:30 AM Masahiro Yamada
wrote:
>
> We use $(LD) to link vmlinux, modules, decompressors, etc.
>
> VDSO is the only exceptional case where $(CC) is used as the linker
> driver, but I do not know why we need to do so. VDSO uses a special
> linker script, and does not link sta
On Thu 11-04-19 09:47:31, Suren Baghdasaryan wrote:
[...]
> > I would question whether we really need this at all? Relying on the exit
> > speed sounds like a fundamental design problem of anything that relies
> > on it.
>
> Relying on it is wrong, I agree. There are protections like allocation
>
Hi,
On Thu, Apr 11, 2019 at 05:49:36PM +0100, Sudeep Holla wrote:
> On Thu, Apr 11, 2019 at 11:42:28AM +, Koskinen, Aaro (Nokia - FI/Espoo)
> wrote:
> > From: Sudeep Holla [sudeep.ho...@arm.com]:
> > > static void psci_sys_reset(enum reboot_mode reboot_mode, const char *cmd)
> > > {
> > > +
Hi Miquel,
On 2/5/19 6:55 AM, Miquel Raynal wrote:
[..]
>> @@ -3280,12 +3280,14 @@ static void onenand_check_features(struct mtd_info
>> *mtd)
>> if ((this->version_id & 0xf) == 0xe)
>> this->options |= ONENAND_HAS_NOP_1;
>> }
>> +
Quoting Jolly Shah (2019-03-04 15:27:46)
> From: Rajan Vaja
>
> Zero divider is valid and default for some of ZynqMP
> clocks. Allow zero divisor when CLK_DIVIDER_ALLOW_ZERO
> for the clock is set.
>
> Signed-off-by: Rajan Vaja
> Signed-off-by: Jolly Shah
> ---
Applied to clk-next
Quoting Jolly Shah (2019-03-04 15:19:10)
> From: Rajan Vaja
>
> Versal EEMI APIs uses clock device ID which is combination of class,
> subclass, type and clock index (e.g. 0x8104006 in which 0-13 bits are
> for index(6 in given example), 14-19 bits are for clock type (i.e pll,
> out or ref, 1 in
Hi,
Changes:
1. I removed this sunxi_cpufreq_soc_data structure for now.
2. Convert to less generic name.
3. Update soc_bin xlate. (LINE:484
https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/soc/sunxi/sunxi-sid.c)
Now temporarily consider it as supporting
On Fri, Apr 05, 2019 at 08:32:10PM +0300, Yury Norov wrote:
> Add tests for non-number character, empty regions, integer overflow.
>
> Signed-off-by: Yury Norov
> Reviewed-by: Andy Shevchenko
> ---
> lib/test_bitmap.c | 18 +-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
On 3/28/19 4:47 PM, Mike Kravetz wrote:
> hugetlb uses a fault mutex hash table to prevent page faults of the
> same pages concurrently. The key for shared and private mappings is
> different. Shared keys off address_space and file index. Private
> keys off mm and virtual address. Consider a pr
> >> +
> >> +/*
> >> + * livepatch.h - Kernel Live Patching Core
> >> + *
> >> + * Copyright (C) 2016 Josh Poimboeuf
> >> + */
> >> +
> >> +#ifndef _UAPI_LIVEPATCH_H
> >> +#define _UAPI_LIVEPATCH_H
> >> +
> >> +#include
> >
> >
> > Why is this include needed?
> >
> >> +#define KLP_RELA_PREFIX
Hi,
Changes:
1. I removed this sunxi_cpufreq_soc_data structure for now.
2. Convert to less generic name.
3. Update soc_bin xlate. (LINE:484
https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/soc/sunxi/sunxi-sid.c)
(maybe attach a file is better)
Now
On 4/11/19 12:01 AM, Christoph Hellwig wrote:
On Wed, Apr 10, 2019 at 04:04:42PM -0700, Atish Patra wrote:
nosmp command line option sets max_cpus to zero. No secondary harts
will boot if this is enabled. But present cpu mask will still point to
all possible masks.
Fix present cpu mask for nosm
Quoting Ding Xiang (2019-03-15 00:29:24)
> use PTR_ERR_OR_ZERO inetead of return code
>
> Signed-off-by: Ding Xiang
> ---
Applied to clk-next
Quoting Yue Haibing (2019-03-19 08:35:04)
> From: YueHaibing
>
> Fix sparse warning:
>
> drivers/clk/tegra/clk-super.c:124:22:
> warning: symbol 'tegra_clk_super_mux_ops' was not declared. Should it be
> static?
>
> Signed-off-by: YueHaibing
> ---
Applied to clk-next
Quoting Nicholas Mc Guire (2019-04-11 04:04:11)
> Providing a range for usleep_range() allows the hrtimer subsystem to
> coalesce timers - the delay is runtime configurable so a factor 2
> is taken to provide the range. With the expected range for
> enable_delay_us being milliseconds, the range sho
Hi Matthias,
Am Donnerstag, 11. April 2019, 19:59:17 CEST schrieb Matthias Kaehlcke:
> The USB PHY clock can be configured as (grand) parent of uart0_sclk and
> sclk_gpu. It has been observed that UART0 doesn't work reliably in high
> speed mode with the PHY clock as input when certain USB devices
> diff --git a/samples/livepatch/Makefile b/samples/livepatch/Makefile
> index 2472ce39a18d..8b9b42a258ad 100644
> --- a/samples/livepatch/Makefile
> +++ b/samples/livepatch/Makefile
> @@ -1,3 +1,4 @@
> +LIVEPATCH_livepatch-sample := y
> obj-$(CONFIG_SAMPLE_LIVEPATCH) += livepatch-sample.o
> ob
On Thu, Apr 4, 2019 at 10:33 PM Amir Goldstein wrote:
>
> On Thu, Apr 4, 2019 at 10:05 PM Al Viro wrote:
> >
> ...
> > OK, so... My first reaction had been complete BS. However, the
> > same goes for your analysis - it's not an ordering problem at all.
> > What happens is that we are replacing
Readout the enabled state so it is possible to get the pre-userspace
handler working. Also, avoid disabling the watchdog to ensure it continues
working and triggers if there is an issue later in the boot or if userspace
fails to start.
Signed-off-by: Alexandre Belloni
---
drivers/watchdog/pnx400
On 11/04/2019 10:32, Yuantian Tang wrote:
> Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core cluster
> sensor is used to monitor the temperature of core and SoC platform is for
> platform. The current dts only support the first sensor.
> This patch adds the second sensor node to d
On Thu, Apr 11, 2019 at 08:12:43PM +0200, Michal Hocko wrote:
> On Thu 11-04-19 12:18:33, Joel Fernandes wrote:
> > On Thu, Apr 11, 2019 at 6:51 AM Michal Hocko wrote:
> > >
> > > On Wed 10-04-19 18:43:51, Suren Baghdasaryan wrote:
> > > [...]
> > > > Proposed solution uses existing oom-reaper thr
On 2019-04-11 2:48 pm, Robin Murphy wrote:
On 11/04/2019 13:46, Heiko Stuebner wrote:
Hi Robin,
Am Samstag, 30. März 2019, 00:24:16 CEST schrieb Robin Murphy:
On 2019-03-27 12:00 pm, Heiko Stuebner wrote:
Hi,
Am Dienstag, 26. März 2019, 14:49:16 CET schrieb Katsuhiro Suzuki:
Hello Robin,
S
This patch adds suspend and resume PM ops for tegra SDHCI.
Acked-by: Thierry Reding
Signed-off-by: Sowjanya Komatineni
---
drivers/mmc/host/sdhci-tegra.c | 58 +-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c
Hi Doug, Elaine,
Am Donnerstag, 11. April 2019, 16:42:23 CEST schrieb Doug Anderson:
> On Wed, Apr 10, 2019 at 8:42 PM elaine.zhang wrote:
> > 在 2019/4/10 下午11:25, Doug Anderson 写道:
> > > On Tue, Apr 9, 2019 at 11:42 PM elaine.zhang
> > > wrote:
> > >> 在 2019/4/10 上午4:47, Douglas Anderson 写道:
>
On 10/04/2019 22:07, Tony Lindgren wrote:
> Hi,
>
> * Daniel Lezcano [190410 17:02]:
>> can you ask for an acked-by before pulling a patch in your tree?
>
> I certainly do ask and wait for acks where possible :)
Ok, I may have missed them.
> Note that I have not applied this patch. I just adde
Am Dienstag, 9. April 2019, 22:47:06 CEST schrieb Douglas Anderson:
> Most rk3288-based boards are derived from the EVB and thus use a PWM
> regulator for the logic rail. However, most rk3288-based boards don't
> specify the PWM regulator in their device tree. We'll deal with that
> by making it
0-day/Kbuild starts complaining about missed module dependencies and
compilation issues. Since codecs and soc drivers need to be compilable
independently, let's fix this using the following model:
SOUNDWIRE_INTEL select ---
|
The mechanism should be
config CODEC_XYX_SDW
depends on SOUNDWIRE
select REGMAP_SOUNDWIRE
config REGMAP_SOUNDWIRE
depends on SOUNDWIRE
select SOUNDWIRE_BUS
SOUNDWIRE_BUS can be independently selected by the SOC driver. The SOC
driver should not know or care about REGM
SOUNDWIRE_BUS can be selected independendly by the SOC driver
(e.g. SOUNDWIRE_INTEL) or the codec driver (via REGMAP_SOUNDWIRE).
Remove wrong-way link between SOUNDWIRE_BUS and REGMAP_SOUNDWIRE
Fixes: 6c49b32d3c09 ('soundwire: select REGMAP_SOUNDWIRE')
Signed-off-by: Pierre-Louis Bossart
---
dr
Am Dienstag, 9. April 2019, 22:47:07 CEST schrieb Douglas Anderson:
> From: Caesar Wang
>
> We use the new PWM IP on RK3288, but the PWM's clock indeed incorrect.
>
> Signed-off-by: Caesar Wang
> Signed-off-by: Douglas Anderson
applied into a branch for 5._3_ ... as it requires a change comin
On Thu, Apr 11, 2019 at 09:14:37PM +0200, Alexandre Belloni wrote:
> Readout the enabled state so it is possible to get the pre-userspace
> handler working. Also, avoid disabling the watchdog to ensure it continues
> working and triggers if there is an issue later in the boot or if userspace
> fail
On Thu, Apr 11, 2019 at 09:20:56PM +0200, Daniel Lezcano wrote:
> On 10/04/2019 22:07, Tony Lindgren wrote:
> > Hi,
> >
> > * Daniel Lezcano [190410 17:02]:
> >> can you ask for an acked-by before pulling a patch in your tree?
> >
> > I certainly do ask and wait for acks where possible :)
>
> O
This patch enables command queue support for Tegra186 SDMMC4.
Tested-by: Jon Hunter
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186
Default tap and trim values are incorrect for Tegra186 SDMMC4.
This patch fixes it.
Tested-by: Jon Hunter
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.d
Add a documentation of LED Multicolor LED class specific
sysfs attributes.
Signed-off-by: Dan Murphy
---
.../ABI/testing/sysfs-class-led-multicolor| 91 +++
1 file changed, 91 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-class-led-multicolor
diff --git a
Add DT bindings for the LEDs multicolor class framework.
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/leds/common.txt | 2 +
.../bindings/leds/leds-class-multicolor.txt | 142 ++
2 files changed, 144 insertions(+)
create mode 100644
Documentation/devicetree/b
Introduce the LP5036/30/24/18 RGB LED driver.
The difference in these parts are the number of
LED outputs where the:
LP5036 can control 36 LEDs
LP5030 can control 30 LEDs
LP5024 can control 24 LEDs
LP5018 can control 18 LEDs
The device has the ability to group LED output into control banks
so tha
Introduce the bindings for the Texas Instruments LP5036, LP5030, LP5024 and the
LP5018
RGB LED device driver. The LP5036/3024/18 can control RGB LEDs individually
or as part of a control bank group. These devices have the ability
to adjust the mixing control for the RGB LEDs to obtain different
On Wed, Apr 10, 2019 at 10:55:00PM +0800, kernel test robot wrote:
> Greetings,
>
> 0day kernel testing robot got the below dmesg and the first bad commit is
>
> https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git core/mm
>
> commit 1808d65b55e4489770dd4f76fb0dff5b81eb9b11
> Author:
Add a new color ID that is declared as MULTICOLOR as with the
multicolor framework declaring a definitive color is not accurate
as the node can contain multiple colors.
Signed-off-by: Dan Murphy
---
drivers/leds/led-class.c | 1 +
include/dt-bindings/leds/common.h | 3 ++-
2 files chang
Introduce a multicolor class that groups colored LEDs
within a LED node.
The framework allows for dynamically setting individual LEDs
or setting brightness levels of LEDs and updating them virtually
simultaneously.
Signed-off-by: Dan Murphy
---
drivers/leds/Kconfig | 10 +
driv
Add the support documentation on the multicolor LED framework.
This document defines the directores and file generated by the
multicolor framework. It also documents usage.
Signed-off-by: Dan Murphy
---
Documentation/leds/leds-class-multicolor.txt | 99
1 file changed, 99 i
I have updated the patchset for the multicolor framework and scrubed the base
code. I have incoroporated the minor changes that were asked for. But I still
have not added any code for the brightness models as this is still in
discussion.
I have also included the TI LP50xx driver that demonstrat
> On Mon, 1 Apr 2019 at 19:43, Sowjanya Komatineni
> wrote:
> >
> > > > >
> > > > > Default tap and trim values are incorrect for Tegra186 SDMMC4.
> > > > > This patch fixes it.
> > > > >
> > > > > Tested-by: Jon Hunter
> > > > > Signed-off-by: Sowjanya Komatineni
> > > >
> > > > Is this a fix
Hi Rob,
I've collected references to the DT patches we're waiting
to be reviewed. This is just to make sure that none of them
will be missed - recent traffic on the linux-leds list
is a bit heavier.
[0] - draft of LED multi color class - we would especially like
to get a feedback on the pr
On 4/8/19 2:16 AM, Hans de Goede wrote:>
>
> Hmm, interesting so you have hibernation working on a T100TA
> (with 5.0 + 02e45646d53b reverted), right ?
>
Hi Hans and Kai-Heng
First, apologies for how long it took me to reply to both your inquiries.
In trying to answer them I discovered some i
Hi Daniel,
On Tue, 2019-04-09 at 19:54 +0200, Daniel Mack wrote:
> On 9/4/2019 6:55 PM, Trond Myklebust wrote:
> > On Tue, 2019-04-09 at 18:25 +0200, Daniel Mack wrote:
> > > On 8/4/2019 8:51 PM, Trond Myklebust wrote:
> > > > On Mon, 2019-04-08 at 19:01 +0200, Daniel Mack wrote:
> > > > > Hi,
> >
On 4/7/19 9:44 PM, Kai Heng Feng wrote:
> at 4:58 AM, Robert R. Howell wrote:
>
>>> On 03-04-19 07:43, Kai-Heng Feng wrote:
i2c-designware-platdrv fails to work after the system restored from
hibernation:
>> I did try applying your (Hans') patch to a 5.0.0 and a 5.1-rc3 kernel,
>> inste
On Thu, Apr 11, 2019 at 09:39:06PM +0200, Peter Zijlstra wrote:
> I think this bisect is bad. If you look at your own logs this patch
> merely changes the failure, but doesn't make it go away.
>
> Before this patch (in fact, before tip/core/mm entirely) the errror
> reads like the below, which sug
On Thu, 11 Apr 2019 at 18:51, Mathieu Desnoyers
wrote:
> - On Apr 11, 2019, at 12:42 PM, Will Deacon will.dea...@arm.com wrote:
> > Peter suggests that anything of the form 0xe7fxdefx should trap in both A32
> > and T32, although it does assemble to UDF; B in T16. I'm not sure we
> > should g
On Thu, Apr 11, 2019 at 11:19 AM Michal Hocko wrote:
>
> On Thu 11-04-19 09:47:31, Suren Baghdasaryan wrote:
> [...]
> > > I would question whether we really need this at all? Relying on the exit
> > > speed sounds like a fundamental design problem of anything that relies
> > > on it.
> >
> > Rely
> On Thu, Apr 04, 2019 at 05:14:10PM -0700, Sowjanya Komatineni wrote:
> > Some SPI Master controllers support configuring Least significant byte
> > first or Most significant byte first order for transfers. Also some
> > SPI slave devices expect bytes to be in Least significant first order
> >
On Thu, Apr 11, 2019 at 01:50:42PM -0400, Joel Fernandes (Google) wrote:
> pidfd are /proc/pid directory file descriptors referring to a task group
> leader. Android low memory killer (LMK) needs pidfd polling support to
> replace code that currently checks for existence of /proc/pid for
> knowing
On Thu, Apr 11, 2019 at 05:47:46AM +0100, Al Viro wrote:
> The reason for that dance is the locking - shrink list belongs to whoever
> has set it up and nobody else is modifying it. So __dentry_kill() doesn't
> even try to remove the victim from there; it does all the teardown
> (detaches from in
On April 11, 2019 10:00:59 PM GMT+02:00, Joel Fernandes
wrote:
>On Thu, Apr 11, 2019 at 01:50:42PM -0400, Joel Fernandes (Google)
>wrote:
>> pidfd are /proc/pid directory file descriptors referring to a task
>group
>> leader. Android low memory killer (LMK) needs pidfd polling support
>to
>> repl
On Thu, Apr 11, 2019 at 09:19:55AM -0400, Steven Rostedt wrote:
> On Thu, 11 Apr 2019 04:21:06 -0400
> Joel Fernandes wrote:
>
> > Patch 2/3 and 3/3 would not be nececessary if this works out. 1/3 may be a
> > nice clean up but is not something urgent and we could do that in the future
> > if nee
On Thu, Apr 11, 2019 at 10:35 AM Kees Cook wrote:
>
> On Thu, Apr 11, 2019 at 9:42 AM Guenter Roeck wrote:
> >
> > On Thu, Apr 11, 2019 at 9:19 AM Kees Cook wrote:
> > >
> > > On Thu, Mar 7, 2019 at 7:43 AM Dan Williams
> > > wrote:
> > > > I went ahead and acquired one of these boards to see
On 25/03/2019 04:05, Sugaya Taichi wrote:
> Fix mlb_set_oneshot_state() to enable one-shot timer.
> The function should stop and start a timer, but "start" statement was
> dropped. Kick the register to start one-shot timer.
Can you add the "Fixes" tag please.
> Signed-off-by: Sugaya Taichi
> -
On Sun, Mar 24, 2019 at 10:24 PM Wu Hao wrote:
Hi Hao,
>
> This patch adds support for power management private feature under
> FPGA Management Engine (FME), sysfs interfaces are introduced for
> different power management functions, users could use these sysfs
> interface to get current number
On Thu 11-04-19 15:14:30, Joel Fernandes wrote:
> On Thu, Apr 11, 2019 at 08:12:43PM +0200, Michal Hocko wrote:
> > On Thu 11-04-19 12:18:33, Joel Fernandes wrote:
> > > On Thu, Apr 11, 2019 at 6:51 AM Michal Hocko wrote:
> > > >
> > > > On Wed 10-04-19 18:43:51, Suren Baghdasaryan wrote:
> > > >
On Thu, Apr 11, 2019 at 09:39:09AM +, S.j. Wang wrote:
> Unify the supported input and output rate, add the
We previously didn't support 5KHz->5KHz, but now we do? That'd be
great if so.
> static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
> @@ -626,14 +629,18 @@ static i
(Please trim replies to save me time)
Quoting Nicolas Boichat (2019-03-14 16:21:26)
> On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu wrote:
> > +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
> > +{
> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + u32 mask = GENMASK(mux->data->
On 11/04/2019 21:36, Nathan Chancellor wrote:
> On Thu, Apr 11, 2019 at 09:20:56PM +0200, Daniel Lezcano wrote:
>> On 10/04/2019 22:07, Tony Lindgren wrote:
>>> Hi,
>>>
>>> * Daniel Lezcano [190410 17:02]:
can you ask for an acked-by before pulling a patch in your tree?
>>>
>>> I certainly do
Quoting Nicolas Boichat (2019-03-07 22:20:27)
> On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu wrote:
> >
> > From: Owen Chen
> >
> > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
> >add a variable to indicate this change and
> >backward-compatible.
> > 2. fmin: The pll freq
On 11/04/2019 09:11, Sugaya, Taichi wrote:
> This is ping..
> Does anyone have any comments?
Other than the missing Fixes tag, the patches look good to me.
> On 2019/03/25 12:05, Sugaya Taichi wrote:
>> This series fixes a bug and cleanup code about timer driver for
>> Milbeaut M10V.
>> Since i
Quoting Weiyi Lu (2019-03-04 21:05:40)
> From: Owen Chen
>
> 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
>add a variable to indicate this change and
>backward-compatible.
> 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
>1.5Ghz, add a variable to in
Quoting Weiyi Lu (2019-03-04 21:05:39)
> From: Owen Chen
>
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new API to handl
Quoting Weiyi Lu (2019-03-04 21:05:38)
> From: Owen Chen
>
> PLLs with tuner_en bit, such as APLL1, need to disable
> tuner_en before apply new frequency settings, or the new frequency
> settings (pcw) will not be applied.
> The tuner_en bit will be disabled during changing PLL rate
> and be rest
Quoting Weiyi Lu (2019-03-04 21:05:42)
> Add MT8183 clock dt-bindings, include topckgen, apmixedsys,
> infracfg, mcucfg and subsystem clocks.
>
> Signed-off-by: Weiyi Lu
> Reviewed-by: Rob Herring
> ---
Applied to clk-next
On Thu 11-04-19 12:56:32, Suren Baghdasaryan wrote:
> On Thu, Apr 11, 2019 at 11:19 AM Michal Hocko wrote:
> >
> > On Thu 11-04-19 09:47:31, Suren Baghdasaryan wrote:
> > [...]
> > > > I would question whether we really need this at all? Relying on the exit
> > > > speed sounds like a fundamental
From: Yazen Ghannam
The number of MCA banks is provided per logical CPU. Historically, this
number has been the same across all CPUs, but this is not an
architectural guarantee. Future AMD systems may have MCA bank counts
that vary between logical CPUs in a system.
This issue was partially addre
From: Yazen Ghannam
The OS is expected to write all bits in MCA_CTL. However, only
implemented bits get set in the hardware.
Read back MCA_CTL so that the value in the hardware is saved and
reported through sysfs.
Signed-off-by: Yazen Ghannam
---
Link:
https://lkml.kernel.org/r/20190408141205.
From: Yazen Ghannam
The OS is expected to write all bits to MCA_CTL for each bank. However,
some banks may be unused in which case the registers for such banks are
Read-as-Zero/Writes-Ignored. Also, the OS may not write any control bits
because of quirks, etc.
A bank can be considered uninitiali
From: Yazen Ghannam
Current AMD systems have unique MCA banks per logical CPU even though
the type of the banks may all align to the same bank number. Each CPU
will have control of a set of MCA banks in the hardware and these are
not shared with other CPUs.
For example, bank 0 may be the Load-St
From: Yazen Ghannam
The struct mce_banks[] array is only used in mce/core.c so move the
definition of struct mce_bank to mce/core.c and make the array static.
Also, change the "init" field to bool type.
Signed-off-by: Yazen Ghannam
---
Link:
https://lkml.kernel.org/r/20190408141205.12376-2-yaz
From: Yazen Ghannam
On legacy systems, the addresses of the MCA_MISC* registers need to be
recursively discovered based on a Block Pointer field in the registers.
On Scalable MCA systems, the register space is fixed, and particular
addresses can be derived by regular offsets for bank and registe
From: Yazen Ghannam
The focus of this patchset is define and use the MCA bank structures
and bank count per logical CPU.
With the exception of patch 4, this set applies to systems in production
today.
Patch 1:
Moves the declaration of struct mce_banks[] to the only file it's used.
Patch 2:
Spl
On Thu, Apr 11, 2019 at 10:02:32PM +0200, Christian Brauner wrote:
> On April 11, 2019 10:00:59 PM GMT+02:00, Joel Fernandes
> wrote:
> >On Thu, Apr 11, 2019 at 01:50:42PM -0400, Joel Fernandes (Google)
> >wrote:
> >> pidfd are /proc/pid directory file descriptors referring to a task
> >group
> >
Quoting Weiyi Lu (2019-03-04 21:05:43)
> On some Mediatek platforms, there are critical clocks of
> clock gate type.
> To register clock gate with flags CLK_IS_CRITICAL,
> we need to add the flags field in mtk_gate data and register APIs.
>
> Signed-off-by: Weiyi Lu
This patch doesn't apply, bec
Quoting Weiyi Lu (2019-03-04 21:05:44)
> In previous MediaTek PLL design, it assumes the pcw change control
> is always on the CON1 register.
> However, the pcw change bit on MT8183 was moved onto CON0 because
> the the PCW length of audio PLLs are extended to 32-bit.
> Add configurable pcw_chg_reg
On Thu, Apr 11, 2019 at 1:08 PM Guenter Roeck wrote:
>
> On Thu, Apr 11, 2019 at 10:35 AM Kees Cook wrote:
> >
> > On Thu, Apr 11, 2019 at 9:42 AM Guenter Roeck wrote:
> > >
> > > On Thu, Apr 11, 2019 at 9:19 AM Kees Cook wrote:
> > > >
> > > > On Thu, Mar 7, 2019 at 7:43 AM Dan Williams
> >
Quoting Nicolas Boichat (2019-03-08 06:46:01)
>
> > > +
> > > +#define GATE_AUDIO0(_id, _name, _parent, _shift) \
> > > + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
> > > + &mtk_clk_gate_ops_no_setclr)
>
> This macro (or variants that end up being
Quoting Weiyi Lu (2019-03-04 21:05:45)
> Add MT8183 clock support, include topckgen, apmixedsys,
> infracfg, mcucfg and subsystem clocks.
>
> Signed-off-by: Weiyi Lu
> ---
Applied to clk-next
Quoting Weiyi Lu (2019-03-04 21:05:46)
> From: James Liao
>
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are
Since commit title ("srcu: Allocate per-CPU data for DEFINE_SRCU() in
modules"), modules that call DEFINE_{STATIC,}SRCU will have a new array
of srcu_struct pointers, which is used by srcu code to initialize and
clean up these structures and save valuable per-cpu reserved space.
There is no reason
On 11/04/2019 21:36, Nathan Chancellor wrote:
> On Thu, Apr 11, 2019 at 09:20:56PM +0200, Daniel Lezcano wrote:
>> On 10/04/2019 22:07, Tony Lindgren wrote:
>>> Hi,
>>>
>>> * Daniel Lezcano [190410 17:02]:
can you ask for an acked-by before pulling a patch in your tree?
>>>
>>> I certainly do
Quoting Bjorn Andersson (2019-03-05 21:51:48)
> Add the clocks and resets need in order to control the Turing
> remoteproc.
>
> Signed-off-by: Bjorn Andersson
> ---
Applied to clk-next
Quoting Bjorn Andersson (2019-03-06 09:47:56)
> Add devicetree binding for the turing clock controller found in QCS404.
>
> Signed-off-by: Bjorn Andersson
> ---
Applied to clk-next
Quoting Bjorn Andersson (2019-03-06 09:47:57)
> Some clocks can only be turned on by resetting the block containing
> them, provide a clock type that allow us to reference these clocks and
> have the client drivers enable and "disable" them.
>
> Signed-off-by: Bjorn Andersson
> ---
Applied to cl
Quoting Bjorn Andersson (2019-03-06 09:47:58)
> The Turing Clock Controller provides resources related to running the
> Turing subsystem.
>
> PM runtime is used to ensure that the associated AHB clock is ticking
> while the clock framework is accessing the registers in the Turing clock
> controlle
On Thu, Apr 11, 2019 at 12:26 PM Eric Biggers wrote:
> Well, I guess I'll just add __GFP_COMP so I at least don't get spammed with
> useless bug reports.
Thanks, I appreciate it.
> But I don't think it's in any way acceptable to change the semantics of the
> kernel's page allocator but only unde
Quoting Bjorn Andersson (2019-03-06 09:47:58)
> +
> +static int turingcc_probe(struct platform_device *pdev)
> +{
> + int ret;
> +
> + pm_runtime_enable(&pdev->dev);
> + ret = pm_clk_create(&pdev->dev);
Neat solution. Thanks!
> + if (ret)
> + goto disable_pm_
Quoting Paul Cercueil (2019-03-19 07:05:36)
> Add clock for the USB Device Controller PHY.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
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