On Tue, 9 Apr 2019 11:22:52 +0800
Mason Yang wrote:
> Add a driver for Macronix NAND read retry and randomizer.
These are 2 orthogonal changes, and should thus bit split in 2 patches.
>
> Signed-off-by: Mason Yang
> ---
> drivers/mtd/nand/raw/nand_macronix.c | 169
> +++
On 09.04.19 04:44, Michael S. Tsirkin wrote:
> On Fri, Apr 05, 2019 at 05:09:45PM -0700, Alexander Duyck wrote:
>> In addition we will need some way to identify which pages have been
>> hinted on and which have not. The way I believe easiest to do this
>> would be to overload the PageType value so
> From: Joakim Zhang
> Sent: Tuesday, April 9, 2019 5:07 AM
> Hi Stefan,
>
> Thanks for your validation! Could you add your test tag if you can
> successfully validated?
Sure, no problem. Please note that I needed to replace "flexcan_read" and
"flexcan_write" with "priv->read" and "priv->write"
On Tue, Apr 9, 2019 at 2:17 PM Keerthy wrote:
>
>
>
> On 09/04/19 10:37 AM, Masahiro Yamada wrote:
> > On Tue, Apr 9, 2019 at 2:00 PM Keerthy wrote:
> >>
> >>
> >>
> >> On 08/04/19 9:48 PM, Tony Lindgren wrote:
> >>> Hi,
> >>>
> >>> * Masahiro Yamada [190408 07:56]:
> is only generated and
Hello,
syzbot found the following crash on:
HEAD commit:ac5b84a1 Add linux-next specific files for 20190408
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=10ae80b720
kernel config: https://syzkaller.appspot.com/x/.config?x=42a33a21877c9c95
dashboard
This series adds support for STMicroelectronics Multi-Function eXpander
(STMFX), used on some STM32 discovery and evaluation boards.
STMFX is an STM32L152 slave controller whose firmware embeds the following
features:
- I/O expander (16 GPIOs + 8 extra if the other features are not enabled),
- res
This patch adds support for STMicroelectronics Multi-Function eXpander
(STMFX) on stm32mp157c-ev1. It is connected on i2c2.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp157c-ev1.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157c
The joystick (B1) on stm32mp157c-ev1 uses gpios on STMFX gpio expander.
These gpios need a pin configuration (push-pull and bias-pull-down),
described under stmfx_pinctrl node.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp157c-ev1.dts | 44 +++
1 fi
This patch adds pinctrl/GPIO driver for STMicroelectronics
Multi-Function eXpander (STMFX) GPIO expander.
STMFX is an I2C slave controller, offering up to 24 GPIOs.
The driver relies on generic pin config interface to configure the GPIOs.
Signed-off-by: Amelie Delaunay
---
drivers/pinctrl/Kconfi
The joystick (B3) on stm32746g-eval uses gpios on STMFX gpio expander.
These gpios need a pin configuration (push-pull and bias-pull-up),
described under stmfx_pinctrl node.
Signed-off-by: Amelie Delaunay
Acked-by: Linus Walleij
---
arch/arm/boot/dts/stm32746g-eval.dts | 43
Orange (LD2) and blue (LD4) leds on stm32746g-eval are connected on
STMFX gpio expander, offset 17 and 19.
Signed-off-by: Amelie Delaunay
Acked-by: Linus Walleij
---
arch/arm/boot/dts/stm32746g-eval.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stm32746g-eval.d
This patch adds documentation of device tree bindings for the
STMicroelectronics Multi-Function eXpander (STMFX) MFD core.
Signed-off-by: Amelie Delaunay
Reviewed-by: Linus Walleij
Reviewed-by: Rob Herring
Acked-for-MFD-by: Lee Jones
---
Documentation/devicetree/bindings/mfd/stmfx.txt | 28 ++
STMicroelectronics Multi-Function eXpander (STMFX) is a slave controller
using I2C for communication with the main MCU. Main features are:
- 16 fast GPIOs individually configurable in input/output
- 8 alternate GPIOs individually configurable in input/output when other
STMFX functions are not used
This patch adds documentation of device tree bindings for the
STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander.
Signed-off-by: Amelie Delaunay
Reviewed-by: Linus Walleij
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pinctrl/pinctrl-stmfx.txt | 116 +
This patch adds support for STMicroelectronics Multi-Function eXpander
(STMFX) on stm32746g-eval. It is connected on i2c1.
Signed-off-by: Amelie Delaunay
Acked-by: Linus Walleij
---
arch/arm/boot/dts/stm32746g-eval.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/
On Mon, 8 Apr 2019, Sebastian Andrzej Siewior wrote:
> On 2019-04-08 19:05:56 [+0200], Thomas Gleixner wrote:
> > > diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c
> > > index a5b086ec426a5..f20e1d1fffa29 100644
> > > --- a/arch/x86/kernel/fpu/signal.c
> > > +++ b/arch/x86
On 4/8/19 3:29 PM, xiang xiao wrote:
> On Mon, Apr 8, 2019 at 8:05 PM Arnaud Pouliquen
> wrote:
>>
>>
>>
>> On 4/6/19 9:56 AM, xiang xiao wrote:
>>> On Sat, Apr 6, 2019 at 12:08 AM Arnaud Pouliquen
>>> wrote:
On 4/5/19 4:03 PM, xiang xiao wrote:
> On Fri, Apr 5, 2019 a
On 二, 2019-04-09 at 05:28 +, Anson Huang wrote:
> Ping...
> Can anyone provide some suggestion about how to proceed next?
>
Hi, Eduardo,
I guess you will comment on this patch, right?
Or else I will take the patch following Rob' suggestion.
thanks,
rui
> Best Regards!
> Anson Huang
>
> >
DPPA2(Data Path Acceleration Architecture 2) qDMA
The qDMA supports channel virtualization by allowing DMA jobs to be enqueued
into different frame queues. Core can initiate a DMA transaction by preparing
a frame descriptor(FD) for each DMA job and enqueuing this job to a frame queue.
through a har
The MC exports the DPDMAI object as an interface to operate the DPAA2 QDMA
Engine. The DPDMAI enables sending frame-based requests to QDMA and receiving
back confirmation response on transaction completion, utilizing the DPAA2 QBMan
infrastructure. DPDMAI object provides up to two priorities for pr
On 08.04.19 12:12, David Hildenbrand wrote:
> Only memory added via add_memory() and friends will need memory
> block devices - only memory to be used via the buddy and to be onlined/
> offlined by user space in memory block granularity.
>
> Move creation of memory block devices out of arch_add_me
On 2019-04-08 12:45:05 [-0700], Tejun Heo wrote:
> Hello,
Hi,
…
> This looks good from wq side. Peter, are you okay with routing this
> through the wq tree? If you wanna take it through the sched tree,
> please feel free to add
Thank you.
> Acked-by: Tejun Heo
>
> Thanks.
Sebastian
On Thu 2019-04-04 15:18:55, Josh Poimboeuf wrote:
> On Thu, Apr 04, 2019 at 08:44:11PM +0200, Miroslav Benes wrote:
> > GCC 9 introduces a new option, -flive-patching. It disables certain
> > optimizations which could make a compilation unsafe for later live
> > patching of the running kernel.
> >
> -Original Message-
> From: Andrew Morton
> Sent: Tuesday, April 09, 2019 1:52 AM
> To: Vadim Pasternak
> Cc: jacek.anaszew...@gmail.com; pa...@ucw.cz; linux-kernel@vger.kernel.org;
> linux-l...@vger.kernel.org; Ido Schimmel ; Andrey
> Ryabinin
> Subject: Re: [PATCH v1 bitops] bitops
On 08/04/2019 19:07, Guenter Roeck wrote:
> On Mon, Apr 08, 2019 at 04:49:02PM +0100, Marc Zyngier wrote:
>> Only arch_timer_read_counter will guarantee that workarounds are
>> applied. So let's use this one instead of arch_counter_get_cntvct.
>>
>> Signed-off-by: Marc Zyngier
>
> Reviewed-by: Gu
On Mon, Apr 08, 2019 at 02:09:01PM +0200, Ondřej Jirman wrote:
> Hello Maxime,
>
> On Mon, Apr 08, 2019 at 10:00:56AM +0200, Maxime Ripard wrote:
> > On Wed, Mar 27, 2019 at 03:33:38AM +0100, meg...@megous.com wrote:
> > > From: Ziping Chen
> > >
> > > Allwinner A83T SoC has a low res adc like the
On 08.04.2019 23:01, Hugh Dickins wrote:
The igrab() in shmem_unuse() looks good, but we forgot that it gives no
protection against concurrent unmounting: a point made by Konstantin
Khlebnikov eight years ago, and then fixed in 2.6.39 by 778dd893ae78
("tmpfs: fix race between umount and swapoff")
On Fri, Apr 5, 2019 at 4:12 PM Colin King wrote:
>
> From: Colin Ian King
>
> The pointer 'target' is not initialized and is only assigned when the
> ACPI_HMAT_MEMORY_PD_VALID bit in p->flags is set. There is a later null
> check on target that leads to an uninitialized pointer read and
> derefe
Hi Rob,
On 28/03/19 6:01 PM, Rob Herring wrote:
> On Tue, Mar 12, 2019 at 02:35:17PM +0530, Vignesh Raghavendra wrote:
>> Add dt bindings for TI syscon gate clock.
>>
>> Signed-off-by: Vignesh Raghavendra
>> ---
>> .../bindings/clock/ti,syscon-gate-clock.txt | 35 +++
>> 1 file
Dmitry V. Levin 於 2019年4月9日 週二 上午1:41寫道：
>
> All syscall_get_*() and syscall_set_*() functions must be defined
> as static inline as on all other architectures, otherwise asm/syscall.h
> cannot be included in more than one compilation unit.
>
> This bug has to be fixed in order to extend the gener
Hi all,
Changes since 20190408:
The mac80211-next tree gained a conflict against the mac80211 tree.
The drm tree still had its build failure for which I disabled a driver.
The drm-misc tree gained conflicts against the drm tree and also a build
failure for which I marked a driver as BROKEN.
Th
On 09/04/2019 00.52, Andrew Morton wrote:
> (resend, cc Andrey)
>
> On Sun, 7 Apr 2019 12:53:25 + Vadim Pasternak
> wrote:
>
>> The warning is caused by call to rorXX(), if the second parameters of
>> this function "shift" is zero. In such case UBSAN reports the warning
>> for the next exp
On Tue, Apr 09, 2019 at 12:13:58AM +0800, Frank Lee wrote:
> On Fri, Apr 5, 2019 at 10:55 PM Maxime Ripard
> wrote:
> >
> > Hi,
> >
> > On Fri, Apr 05, 2019 at 06:24:55AM -0400, Yangtao Li wrote:
> > > Allwinner Process Voltage Scaling Tables defines the voltage and
> > > frequency value based o
On Mon, Apr 08, 2019 at 12:45:05PM -0700, Tejun Heo wrote:
> Hello,
>
> On Wed, Mar 13, 2019 at 05:55:48PM +0100, Sebastian Andrzej Siewior wrote:
> > From: Thomas Gleixner
> >
> > The worker accounting for CPU bound workers is plugged into the core
> > scheduler code and the wakeup code. This i
On 01/04/2019 13:51, Neil Armstrong wrote:
> On 25/03/2019 11:03, Neil Armstrong wrote:
>> Add following peripherals :
>> - SAR-ADC
>> - USB
>> - Mali GPU
>>
>> Dependencies :
>> - ADC
>>
>> Depends on CLKID_AO_SAR_ADC_SEL, stable clk headers tags will be
>> available after v5.1-rc4
>>
>> Bindings
(+ LKML)
Apologies forgot to CC the list.
On 04/07/19 18:52, Qais Yousef wrote:
> Hi Steve, Peter
>
> I know the topic has sprung up in the past but I couldn't find anything that
> points into any conclusion.
>
> As far as I understand new TRACE_EVENTS() in the scheduler (and probably other
> s
On Sat, Apr 6, 2019 at 8:18 PM Qian Cai wrote:
>
> The commit 665ac7e92757 ("acpi/hmat: Register processor domain to its
> memory") introduced some memory leaks below due to it fails to release
> the heap memory in an error path, and then the stack __initdata memory
> which reference them get free
On Tue, Apr 09, 2019 at 08:07:49AM +0200, Thomas-Mich Richter wrote:
> On 4/8/19 11:50 AM, Peter Zijlstra wrote:
> > On Mon, Apr 08, 2019 at 10:22:29AM +0200, Peter Zijlstra wrote:
> >> On Mon, Apr 08, 2019 at 09:12:28AM +0200, Thomas-Mich Richter wrote:
> >
> >>> very good news, your fix ran over
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Tuesday 19 March 2019 19:46
> To: Dragan Cvetic
> Cc: gregkh ; Michal Simek ;
> Derek Kiernan ; Linux ARM
> ; Linux Kernel Mailing List
>
> Subject: Re: [PATCH 04/12] misc: xilinx_sdfec: Add open, close and ioct
On Mon, Apr 08, 2019 at 07:11:21PM +, Singh, Brijesh wrote:
> The following commit 0a9fe8ca844d ("x86/mm: Validate
> kernel_physical_mapping_init()
> PTE population") triggers the below warning in the SEV guest.
>
> WARNING: CPU: 0 PID: 0 at arch/x86/include/asm/pgalloc.h:87
> phys_pmd_init+
On Tue, Apr 9, 2019 at 4:28 PM Maxime Ripard wrote:
>
> On Tue, Apr 09, 2019 at 04:07:34PM +0800, Chen-Yu Tsai wrote:
> > On Tue, Apr 9, 2019 at 3:58 PM Maxime Ripard
> > wrote:
> > > On Tue, Apr 09, 2019 at 12:57:42AM +0800, Chen-Yu Tsai wrote:
> > > > From: Chen-Yu Tsai
> > > >
> > > > The A8
Stats is updated by each policy, using the lock by stat can
reduce the contention.
Signed-off-by: Kyle Lin
---
Changes in v2:
- Drop the comment of the lock.
drivers/cpufreq/cpufreq_stats.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/cpufreq/cpu
Hi, Uwe
Best Regards!
Anson Huang
> -Original Message-
> From: Uwe Kleine-König [mailto:u.kleine-koe...@pengutronix.de]
> Sent: 2019年4月9日 14:48
> To: Anson Huang
> Cc: thierry.red...@gmail.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker..
On Mon, Apr 08, 2019 at 11:50:31AM +0200, Peter Zijlstra wrote:
> On Mon, Apr 08, 2019 at 10:22:29AM +0200, Peter Zijlstra wrote:
> > On Mon, Apr 08, 2019 at 09:12:28AM +0200, Thomas-Mich Richter wrote:
>
> > > very good news, your fix ran over the weekend without any hit!!!
> > >
> > > Thanks ve
Hi Moritz,
Thanks for the quick response.
Please find my response inline
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Tuesday, April 9, 2019 12:04 PM
> To: Moritz Fischer ; Nava kishore Manne
>
> Cc: at...@kernel.org; robh...@kernel.org; mark.rutl...
On Tue, Apr 09, 2019 at 05:31:48AM +, Vaittinen, Matti wrote:
> On Mon, 2019-04-08 at 23:21 +0100, Russell King - ARM Linux admin
> wrote:
> > On Mon, Apr 08, 2019 at 10:00:02AM -0700, Stephen Boyd wrote:
> > > Quoting Matti Vaittinen (2019-04-08 03:49:41)
> > > > On Fri, Apr 05, 2019 at 01:37:
On 09/04/2019 10.08, Rasmus Villemoes wrote:
> one could do
>
> u32 ror32(u32 x, unsigned s)
> {
> return (x >> (s&31)) | (x << ((32-s)&31));
> }
>
> to make the shifts always well-defined and also work as expected for s
> >= 32... if only gcc recognized that the masking is redundant, so t
Linus Torvalds's on April 6, 2019 1:50 am:
> On Fri, Apr 5, 2019 at 4:01 AM Will Deacon wrote:
>>
>> mmiowb() is now implied by spin_unlock() on architectures that require
>> it, so there is no reason to call it from driver code. This patch was
>> generated using coccinelle:
>>
>> @mmiowb@
Hi.
On Mon, Apr 8, 2019 at 5:03 PM Wiebe, Wladislav (Nokia - DE/Ulm)
wrote:
>
> Hi!
>
> On 07.04.2019 11:04, Masahiro Yamada wrote:
> > (+CC Jonas Gorski)
> >
> >
> > On Tue, Mar 26, 2019 at 6:58 PM Wiebe, Wladislav (Nokia - DE/Ulm)
> > wrote:
> >>
> >> Commit ea837f1c0503 ("kbuild: make modpost
This patch adds stpmic1 support on stm32mp157c ed1 board.
The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10
regulators, 3 power switches, a watchdog and an input for a power on key.
The DMAs are disabled because the PMIC generates a very few traffic and
DMA channels may lack
Add support for STPMIC1 on:
- stm32mp157c ed1 board
- stm32mp157a dk1 board
- arm multi_v7_defconfig
Pascal Paillet (3):
changes in v2:
* Describe why we disable the DMAs for PMIC
ARM: dts: stm32: add stpmic1 support on stm32mp157c ed1 board
ARM: dts: stm32: add stpmic1 support on stm32mp157
STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10
regulators, 3 power switches, a watchdog and an input for a power on key.
Signed-off-by: Pascal Paillet
---
arch/arm/configs/multi_v7_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/configs/multi_v7_d
This patch adds stpmic1 support on stm32mp157a dk1 board.
The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10
regulators, 3 power switches, a watchdog and an input for a power on key.
The DMAs are disabled because the PMIC generates a very few traffic and
DMA channels may lack
There was a missing comparison with 0 when checking if type is "s64" or
"u64". Therefore, the body of the if-statement was entered if "type" was
"u64" or not "s64", which made the first strcmp() redundant since if
type is "u64", it's not "s64".
If type is "s64", the body of the if-statement is not
On Mon, Apr 08, 2019 at 12:12:26PM +0200, David Hildenbrand wrote:
> Let's factor out removing of memory block devices, which is only
> necessary for memory added via add_memory() and friends that created
> memory block devices. Remove the devices before calling
> arch_remove_memory().
>
> TODO: W
On 09/04/2019 10:46, Jerome Brunet wrote:
> On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote:
>> While switching to the Common Clock Framework is still Work In Progress,
>> this patch adds the corresponding G12A HDMI PLL setup to be on-par
>> with the other SoCs support.
>>
>> The G12A has o
> With that said I have a few ideas that may help to address the 4
> issues called out above. The basic idea is simple. We use a high water
> mark based on zone->free_area[order].nr_free to determine when to wake
> up a thread to start hinting memory out of a given free area. From
> there we alloca
Thomas Gleixner's on April 6, 2019 3:54 am:
> On Fri, 5 Apr 2019, Nicholas Piggin wrote:
>> Thomas Gleixner's on April 5, 2019 12:36 am:
>> > On Thu, 4 Apr 2019, Nicholas Piggin wrote:
>> >
>> >> I've been looking at ways to fix suspend breakage with CPU0 as a
>> >> nohz CPU. I started looking at
On 04-04-19, 07:09, Niklas Cassel wrote:
> Add qcom-opp bindings with properties needed for Core Power Reduction (CPR).
>
> CPR is included in a great variety of Qualcomm SoC, e.g. msm8916 and msm8996,
> and was first introduced in msm8974.
>
> Co-developed-by: Jorge Ramirez-Ortiz
> Signed-off-b
On 09.04.19 11:18, Oscar Salvador wrote:
> On Mon, Apr 08, 2019 at 12:12:26PM +0200, David Hildenbrand wrote:
>> Let's factor out removing of memory block devices, which is only
>> necessary for memory added via add_memory() and friends that created
>> memory block devices. Remove the devices befor
On 09-04-19, 16:43, Kyle Lin wrote:
> Stats is updated by each policy, using the lock by stat can
> reduce the contention.
>
> Signed-off-by: Kyle Lin
> ---
> Changes in v2:
> - Drop the comment of the lock.
>
> drivers/cpufreq/cpufreq_stats.c | 15 ---
> 1 file changed, 8 inserti
Kees Cook wrote:
> These look good to me. Gets us another step to finishing this. :)
Can we fix the compiler, please, to say that *every* case (perhaps barring the
last) is expected to fall through?
David
Hello,
On Tue, Apr 09, 2019 at 08:51:48AM +, Anson Huang wrote:
> > On Tue, Mar 26, 2019 at 06:52:33AM +, Anson Huang wrote:
> > > + /* get polarity */
> > > + if (chan) {
> > > + state->polarity = chan->polarity;
> > > + } else {
> > > + /* in case no c
On 09/04/2019 11:15, Oleksandr Andrushchenko wrote:
> From: Oleksandr Andrushchenko
>
> This is the ABI for the two halves of a para-virtualized
> camera driver which extends Xen's reach multimedia capabilities even
> further enabling it for video conferencing, In-Vehicle Infotainment,
> high def
On Tue, Apr 09, 2019 at 02:23:53PM +1000, Michael Ellerman wrote:
> I'd much rather we use a trap with a specific immediate value. Otherwise
> someone's going to waste time one day puzzling over why userspace is
> doing mtmsr.
It's data. We have other data in executable sections. Anyone who
wond
--
Dear Friend (Assalamu Alaikum),
I came across your e-mail contact prior a private search while in need of
your assistance. My name is Aisha Al-Qaddafi a single Mother and a Widow
with three Children. I am the only biological Daughter of late Libyan
President (Late Colonel Muammar Gaddafi).
I
The QEMU powerpc/pseries machine model was not expecting a self-IPI,
and it may be a bit surprising thing to do, so have irq_work_queue_on
do local queueing when target is the current CPU.
Reported-by: Sebastian Andrzej Siewior
Tested-by: Sebastian Andrzej Siewior
Suggested-by: Steven Rostedt
A
Gustavo A. R. Silva wrote:
Please fix the compiler so that you can annotate a switch-statement to say
that every case must fall through (except, perhaps, the last).
> /* extract the FID array and its count in two steps */
> + /* fall through */
> case 1:
Capitial
On Tue, Apr 09, 2019 at 10:40:31AM +0200, Peter Zijlstra wrote:
> On Mon, Apr 08, 2019 at 07:11:21PM +, Singh, Brijesh wrote:
> > The following commit 0a9fe8ca844d ("x86/mm: Validate
> > kernel_physical_mapping_init()
> > PTE population") triggers the below warning in the SEV guest.
> >
> > W
On Sun, 2019-03-10 at 19:15 +0800, Nicolas Boichat wrote:
> On Thu, Mar 7, 2019 at 9:45 AM Long Cheng wrote:
> >
> > In DMA engine framework, add 8250 uart dma to support MediaTek uart.
> > If MediaTek uart enabled(SERIAL_8250_MT6577), and want to improve
> > the performance, can enable the functi
Hello, Roman.
>
> Reviewed-by: Roman Gushchin
>
> Thanks!
I appreciate your effort in reviewing to make it better.
Thank you!
--
Uladzislau Rezki
On Tue, 9 Apr 2019 17:35:39 +0800
masonccy...@mxic.com.tw wrote:
> > > +
> > > +static const struct kobj_attribute sysfs_mxic_nand =
> > > + __ATTR(nand_random, S_IRUGO | S_IWUSR,
> > > + mxic_nand_rand_type_show,
> > > + mxic_nand_rand_type_store);
> >
> > No, we don't want
On 09/04/2019 11:33, Oleksandr Andrushchenko wrote:
> On 4/9/19 12:28 PM, Juergen Gross wrote:
>> On 09/04/2019 11:15, Oleksandr Andrushchenko wrote:
>>> From: Oleksandr Andrushchenko
>>>
>>> This is the ABI for the two halves of a para-virtualized
>>> camera driver which extends Xen's reach multi
Hi!
> (resend, cc Andrey)
>
> On Sun, 7 Apr 2019 12:53:25 + Vadim Pasternak
> wrote:
>
> > The warning is caused by call to rorXX(), if the second parameters of
> > this function "shift" is zero. In such case UBSAN reports the warning
> > for the next expression: (word << (XX - shift), wh
On Tue, 9 Apr 2019 13:53:32 +0900
Masahiro Yamada wrote:
> Currently, drivers are able to constify a nand_op_parser array,
> but not nand_op_parser_pattern and nand_op_parser_pattern_elem
> since they are instantiated by using the NAND_OP_PARSER(_PATTERN).
>
> Add 'const' to them in order to mo
On 08.04.19 23:26, Arnd Bergmann wrote:
> The 'func_code' variable gets printed in debug statements without
> a prior initialization in multiple functions, as reported when building
> with clang:
>
> drivers/s390/crypto/zcrypt_api.c:659:6: warning: variable 'func_code' is used
> uninitialized when
> The EC is in charge of controlling the keyboard backlight on
> the Wilco platform. We expose a standard LED class device at
> /sys/class/leds/chromeos::kbd_backlight. This driver is modeled
As discussed, please use platform::.
Pave
Hi,
Kindly pull the new firmware from the following URL:
git://git.chelsio.net/pub/git/linux-firmware.git for-upstream
Thanks,
Vishal
The following changes since commit 67b75798ea88f4b1d6ee6a3b5a0634d29620c094:
linux-firmware: add firmware for MT7615E (2019-04-02 08:00:12 -0400)
are availabl
Arnaldo reported assertion in perf stat record:
assertion failed at util/header.c:875
There's no support for this in perf state record
command, disabling the feature.
Reported-by: Arnaldo Carvalho de Melo
Link: http://lkml.kernel.org/n/tip-2uhyh815jfwikg5uhve8l...@git.kernel.org
Signed-off-by
Failing while removing memory is mostly ignored and cannot really be
handled. Let's treat errors in unregister_memory_section() in a nice
way, warning, but continuing.
Cc: Greg Kroah-Hartman
Cc: "Rafael J. Wysocki"
Cc: Ingo Molnar
Cc: Andrew Banman
Cc: "mike.tra...@hpe.com"
Cc: David Hildenbr
Error handling when removing memory is somewhat messed up right now. Some
errors result in warnings, others are completely ignored. Memory unplug
code can essentially not deal with errors properly as of now.
remove_memory() will never fail.
We have basically two choices:
1. Allow arch_remov_memory
__add_pages() doesn't add the memory resource, so __remove_pages()
shouldn't remove it. Let's factor it out. Especially as it is a special
case for memory used as system memory, added via add_memory() and
friends.
We now remove the resource after removing the sections instead of doing
it the other
Let's just warn in case a section is not valid instead of failing to
remove somewhere in the middle of the process, returning an error that
will be mostly ignored by callers.
Cc: Andrew Morton
Cc: Oscar Salvador
Cc: Michal Hocko
Cc: David Hildenbrand
Cc: Pavel Tatashin
Cc: Qian Cai
Cc: Wei Y
All callers of arch_remove_memory() ignore errors. And we should really
try to remove any errors from the memory removal path.
No more errors are reported from __remove_pages(). BUG() in s390x code
in case arch_remove_memory() is triggered. We may implement that properly
later. WARN in case powerpc
Add char device interface per DT node present and support
file operations:
- open(),
- close(),
- unlocked_ioctl(),
- compat_ioctl().
Tested-by: Dragan Cvetic
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
drivers/misc/xilinx_sdfec.c | 78 +++
Implements an platform driver that matches with xlnx,
sd-fec-1.1 device tree node and registers as a character
device, including:
- SD-FEC driver binds to sdfec DT node.
- creates and initialise an initial driver dev structure.
- add the driver in Linux build and Kconfig.
Tested-by: Dragan Cvetic
On 05-04-19, 06:24, Yangtao Li wrote:
> +++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> +
SD-FEC statistic data are:
- count of data interface errors (isr_err_count)
- count of Correctable ECC errors (cecc_count)
- count of Uncorrectable ECC errors (uecc_count)
Add support:
1. clear stats ioctl callback which clears collected
statistic data,
2. get stats ioctl callback which reads a co
Add SD-FEC driver documentation.
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
Documentation/misc-devices/index.rst| 1 +
Documentation/misc-devices/xilinx_sdfec.rst | 291
2 files changed, 292 insertions(+)
create mode 100644 Documentatio
Stores configuration based on parameters from the DT
node and values from the SD-FEC core plus reads
the default state from the SD-FEC core. To obtain
values from the core register read, write capabilities
have been added plus related register map details.
Tested-by: Dragan Cvetic
Signed-off-by:
Add the capability to configure LDPC mode via the ioctl
XSDFEC_ADD_LDPC_CODE_PARAMS.
Tested-by: Dragan Cvetic
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
drivers/misc/xilinx_sdfec.c | 333 +++
include/uapi/misc/xilinx_sdfec.h | 119 +++
- Add capability to get SD-FEC config data using ioctl
XSDFEC_GET_CONFIG.
- Add capability to set SD-FEC data order using ioctl
SDFEC_SET_ORDER.
- Add capability to set SD-FEC bypass option using ioctl
XSDFEC_SET_BYPASS.
- Add capability to set SD-FEC active state using ioctl
XSDFEC_IS_ACTIVE.
support
Add maintainer entry for Xilinx SD-FEC driver support.
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
MAINTAINERS | 12
1 file changed, 12 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 43b36db..da8f21a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
Support monitoring and detecting the SD-FEC error events
through IRQ and poll file operation.
The SD-FEC device can detect one-error or multi-error events.
An error triggers an interrupt which creates and run the ONE_SHOT
IRQ thread.
The ONE_SHOT IRQ thread detects type of error and pass that
info
mode
Add the capability to configure and retrieve turbo mode
via the ioctls XSDFEC_SET_TURBO and XSDFEC_GET_TURBO.
Tested-by: Dragan Cvetic
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
drivers/misc/xilinx_sdfec.c | 77
include/uap
Add the Soft Decision Forward Error Correction (SDFEC) Engine
bindings which is available for the Zynq UltraScale+ RFSoC
FPGA's.
Signed-off-by: Dragan Cvetic
Signed-off-by: Derek Kiernan
---
.../devicetree/bindings/misc/xlnx,sd-fec.txt | 58 ++
1 file changed, 58 inser
This patchset is adding the full Soft Decision Forward Error
Correction (SD-FEC) driver implementation, driver DT binding and
driver documentation.
Forward Error Correction (FEC) codes such as Low Density Parity
Check (LDPC) and turbo codes provide a means to control errors in
data transmissions o
Add the support for Linux Clock Control Framework (CCF).
Registers and enables clocks with the Clock Control
Framework (CCF), to prevent shared clocks from been
disabled.
Tested-by: Dragan Cvetic
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
drivers/misc/xilinx_sdfec.c | 154 ++
On Tue, Apr 9, 2019 at 11:54 AM Harald Freudenberger
wrote:
> On 08.04.19 23:26, Arnd Bergmann wrote:
> Thanks Arnd, but as Nathan already wrote, I'd prefer to have the
> variable initialized with 0 instead of -1.
> If you agree with this, I'll rewrite the patch and apply it to our
> internal git
On Tue, Apr 9, 2019 at 3:28 PM Arnaud Pouliquen wrote:
>
>
>
> On 4/8/19 3:29 PM, xiang xiao wrote:
> > On Mon, Apr 8, 2019 at 8:05 PM Arnaud Pouliquen
> > wrote:
> >>
> >>
> >>
> >> On 4/6/19 9:56 AM, xiang xiao wrote:
> >>> On Sat, Apr 6, 2019 at 12:08 AM Arnaud Pouliquen
> >>> wrote:
>
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