Hi, Dmitry
Best Regards!
Anson Huang
> -Original Message-
> From: dmitry.torok...@gmail.com [mailto:dmitry.torok...@gmail.com]
> Sent: 2019年3月27日 12:29
> To: Anson Huang
> Cc: Fabio Estevam ; linux-in...@vger.kernel.org;
> linux-kernel@vger.kernel.org; dl-linux-imx
> Subject: Re: [PATCH
On Tue, Mar 26, 2019 at 09:29:14PM -0700, Andy Lutomirski wrote:
> On Tue, Mar 26, 2019 at 5:31 PM Greg KH wrote:
> >
> > On Tue, Mar 26, 2019 at 12:20:24PM -0700, Andy Lutomirski wrote:
> > > On Tue, Mar 26, 2019 at 11:28 AM Matthew Garrett
> > > wrote:
> > > >
> > > > From: Matthew Garrett
> >
On Wed, Mar 27, 2019 at 09:36:06AM +0530, Naresh Kamboju wrote:
> On Tue, 26 Mar 2019 at 12:09, Greg Kroah-Hartman
> wrote:
> >
> > This is the start of the stable review cycle for the 5.0.5 release.
> > There are 52 patches in this series, all will be posted as a response
> > to this one. If any
From: Erin Lo
Add memory table mapping API for other driver to lookup
reserved physical and virtual memory
Signed-off-by: Erin Lo
Signed-off-by: Pi-Hsun Shih
---
Changes from v6:
- No change.
Changes from v5:
- No change.
Changes from v4:
- New patch.
---
drivers/remoteproc/mtk_scp.c
From: Erin Lo
Provide a basic driver to control Cortex M4 co-processor
Signed-off-by: Erin Lo
Signed-off-by: Nicolas Boichat
Signed-off-by: Pi-Hsun Shih
---
Changes from v6:
- No change.
Changes from v5:
- Changed some space to tab.
Changes from v4:
- Rename most function from mtk_scp_*
From: Pi-Hsun Shih
Add EC host command support through rpmsg.
Signed-off-by: Pi-Hsun Shih
---
Changes from v6:
- Make data for response aligned to 4 bytes.
Changes from v5:
- Change commit title.
- Add documents for some structs, and fix all warning from
scripts/kernel-doc.
- Miscellane
From: Pi-Hsun Shih
Add a simple rpmsg support for mt8183 SCP, that use IPI / IPC directly.
Signed-off-by: Pi-Hsun Shih
---
Changes from v6:
- Decouple mtk_rpmsg from mtk_scp by putting all necessary informations
(name service IPI id, register/unregister/send functions) into a
struct, and
From: Erin Lo
Add a DT binding documentation of SCP for the
MT8183 SoC from Mediatek.
Signed-off-by: Erin Lo
Signed-off-by: Pi-Hsun Shih
Reviewed-by: Rob Herring
---
Changes from v6:
- No change.
Changes from v5:
- Remove dependency on CONFIG_RPMSG_MTK_SCP.
Changes from v4:
- Add detail
From: Pi-Hsun Shih
Since a SCP and EC would both exist on a system, and use the cros_ec_dev
driver, we need to differentiate between them for the userspace, or they
would both be registered at /dev/cros_ec, causing a conflict.
Signed-off-by: Pi-Hsun Shih
---
Changes from v6:
- No change.
Chan
From: Pi-Hsun Shih
Add a DT binding documentation for ChromeOS EC driver over rpmsg.
Signed-off-by: Pi-Hsun Shih
---
Changes from v6:
- No change.
Changes from v5:
- New patch.
---
Documentation/devicetree/bindings/mfd/cros-ec.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
d
Zdravstvujte Vas interesuyut klientskie bazy dannyh?
Print out the page migratetype name which is more readable.
Signed-off-by: Huang Shijie
---
include/trace/events/page_ref.h | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/include/trace/events/page_ref.h b/include/trace/events/page_ref.h
index 5d2ea93956ce..94df979
On Mon, Mar 25, 2019 at 05:58:36PM -0500, Scott Wood wrote:
> On Mon, 2019-03-25 at 17:53 -0500, Scott Wood wrote:
> > On Mon, 2019-03-25 at 11:07 +0800, Wu Hao wrote:
> > > In early partial reconfiguration private feature, it only
> > > supports 32bit data width when writing data to hardware for
>
> On Mar 26, 2019, at 10:06 PM, Greg KH wrote:
>
>> On Tue, Mar 26, 2019 at 09:29:14PM -0700, Andy Lutomirski wrote:
>>> On Tue, Mar 26, 2019 at 5:31 PM Greg KH wrote:
>>>
On Tue, Mar 26, 2019 at 12:20:24PM -0700, Andy Lutomirski wrote:
On Tue, Mar 26, 2019 at 11:28 AM Matthew Garr
On Tue, Mar 26, 2019 at 10:29:41PM -0700, Andy Lutomirski wrote:
>
>
> > On Mar 26, 2019, at 10:06 PM, Greg KH wrote:
> >
> >> On Tue, Mar 26, 2019 at 09:29:14PM -0700, Andy Lutomirski wrote:
> >>> On Tue, Mar 26, 2019 at 5:31 PM Greg KH
> >>> wrote:
> >>>
> On Tue, Mar 26, 2019 at 12:2
Fixes: Use PIO bit in SPI_COMMAND1 register for PIO mode.
Current driver uses DMA_EN instead of PIO bit.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra1
Fixes: Clear packed bit when not using packed mode.
Packed bit is not cleared when not using packed mode. This results
in transfer timeouts for the unpacked mode transfers followed by the
packed mode transfers.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 2 ++
1 file cha
Fixes: Use packed mode for 32 bits per word transfers to increase
performance as each packet is a full 32-bit word.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-t
Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels
to avoid mismatch.
SPI FIFO trigger levels are calculated based on the transfer length.
So this patch moves DMA slave configuration to happen before start
of DMAs.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra
Fixes: Flush TX and RX FIFOs before start of new transfer and on FIFO
overflow or underrun errors.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 39 ++-
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-tegra1
This patch sets the SPI device id from the device tree as the
bus number.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 94acef0f5ea5..9b9d4b9e1f3e 100644
---
This patch adds support for dual mode SPI transfer.
Dual mode uses both MOSI and MISO lines in parallel where the data
is interleaved on MOSI and MISO lines increasing the throughput.
Packet from Tx FIFO is transmitted on both MOSI and MISO lines and
packet to Rx FIFO is received from both MOSI a
This patch adds support for HW based CS control.
Tegra SPI controller supports both HW and SW based CS control
transfers.
Tegra SPI driver default uses SW CS control for transfers and HW CS
control can be enabled through SPI client device node DT property
nvidia,enable-hw-based-cs and is used onl
Tegra SPI supports 4 through 32 bits per word.
This patch sets bits_per_word_mask accordingly to support transfer
with these bits per word.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/
Tegra SPI controller has TX_CLK_TAP_DELAY and RX_CLK_TAP_DELAY in
COMMAND2 register to tune delay of the clock going out to external
device during transmit and also for the clock coming in from external
device during receive.
TX/RX clock tap delays may vary based on the trace lengths of the
platfo
mode and mode_bits is declared as u16 and all bits are used.
This patch changes mode and mode_bits to be u32 to allow for more mode
configurations.
Some SPI Master controllers support configuring Least significant byte
first or Most significant byte first order for transfers. Also some SPI
slave
With SW CS, during transfer completion CS is de-asserted by writing the
default command1 register value to SPI_COMMAND1 register. With this both
mode and CS state are set at the same time and if current transfer mode
is different to default SPI mode and if mode change happens prior to CS
de-assert,
This patch adds supports for chip select control using GPIO if valid
CS gpio exists rather than controlling from the SPI controller.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 57 ++
1 file changed, 57 insertions(+)
diff --git
Some SPI devices expects SPI transfers to be in Least significant byte
first order and some devices expect Most significant byte first order.
This patch adds SPI_LSBYTE_FIRST to supported mode list and implements
configuration accordingly.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-
Some slaves may need certain CS setup time, hold time, CS inactive
delay between the packets. Tegra SPI controller supports configuring
these CS timing parameters and are applicable when using HW CS.
This patch adds support for configuring these HW CS timing parameters
through device tree properti
This patch adds Tegra SPI master tx and rx clock delay properties.
TX/RX clock delays may vary depending on the platform design trace lengths
for each client on the Tegra SPI bus. These properties helps to tune the
clock delays.
Signed-off-by: Sowjanya Komatineni
---
.../devicetree/bindings/spi
This patch adds below cs timing properties to allow SPI master configuring
setup, hold and time interval between two SPI transactions to meet specific
SPI client device requirements.
CS setup time
CS hold time
CS inactive delay
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com;
This patch creates tegra_spi_soc_data structure to maintain and implement
SPI HW feature differences between different Tegra chips and also creates
a separate compatible string for T124/T210/T186.
Tegra210 and later has a separate interrupt mask register SPI_INTR_MASK
for enabling or disabling int
This patch adds 3 wire transfer support to SPI mode list and also
implements it.
3 wire or Bi-directional mode uses only one serial data pin for
the transfer. SPI in master mode uses MOSI data line only and MISO
data line is not used by the SPI.
Signed-off-by: Sowjanya Komatineni
---
drivers/sp
Tegra SPI controller supports lsb first mode. Default is MSB bit first
and on selection of SPI_LSB_FIRST through SPI mode transmission happens
with LSB bit first.
This patch adds SPI_LSB_FIRST flag to mode_bits and also configures it
on request.
Signed-off-by: Sowjanya Komatineni
---
drivers/sp
This patch dumps SPI registers on DMA or transfer timeout for debug
purpose.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index b7e71676a506..268a7
Fixes: use unpacked mode when transfer length is less than 4 bytes.
Packed mode expects minimum transfer length of 4 bytes.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-tegra114.c b/driver
Fixes: SPI driver can be built as module so perform SPI controller reset
on probe to make sure it is in valid state before initiating transfer.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(
Fixes: terminate DMA and perform controller reset on transfer timeout
to clear the FIFO's and errors.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 71658
Fixes: move SPI controller reset out of spin lock.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/spi-tegra114.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 268a790a663e..5523936b21f5 100644
--- a/
Fixes: computation of actual bytes to fill/receive in/from FIFO in unpacked
mode when transfer length is not a multiple of requested bits per word.
unpacked mode transfers fails when the transfer includes partial bytes in
the last word.
Total words to be written/read to/from FIFO is computed base
On Mon, Mar 25, 2019 at 05:53:50PM -0500, Scott Wood wrote:
> On Mon, 2019-03-25 at 11:07 +0800, Wu Hao wrote:
> > @@ -200,21 +228,32 @@ static int fme_mgr_write(struct fpga_manager *mgr,
> > pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT,
> > pr_status);
> > }
> >
> >
SNVS IRQ is requested before necessary driver data initialized,
if there is a pending IRQ during driver probe phase, kernel
NULL pointer panic will occur in IRQ handler. To avoid such
scenario, just initialize necessary driver data before enabling
IRQ. This patch is inspired by NXP's internal kerne
With calling dev_pm_set_wake_irq() to set SNVS ON/OFF button
as wakeup source for suspend, generic wake irq mechanism
will automatically enable it as wakeup source when suspend,
then the enable_irq_wake()/disable_irq_wake() can be removed
in suspend/resume callback, it simplifies the code.
Signed-
On Wed, 2019-03-27 at 12:37 +0800, Wu Hao wrote:
> On Tue, Mar 26, 2019 at 04:22:34PM -0500, Scott Wood wrote:
> > On Tue, 2019-03-26 at 14:33 -0500, Alan Tull wrote:
> > > On Mon, Mar 25, 2019 at 5:58 PM Scott Wood wrote:
> > > > >
> > > Hi Scott,
> > >
> > > > On Mon, 2019-03-25 at 17:53 -0500
With calling dev_pm_set_wake_irq() to set SNVS RTC as wakeup
source for suspend, generic wake irq mechanism will automatically
enable it as wakeup source when suspend, then the suspend/resume
callback which are ONLY for enabling/disabling irq wake can be
removed, it simplifies the code.
Signed-off
On Wed, Mar 27, 2019 at 01:10:31AM -0500, Scott Wood wrote:
> On Wed, 2019-03-27 at 12:37 +0800, Wu Hao wrote:
> > On Tue, Mar 26, 2019 at 04:22:34PM -0500, Scott Wood wrote:
> > > On Tue, 2019-03-26 at 14:33 -0500, Alan Tull wrote:
> > > > On Mon, Mar 25, 2019 at 5:58 PM Scott Wood wrote:
> > > >
On Wed, 2019-03-27 at 13:10 +0800, Wu Hao wrote:
> On Mon, Mar 25, 2019 at 05:58:36PM -0500, Scott Wood wrote:
> > On Mon, 2019-03-25 at 17:53 -0500, Scott Wood wrote:
> > > On Mon, 2019-03-25 at 11:07 +0800, Wu Hao wrote:
> > > > In early partial reconfiguration private feature, it only
> > > > su
From: Yongqiang Niu
Here is two modifition in this patch:
1.bls->dpi0 and rdma1->dsi are differen usecase,
Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase
2.remove DISP_REG_CONFIG_DPI_SEL setting, DPI_SEL_IN_BLS is 0 and
this is same with hardware defautl setting,
Signed-off-by: Yongqi
From: Yongqiang Niu
This patch add commponent OVL0_2L
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/g
Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX6SX_CLK_SDMA result in driver incorrectly thinking that
ratio is 1:1 which res
Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX7D_CLK_SDMA result in driver incorrectly thinking that
ratio is 1:1 which resu
Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX6QDL_CLK_SDMA result in driver incorrectly thinking that
ratio is 1:1 which re
On Tue, Mar 26, 2019 at 11:55:07PM +0530, Anirudh Rayabharam wrote:
> Shorten the expression by re-using the part that was already computed to
This confused me. Better to phrase it like:
Shorten the expression by using the "psecuritypriv" pointer.
> fix the line over 80 characters warning repor
i.MX7D comes with 4 viewports, so configure PCIE node accordingly so
that the driver won't assume we only have 2.
Signed-off-by: Andrey Smirnov
Cc: Richard Zhu
Cc: Chris Healy
Cc: Lucas Stach
Cc: Fabio Estevam
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch
i.MX6 comes with 4 viewports, so configure PCIE node accordingly so
that the driver won't assume we only have 2.
Signed-off-by: Andrey Smirnov
Cc: Richard Zhu
Cc: Chris Healy
Cc: Lucas Stach
Cc: Fabio Estevam
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/
Add support for ZII's i.MX7 based Remote Peripheral Unit 2 (RPU2)
board.
Signed-off-by: Andrey Smirnov
Cc: Shawn Guo
Cc: Chris Healy
Cc: Andrew Lunn
Cc: Fabio Estevam
Cc: Rob Herring
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/Makefile |
Add support for ZII i.MX7 RPU2 board.
Signed-off-by: Andrey Smirnov
Cc: Shawn Guo
Cc: Chris Healy
Cc: Andrew Lunn
Cc: Fabio Estevam
Cc: Rob Herring
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 ins
On Wed, Mar 27, 2019 at 01:58:45PM +0900, William Breathitt Gray wrote:
> This macro iterates for each 8-bit group of bits (clump) with set bits,
> within a bitmap memory region. For each iteration, "start" is set to the
> bit offset of the found clump, while the respective clump value is
> stored
Fix error bit operation in watchdog_start()
Fixes: 14b24a88a3660 ("watchdog: f71808e_wdt: Add F81866 support")
Signed-off-by: Ji-Ze Hong (Peter Hong)
---
drivers/watchdog/f71808e_wdt.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/watchdog/f71808e_wdt
Separate declaration and assignment in watchdog_start()
Signed-off-by: Ji-Ze Hong (Peter Hong)
---
drivers/watchdog/f71808e_wdt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/f71808e_wdt.c b/drivers/watchdog/f71808e_wdt.c
index 9a1c761258ce..bd2ced9f39f
On Tue, 2019-03-26 at 23:23 +, Kirill Smelkov wrote:
> Using scripts/coccinelle/api/stream_open.cocci added in the previous
> patch, search and convert to stream_open all in-kernel nonseekable_open
> users for which read and write actually do not depend on ppos and where
> there is no other met
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