mode and mode_bits is declared as u16 and all bits are used.
This patch changes mode and mode_bits to be u32 to allow for more mode
configurations.
Some SPI Master controllers support configuring Least significant byte
first or Most significant byte first order for transfers. Also some SPI
slave devices expect bytes to be in Least significant first order and
some devices expect Most significant first order.
This patch creates SPI_LSBYTE_FIRST mode for this purpose.
Signed-off-by: Sowjanya Komatineni <skomatin...@nvidia.com>
---
include/linux/spi/spi.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index a0975cf76cf6..0032aa47dea0 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -143,7 +143,7 @@ struct spi_device {
u32 max_speed_hz;
u8 chip_select;
u8 bits_per_word;
- u16 mode;
+ u32 mode;
#define SPI_CPHA 0x01 /* clock phase */
#define SPI_CPOL 0x02 /* clock polarity */
#define SPI_MODE_0 (0|0) /* (original MicroWire)
*/
@@ -164,6 +164,7 @@ struct spi_device {
#define SPI_TX_OCTAL 0x2000 /* transmit with 8
wires */
#define SPI_RX_OCTAL 0x4000 /* receive with 8 wires
*/
#define SPI_3WIRE_HIZ 0x8000 /* high impedance
turnaround */
+#define SPI_LSBYTE_FIRST 0x10000 /* per-word bytes-on-wire */
int irq;
void *controller_state;
void *controller_data;
@@ -439,7 +440,7 @@ struct spi_controller {
u16 dma_alignment;
/* spi_device.mode flags understood by this controller driver */
- u16 mode_bits;
+ u32 mode_bits;
/* bitmask of supported bits_per_word for transfers */
u32 bits_per_word_mask;
--
2.7.4
