There is a potential NULL pointer dereference in case kzalloc()
fails and returns NULL.
Fixes: 4bba66899ac6 ("irqchip/tango: Add support for Sigma Designs
SMP86xx/SMP87xx interrupt controller")
Signed-off-by: YueHaibing
---
drivers/irqchip/irq-tango.c | 2 ++
1 file changed, 2 insertions(+)
di
Since commit 1c459de1e645 ("ARM: pxa: ssp: use devm_ functions")
kfree, iounmap, clk_put etc no need do any more in remove path.
Fixes: 1c459de1e645 ("ARM: pxa: ssp: use devm_ functions")
Signed-off-by: YueHaibing
---
arch/arm/plat-pxa/ssp.c | 9 -
1 file changed, 9 deletions(-)
diff --
Hi,
On 2019/1/29 2:30, Dan Carpenter wrote:
> Are you serious? The standard fault injection doesn't do that???
>
> Please fix it instead of creating a duplicate better implementation
> which only your filesystem can use. I would have thought that obviously
> any fault injection framework could
The Spreadtrum DMA engine uses the link-list mode to support audio playback
or capture, thus this patch adds audio DMA platform support for CPU DAI to
trigger DMA link-list transfer.
Signed-off-by: Baolin Wang
---
sound/soc/Kconfig |1 +
sound/soc/Makefile|1 +
so
Add documentation for Spreadtrum DMA platform driver.
Signed-off-by: Baolin Wang
---
.../devicetree/bindings/sound/sprd-pcm.txt | 23
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/sprd-pcm.txt
diff --git a/Documentati
From: Hou Zhiqiang
This patch set is aim to refactor the Mobiveil driver and add
PCIe support for NXP Layerscape series SoCs integrated Mobiveil's
PCIe Gen4 controller.
Hou Zhiqiang (27):
PCI: mobiveil: uniform the register accessors
PCI: mobiveil: format the code without function change
P
From: Hou Zhiqiang
As it won't delete any node in this iteration, replaced
the function resource_list_for_each_entry_safe() with
the resource_list_for_each_entry().
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/pcie-mobiveil.c | 4 ++--
1
From: Hou Zhiqiang
It should get PCI base address from the DT node property 'ranges'
to setup MEM/IO outbound windows instead of always zero.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge
IP driver")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No chan
From: Hou Zhiqiang
Just format the code without functionality change.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/pcie-mobiveil.c | 261 +
1 file changed, 137 insertions(+), 124 deletions(-)
diff --git a/drivers/
Current SVM AVIC driver makes two incorrect assumptions:
1. APIC LDR register cannot be zero
2. APIC DFR for all vCPUs must be the same
LDR=0 means the local APIC does not support logical destination mode.
Therefore, the driver should mark any previously assigned logical APIC ID
table entry as
From: Hou Zhiqiang
It's confused that R/W some registers by csr_readl()/csr_writel(),
while others by read_paged_register()/write_paged_register().
Actually the low 3KB of 4KB PCIe configure space can be accessed
directly and high 1KB is paging area. So this patch uniformed the
register accessors
From: Hou Zhiqiang
The inbound windows have different register set with outbound windows.
This patch change the MEM inbound window to the first one.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/pcie-mobiveil.c | 2 +-
1 file changed, 1 in
From: Hou Zhiqiang
Outbound window routine:
- Removed unused var definition and register read operations.
- Added the upper 32-bit cpu address setup of the window.
- Instead of blindly write, only change the fields specified.
- Masked the lower bits of window size in case override the
cont
From: Hou Zhiqiang
As the .map_bus() use the WIN_NUM_0 for CFG transactions,
it's better passing WIN_NUM_0 explicitly when initialize
the CFG outbound window.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/pcie-mobiveil.c | 5 ++---
1 file
From: Hou Zhiqiang
This patch corrected the returned error number by convention,
and removed a unnecessary error check.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/pcie-mobiveil.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletion
On 28.01.19 г. 23:24 ч., Dennis Zhou wrote:
> Zlib compression supports multiple levels, but doesn't require changing
> in how a workspace itself is created and managed. Zstd introduces a
> different memory requirement such that higher levels of compression
> require more memory. This requires c
From: Hou Zhiqiang
Sometimes there is not a PCIe Endpoint in the PCIe slot, so do
not exit when the PCIe link is not up. And degrade the print
level of link up info.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/mobiveil/pcie-mobiveil-host
From: Hou Zhiqiang
Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
is not used in current code, and "apb_csr" is not used by some
platforms.
Signed-off-by: Hou Zhiqiang
Acked-by: Subrahmanya Lingappa
Acked-by: Rob Herring
Reviewed-by: Minghuan Lian
---
V3:
- No change
From: Hou Zhiqiang
Fix up the Class Code to PCI bridge, do not change the Revision ID.
And move the fixup to mobiveil_host_init function.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge
IP driver")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
The function svm_refresh_apicv_exec_ctrl() always returning prematurely
as kvm_vcpu_apicv_active() always return false when calling from
the function arch/x86/kvm/x86.c:kvm_vcpu_deactivate_apicv().
This is because the apicv_active is set to false just before calling
refresh_apicv_exec_ctrl().
Also
On Tue, Jan 29, 2019 at 04:44:35PM +0900, Alexandre Courbot wrote:
> On Fri, Jan 25, 2019 at 10:04 PM Paul Kocialkowski
> > On Thu, 2019-01-24 at 20:23 +0800, Ayaka wrote:
> > >
> > > Sent from my iPad
> > >
> > > > On Jan 24, 2019, at 6:27 PM, Paul Kocialkowski
> > > > wrote:
> > > >
> > > > Hi,
From: Hou Zhiqiang
Avoid to issue CFG transactions to link partner when the PCIe
link is not up. And allow CFG transactions to all functions of
Endpoint implemented multiple functions.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
Bridge IP driver")
Signed-off-by: Hou Zhiqiang
Rev
On Tue, Jan 29, 2019 at 6:38 PM Matthew Wilcox wrote:
>
> Pages which use page_type must never be mapped to userspace as it would
> destroy their page type. Add an explicit check for this instead of
> assuming that kernel drivers always get this right.
>
> Signed-off-by: Matthew Wilcox
Reviewed
From: Hou Zhiqiang
As the Mobiveil PCIe controller support RC&EP DAUL mode, and to
make platforms which integrated the Mobiveil PCIe IP more easy
to add their drivers, this patch moved the Mobiveil driver to
a new directory 'drivers/pci/controller/mobiveil' and refactored
it according to the abst
From: Hou Zhiqiang
In the loop block, there is not code change the loop key,
this patch updated the loop key by re-read the INTx status
register.
This patch also change to clear the handled INTx status.
Note: Need MV to test this fix.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
From: Hou Zhiqiang
Move irq_set_chained_handler_and_data() out of DT parse function.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/pcie-mobiveil.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controll
From: Hou Zhiqiang
The reset value is all zero, so set a workable value for Primary,
Secondary and Subordinate bus numbers.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/pcie-mobiveil.c | 6 ++
1 file changed, 6 insertions(+)
diff --g
From: Hou Zhiqiang
Host initial sequence does not depend on PCIe link up, so move it
to the place just before the enumeration.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/pcie-mobiveil.c | 15 +++
1 file changed, 7 insertions
From: Hou Zhiqiang
Make the mobiveil_host_init function can be used to re-init
host controller's PAB and GPEX CSR register block, as NXP
integrated Mobiveil IP has to reset and then re-init the PAB
and GPEX CSR registers upon Hot-reset.
Signed-off-by: Hou Zhiqiang
---
V3:
- Removed the duplica
From: Hou Zhiqiang
Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.
Signed-off-by: Hou Zhiqiang
---
V3:
- Change back to use an new doc for Layerscape PCIe Gen4 DT bindings.
- Switch the order of "csr_axi_slave" and "config_axi_slave".
.../bindings/pci/layerscape-pci-gen4.txt
From: Hou Zhiqiang
When LX2 PCIe controller is sending multiple split completions and
ACK latency expires indicating that ACK should be send at priority.
But because of large number of split completions and FC update DLLP,
the controller does not give priority to ACK transmission. This
results in
From: Hou Zhiqiang
PCIe configuration access to non-existent function triggered
SERROR interrupt exception.
Workaround:
Disable error reporting on AXI bus during the Vendor ID read
transactions in enumeration.
This ERRATA is only for LX2160A Rev1.0, and it will be fixed
in Rev2.0.
Signed-off-b
From: Hou Zhiqiang
Enable the PCIe Gen4 controller driver for Layerscape SoCs.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defcon
From: Hou Zhiqiang
This PCIe controller is based on the Mobiveil GPEX IP, which is
compatible with the PCI Express™ Base Specification, Revision 4.0.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/mobiveil/Kconfig | 10 +
drivers/pci
From: Hou Zhiqiang
The LX2160A integrated 6 PCIe Gen4 controllers.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++
1 file changed, 163 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale
From: Hou Zhiqiang
Disabled all inbound and outbound windows before set up the windows
in kernel, in case transactions match the window set by bootloader.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
.../controller/mobiveil/pcie-mobiveil-host.c | 7 +++
From: Hou Zhiqiang
As there are some Byte and Half-Work width registers in PCIe
configuration space, add Byte and Half-Word width register
accessors.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
.../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++
From: Hou Zhiqiang
The current code does not support multiple MSIs, so remove
the corresponding flag from the msi_domain_info structure.
Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V3:
- No change
drivers/pci/controller/p
On Mon, Jan 28, 2019 at 04:49:28PM -0800, Todd Kjos wrote:
> +/**
> + * binder_alloc_copy_user_to_buffer() - copy src user to tgt user
> + * @alloc: binder_alloc for this proc
> + * @buffer: binder buffer to be accessed
> + * @buffer_offset: offset into @buffer data
> + * @from: userspace pointer t
> On 27 Jan 2019, at 07.54, Heiner Litz wrote:
>
> This patch fixes a race condition where a write is mapped to the last
> sectors of a line. The write is synced to the device but the L2P is not
> updated yet. When the line is garbage collected before the L2P update is
> performed, the sectors ar
On Tue, 29 Jan 2019 01:32:55 +,
Heyi Guo wrote:
>
> Hi Marc,
>
> Any comments?
None so far, I've queued this to let it soak, and will send it as a
fix if nothing else breaks.
Thanks,
M.
>
> Thanks,
>
> Heyi
>
>
> On 2019/1/24 21:37, Heyi Guo wrote:
> > 1. In current implement
On 28.01.19 г. 23:24 ч., Dennis Zhou wrote:
> Currently, the only user of set_level() is zlib which sets an internal
> workspace parameter. As level is now plumbed into get_workspace(), this
> can be handled there rather than separately.
>
> This repurposes set_level() to bound the level passed
On 28.01.19 г. 23:24 ч., Dennis Zhou wrote:
> Zstd currently only supports the default level of compression. This
> patch switches to using the level passed in for btrfs zstd
> configuration.
>
> Zstd workspaces now keep track of the requested level as this can differ
> from the size of the wor
>From: "Andrew-sh.Cheng"
>
>For big/little cpu cluster architecture,
>not only CPU frequency, but CCI frequency will also affect performance.
>
>Little cores and cci share the same buck in Mediatek mt8183 IC,
>so we add a CCI devfreq which will get notification when buck voltage
>is changed, then
On 28.01.19 г. 23:24 ч., Dennis Zhou wrote:
> The previous patch added generic helpers for get_workspace() and
> put_workspace(). Now, we can migrate ownership of the workspace_manager
> to be in the compression type code as the compression code itself
> doesn't care beyond being able to get a w
On Tue, Jan 29, 2019 at 1:28 AM Stanimir Varbanov
wrote:
>
> Hi Tomasz,
>
> On 1/28/19 9:38 AM, Tomasz Figa wrote:
> > On Fri, Jan 25, 2019 at 7:25 PM Stanimir Varbanov
> > wrote:
> >>
> >> Hi Tomasz,
> >>
> >> Thanks for the comments!
> >>
> >> On 1/25/19 9:59 AM, Tomasz Figa wrote:
> >>> .Hi St
qxl device will not dma, so we don't need ttm_dma_tt. Go use ttm_tt
instead, to avoid wasting resources (swiotlb bounce buffers for
example).
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_ttm.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu
On Mon, Jan 28, 2019 at 02:56:17PM -0800, Andrew Morton wrote:
>
> ---
> a/mm/memory_hotplug.c~mmmemory_hotplug-fix-scan_movable_pages-for-gigantic-hugepages-fix
> +++ a/mm/memory_hotplug.c
> @@ -1305,28 +1305,27 @@ int test_pages_in_a_zone(unsigned long s
> static unsigned long scan_movable_pag
Hi Yogesh,
On Tue, 29 Jan 2019 06:57:51 + Yogesh Narayan Gaur
wrote:
>
> > WARNING: modpost: missing MODULE_LICENSE() in drivers/spi/spi-nxp-fspi.o
> > see include/linux/module.h for more information
> >
> Can someone help in pointing out that why above warning message is coming for
> me
Hi,
On 2019/01/22 20:50, Russell King - ARM Linux admin wrote:
On Tue, Jan 22, 2019 at 08:36:03PM +0900, Sugaya, Taichi wrote:
Hi
On 2018/12/04 22:32, Rob Herring wrote:
On Tue, Dec 4, 2018 at 5:30 AM Sugaya, Taichi
wrote:
Hi
On 2018/12/04 0:49, Rob Herring wrote:
On Mon, Dec 3, 2018 at
ping
On 15/01/2019 16.46, Rasmus Villemoes wrote:
> With CONFIG_DEV_COREDUMP=y and CONFIG_DEBUG_FS=n, building fails:
>
> drivers/gpu/drm/msm/adreno/a2xx_gpu.c:428:4: error: ‘struct msm_gpu_funcs’
> has no member named ‘show’
>.show = adreno_show,
> ^~~~
> drivers/gpu/drm/msm/adreno/a2xx
Add MODULE_LICENSE info to fix below warning:
WARNING: modpost: missing MODULE_LICENSE() in drivers/spi/spi-nxp-fspi.o
Signed-off-by: Yogesh Narayan Gaur
---
drivers/spi/spi-nxp-fspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
ind
> How does QEMU do this today? There isn't a virtio or some other virtual
> memory device that allows memory regions to be shared? I can't believe
> that there isn't one yet. If not, then this should be some kind of
> "generic" QEMU memory device, not a "goldfish" specific one, right?
I also th
Sparse issues a warning:
CHECK init/calibrate.c
init/calibrate.c:271:28: warning: symbol 'calibration_delay_done' was not
declared. Should it be static?
The actual issue is that it's a __weak symbol that archs can override (in fact,
ARM does so), but no prototype is provided. Let's provide o
Let's use xattr_prefix instead of open code.
No logic changes.
Reviewed-by: Chao Yu
Signed-off-by: Gao Xiang
---
[resend v2 as v4]
change log v2:
- remove the confusing line according to Dan Carpenter;
drivers/staging/erofs/xattr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
Let's add .get_acl() to read the file's acl from its xattrs
to make POSIX ACL usable.
Here is the on-disk detail,
fullname: system.posix_acl_access
struct erofs_xattr_entry:
.e_name_len = 0
.e_name_index = EROFS_XATTR_INDEX_POSIX_ACL_ACCESS (2)
fullname: system.posix_acl_default
s
Some devices are slow and cannot keep up with the SPI bus and therefore
require a short delay between words of the SPI transfer.
The example of this that I'm looking at is a SAMA5D2 with a minimum SPI
clock of 400kHz talking to an AVR-based SPI slave. The AVR cannot put
bytes on the bus fast enou
Changed in v4:
* Rename word_delay to word_delay_us and slot it in _beside_ the
existing word_delay parameter in spi_transfer (see commit message for
more info).
* Add code to __spi_validate to make sure transfer and device align with
respect to the word_delay_us parameter
Changed in v3:
* D
If the SPI slave requires an inter-word delay, configure the DLYBCT
register accordingly.
Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
board).
Signed-off-by: Jonas Bonn
CC: Nicolas Ferre
CC: Mark Brown
CC: Alexandre Belloni
CC: Ludovic Desroches
CC: linux-...@vger.kerne
Hi Stephen,
> -Original Message-
> From: Stephen Rothwell [mailto:s...@canb.auug.org.au]
> Sent: Tuesday, January 29, 2019 1:57 PM
> To: Yogesh Narayan Gaur
> Cc: Mark Brown ; Linux Next Mailing List n...@vger.kernel.org>; Linux Kernel Mailing List
> ;
> Frieder Schrempf ; Boris Brezill
Hi
On 2019-01-28 19:28, Yizhuo wrote:
> In function gsc_set_gscblk_fimd_wb(), local variable "gscblk_cfg"
> could be uninitialized of function regmap_read returns -EINVAL.
> However, this value will be write to the register after "or"
> operation. This is potentially unsafe.
>
> Signed-off-by: Yi
On Mon, Jan 28, 2019 at 04:09:08PM +0100, Thierry Reding wrote:
...
>
> Up to here this is a duplicate of timer-tegra20.c. And a lot of
> tegra210_timer_init() is the same as tegra20_timer_init() as well. Can't
> we unify the two drivers instead?
>
> The power cycle restrictions of the architec
On Tue, Jan 29, 2019 at 04:35:20PM +0800, Gao Xiang wrote:
> Let's add .get_acl() to read the file's acl from its xattrs
> to make POSIX ACL usable.
>
> Here is the on-disk detail,
> fullname: system.posix_acl_access
> struct erofs_xattr_entry:
> .e_name_len = 0
> .e_name_index = E
From: Joerg Roedel
The function returns the maximum size that can be mapped
using DMA-API functions. The patch also adds the
implementation for direct DMA and a new dma_map_ops pointer
so that other implementations can expose their limit.
Reviewed-by: Konrad Rzeszutek Wilk
Signed-off-by: Joerg
From: Joerg Roedel
Segments can't be larger than the maximum DMA mapping size
supported on the platform. Take that into account when
setting the maximum segment size for a block device.
Reviewed-by: Konrad Rzeszutek Wilk
Signed-off-by: Joerg Roedel
---
drivers/block/virtio_blk.c | 10 ++--
From: Joerg Roedel
This function will be used from dma_direct code to determine
the maximum segment size of a dma mapping.
Reviewed-by: Konrad Rzeszutek Wilk
Signed-off-by: Joerg Roedel
---
include/linux/swiotlb.h | 6 ++
kernel/dma/swiotlb.c| 9 +
2 files changed, 15 insertio
Hi,
here is the fourth version of this patch-set. Previous
versions can be found here:
V1: https://lore.kernel.org/lkml/20190110134433.15672-1-j...@8bytes.org/
V2: https://lore.kernel.org/lkml/20190115132257.6426-1-j...@8bytes.org/
V3: https://lore.kernel.org/lkml/2019
From: Bartosz Golaszewski
Modify the way the debugfs interface works in gpio-mockup. Introduce
the concept of dummy pull config which will keep the mockup lines in
known state. The pull values can be modified by writing to the debugfs
files corresponding to lines. Lines in input mode always repor
From: Joerg Roedel
The function returns the maximum size that can be remapped
by the SWIOTLB implementation. This function will be later
exposed to users through the DMA-API.
Reviewed-by: Konrad Rzeszutek Wilk
Signed-off-by: Joerg Roedel
---
include/linux/swiotlb.h | 5 +
kernel/dma/swiot
On Fri, Jan 25, 2019 at 09:53:35AM +0100, David Hildenbrand wrote:
Hi David,
> I only had a quick glimpse. I would prefer if the caller of add_memory()
> can specify whether it would be ok to allocate vmmap from the range.
> This e.g. allows ACPI dimm code to allocate from the range, however
> oth
From: Bartosz Golaszewski
The unlocked variants only get called from places where we already have
the pointer to the underlying gpio_mockup_chip structure, so take it
as parameter instead of struct gpio_chip.
Signed-off-by: Bartosz Golaszewski
---
drivers/gpio/gpio-mockup.c | 19 --
From: Bartosz Golaszewski
While no user reported any race condition problems with gpio-mockup,
let's be on the safe side and use a mutex when performing any changes
on the dummy chip structures.
Suggested-by: Uwe Kleine-König
Signed-off-by: Bartosz Golaszewski
---
drivers/gpio/gpio-mockup.c |
From: Bartosz Golaszewski
We already support set_multiple(). Implement get_multiple() as well.
Signed-off-by: Bartosz Golaszewski
---
drivers/gpio/gpio-mockup.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpio/gpio-mockup.c b/drivers/gpio/gpio-mockup.c
index
From: Joerg Roedel
This function returns the maximum segment size for a single
dma transaction of a virtio device. The possible limit comes
from the SWIOTLB implementation in the Linux kernel, that
has an upper limit of (currently) 256kb of contiguous
memory it can map. Other DMA-API implementati
From: Bartosz Golaszewski
This series aims at reworking the gpio-mockup debugfs interface. The
reason for that is the fact that certain known problems with this
testing module exist and the user-space tests are broken anyway
after commit fa38869b0161 ("gpiolib: Don't support irq sharing
for users
From: Bartosz Golaszewski
User-space tests no longer use it and we're breaking the interface
anyway.
Signed-off-by: Bartosz Golaszewski
---
drivers/gpio/gpio-mockup.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpio/gpio-mockup.c b/drivers/gpio/gpio-mockup.
From: Bartosz Golaszewski
This field can never be negative.
Signed-off-by: Bartosz Golaszewski
---
drivers/gpio/gpio-mockup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-mockup.c b/drivers/gpio/gpio-mockup.c
index 0317917a3678..433adb3b4617 100644
---
From: Bartosz Golaszewski
Delegate the offset to virq number mapping to the provided framework
instead of handling it locally. Use the legacy domain as we want to
preallocate the irq descriptors.
Signed-off-by: Bartosz Golaszewski
---
include/linux/irq_sim.h | 6 +--
kernel/irq/irq_sim.c|
From: Bartosz Golaszewski
We want to support multiple instances of irq_sim. Make struct irq_chip
part of the irq_sim structure.
Signed-off-by: Bartosz Golaszewski
---
include/linux/irq_sim.h | 2 ++
kernel/irq/irq_sim.c| 12 +---
2 files changed, 7 insertions(+), 7 deletions(-)
d
From: Bartosz Golaszewski
Provide a more specialized variant of irq_sim_fire() that allows to
specify the type of the fired interrupt. The type is stored in the
dummy irq context struct via the set_type callback.
Signed-off-by: Bartosz Golaszewski
---
include/linux/irq_sim.h | 9 -
ke
On 29.01.19 09:31, Yogesh Narayan Gaur wrote:
> Add MODULE_LICENSE info to fix below warning:
> WARNING: modpost: missing MODULE_LICENSE() in drivers/spi/spi-nxp-fspi.o
>
> Signed-off-by: Yogesh Narayan Gaur
> ---
> drivers/spi/spi-nxp-fspi.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff -
Em Mon, Jan 28, 2019 at 09:00:37AM -0800, Andi Kleen escreveu:
> > > also now it won't make sample for slave events
> > > with zero value/period read
> > >
> > > note the patch needs to be split into more patches,
> > > sending it all together for discussion over the solution
> >
> > any feedback
From: Hans Holmberg
pblk stripes writes of minimal write size across all non-offline chunks
in a line, which means that the maximum write pointer delta should not
exceed the minimal write size. Extend the line write pointer balance check
to cover this case.
Signed-off-by: Hans Holmberg
---
Thi
Den 29.01.2019 09.25, skrev Gerd Hoffmann:
> qxl device will not dma, so we don't need ttm_dma_tt. Go use ttm_tt
> instead, to avoid wasting resources (swiotlb bounce buffers for
> example).
>
> Signed-off-by: Gerd Hoffmann
> ---
Acked-by: Noralf Trønnes
On Mon, Jan 28, 2019 at 04:53:19PM +0100, Thomas Gleixner wrote:
> Right after staring long enough at it, the commit simply forgot to give
> __rt_mutex_start_proxy_lock() the same treatment as it gave to
> rt_mutex_wait_proxy_lock().
>
> Patch below cures that.
Yes, that is a very nice solution.
Some updates:
http://8ch.net/tech/res/1018729.html#1024398
Anonymous 01/29/19 (Tue) 08:32:45 No.1024591
1024400
I rescind the license from you.
I am going to sue you if I find out who you are.
1024400
#This program is free software; you can redistribute it and/or
#modify it under t
Hi, Bibby:
On Tue, 2019-01-29 at 15:31 +0800, Bibby Hsieh wrote:
> add mt8183 compatible name
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mail
On Mon, 28 Jan 2019, Eddie James wrote:
> From: Eddie James
>
> Source files for the FSI OCC and OCC hwmon drivers had a combination of bad
> license information and missing IBM copyright. Correct the licenses.
Thanks for cleaning that up!
tglx
On 2019/1/29 16:43, Dan Carpenter wrote:
> On Tue, Jan 29, 2019 at 04:35:20PM +0800, Gao Xiang wrote:
>> Let's add .get_acl() to read the file's acl from its xattrs
>> to make POSIX ACL usable.
>>
>> Here is the on-disk detail,
>> fullname: system.posix_acl_access
>> struct erofs_xattr_entry:
>>
Hi Rafael,
On 2019-01-29 00:05, Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
>
> The device links used by rockchip-iommu and exynos-iommu are
> completely managed by these drivers within the IOMMU framework,
> so there is no reason to involve the driver core in the management
> of these lin
On Tue, 29 Jan 2019 08:01:22 +,
YueHaibing wrote:
>
> There is a potential NULL pointer dereference in case kzalloc()
> fails and returns NULL.
>
> Fixes: 4bba66899ac6 ("irqchip/tango: Add support for Sigma Designs
> SMP86xx/SMP87xx interrupt controller")
> Signed-off-by: YueHaibing
> ---
Adding documentation for 3 new backup battery charging dts
properties:
- maxim,backup-battery-charging-current
- maxim,backup-battery-charging-voltage
- maxim,backup-battery-output-resister
Signed-off-by: Mark Zhang
---
.../devicetree/bindings/mfd/max77620.txt | 20 +++
1 fi
This patch adds PMIC configurations for low-battery
monitoring by handling max77620 register CNFGGLBL1.
Signed-off-by: Laxman Dewangan
Signed-off-by: Venkat Reddy Talla
Signed-off-by: Mark Zhang
---
drivers/mfd/max77620.c | 57 +-
1 file changed, 56 inse
This patch set adds support for max77620 backup battery charging and
low battery monitoring.
Changes in v2:
- Add devicetree binding documentation
Mark Zhang (4):
mfd: max77620: Add backup battery charger support
mfd: max77620: add documentation for backup battery charging
mfd: max77620: Ad
Add PMIC configurations for backup battery charger, which
is a constant voltage and constant current style charger
with a series output resistance.
The max77620 register CNFGBBC(addr: 0x04) defines the
parameters of backup battery charger. This patch adds
support for it.
Signed-off-by: Laxman Dew
Adding documentation for low battery monitor properties:
- maxim,low-battery-dac-enable
- maxim,low-battery-dac-disable
- maxim,low-battery-shutdown-enable
- maxim,low-battery-shutdown-disable
- maxim,low-battery-reset-enable
- maxim,low-battery-reset-disable
Signed-off-by: Mark Zhang
---
Docume
On Mon, Jan 28, 2019 at 09:33:04AM +0100, Jacopo Mondi wrote:
> Hi everyone,
>
> On Mon, Jan 28, 2019 at 01:20:37PM +0530, Jagan Teki wrote:
> > On Fri, Jan 25, 2019 at 9:10 PM Maxime Ripard
> > wrote:
> > >
> > > On Thu, Jan 24, 2019 at 11:28:01PM +0530, Jagan Teki wrote:
> > > > The ov5640_try
On Mon, Jan 28, 2019 at 04:53:19PM +0100, Thomas Gleixner wrote:
> On Mon, 28 Jan 2019, Peter Zijlstra wrote:
> > On Mon, Jan 28, 2019 at 02:44:10PM +0100, Peter Zijlstra wrote:
> > > On Thu, Nov 29, 2018 at 12:23:21PM +0100, Heiko Carstens wrote:
> > >
> > > > And indeed, if I run only this test
Hi Andrew,
Andrew Lunn wrote on Mon, 28 Jan 2019 18:42:46 +0100:
> On Mon, Jan 28, 2019 at 04:57:49PM +0100, Miquel Raynal wrote:
> > Hi Andrew,
> >
> > Thanks for helping!
> >
> > Andrew Lunn wrote on Mon, 28 Jan 2019 15:44:17 +0100:
> >
> > > > I don't see where VLAN and bridge informati
Em Wed, Jan 23, 2019 at 09:33:38AM +0100, Jiri Olsa escreveu:
> On Tue, Jan 22, 2019 at 05:34:39PM -0600, Gustavo A. R. Silva wrote:
> > Notice that the use of the bitwise OR operator '|' always leads to
> > true in this particular case, which seems a bit suspicious due to
> > the context in which
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