On 29-10-18, 17:23, Daniel Lezcano wrote:
> In the case of assymetric SoC with the same micro-architecture, we
> have a group of CPUs with smaller OPPs than the other group. One
> example is the 96boards dragonboard 820c. There is no dmips/MHz
> difference between both groups, so no need to specify
On Tue 2018-10-30 02:22:42, YueHaibing wrote:
> Remove duplicated include.
>
> Signed-off-by: YueHaibing
Acked-by: Pavel Machek
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
signature.asc
Description:
Since commit 9042f5e3539e ("perf tools: Stop fallbacking to kallsyms
for vdso symbols lookup"), the kernel address cannot be properly parsed
to kernel symbol with command 'perf script -k vmlinux'. The reason is
CoreSight samples is always to set CPU mode as PERF_RECORD_MISC_USER,
thus it fails to
Am 29.10.18 um 19:25 schrieb Luck, Tony:
> On Mon, Oct 29, 2018 at 06:51:29PM +0100, Borislav Petkov wrote:
>> On Mon, Oct 29, 2018 at 04:59:44PM +, Luck, Tony wrote:
>>> The EDAC driver printed out those messages,
>>
>> I don't think so - that's __print_mce() in mce.c which dumps the three
>
Hi all,
It's time for a release, autofs-5.1.5.
A few changes of note are:
With the deprecation of the fedfs-utils package it was necessary
to add a couple of binaries from that package for fedfs users to
give them time to migrate away from using fedfs. The binaries
included in autofs are fedfs-m
On Saturday, October 27, 2018 8:37:24 AM CET Doug Smythies wrote:
> This is just for anybody else trying to compile:
>
> On 2018.10.26 02:12 Rafael J. Wysocki wrote:
>
> > The venerable menu governor does some thigns that are quite
>
> Typo: thigns -> things
>
> ...[snip]...
>
> > The patch sh
On Mon, Oct 29, 2018 at 1:15 PM David Abdurachmanov
wrote:
>
> Depends on:
> http://lists.infradead.org/pipermail/linux-riscv/2018-October/001931.html
>
> Why we don't have HAVE_SYSCALL_TRACEPOINTS in arch/riscv/Kconfig?
>
I looked this morning into Documentation/trace/ftrace-design.rst again.
O
+ Srinivas
On 19-Oct-18 5:42 PM, Andy Shevchenko wrote:
On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj
wrote:
This adds support to show the Latency Tolerance Reporting for the IPs on
the PCH as reported by the PMC. The format shown here is raw LTR data
payload that can further be decoded as
On Monday, October 29, 2018 3:09:25 AM CET Stephen Rothwell wrote:
>
> --Sig_/Yi5UDAd5LU=QdOHo+ui7Syk
> Content-Type: text/plain; charset=US-ASCII
> Content-Transfer-Encoding: quoted-printable
>
> Hi Rafael,
>
> Today's linux-next merge of the pm tree got conflicts in:
>
> drivers/i2c/busses/
On Monday, October 29, 2018 3:01:24 AM CET Stephen Rothwell wrote:
>
> --Sig_/X_/swfdki+BZTJ8afk_lQqW
> Content-Type: text/plain; charset=US-ASCII
> Content-Transfer-Encoding: quoted-printable
>
> Hi Rafael,
>
> Today's linux-next merge of the pm tree got a conflict in:
>
> drivers/cpuidle/go
On 19-Oct-18 6:09 PM, Andy Shevchenko wrote:
On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj
wrote:
On some Goldmont based systems such as ASRock J3455M the BIOS may not
enable the IPC1 device that provides access to the PMC and PUNIT. In
such scenarios, the IOSS and PSS resources from the
Hi Andy,
Thanks for your review. My comments below.
If you agree then i can quickly send v3 addressing all suggestions so we
can make it in time for 4.20 merge window.
On 19-Oct-18 6:04 PM, Andy Shevchenko wrote:
On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj
wrote:
The LTR values follo
On 30/10/2018 06:50, Viresh Kumar wrote:
> On Mon, Oct 29, 2018 at 9:56 PM Daniel Lezcano
> wrote:
>
> Would have been better if I was cc'd on all the patches since I was
> looking at this
> stuff actively this week :)
ah, yes. Sorry for that.
>> The function 'register_cpufreq_notifier' regist
On 30/10/18 12:17 AM, Rajat Jain wrote:
> Problem:
>
> The card detect IRQ does not work with modern BIOS (that want
> to use _DSD to provide the card detect GPIO to the driver).
>
> Details:
>
> The mmc core provides the mmc_gpiod_request_cd() API to let host drivers
> request the gpio descript
When initialing prz with invalid data in buffer(no PERSISTENT_RAM_SIG),
function call path is like this:
ramoops_init_prz ->
|
|-> persistent_ram_new -> persistent_ram_post_init -> persistent_ram_zap
|
|-> persistent_ram_zap
As we can see, persistent_ram_zap() is called twice.
We can avoid this b
On Tue 30-10-18 14:55:51, Miles Chen wrote:
[...]
> It's a real problem when using page_owner.
> I found this issue recently: I'm not able to read page_owner information
> during a overnight test. (error: read failed: Out of memory). I replace
> kmalloc() with vmalloc() and it worked well.
Is this
On Tue 30-10-18 06:54:33, Naoya Horiguchi wrote:
> On Fri, Oct 26, 2018 at 10:46:36AM +0200, Michal Hocko wrote:
> > On Wed 22-08-18 10:00:25, Michal Hocko wrote:
> > > On Wed 22-08-18 01:37:48, Naoya Horiguchi wrote:
> > > > On Wed, Aug 15, 2018 at 03:43:34PM -0700, Andrew Morton wrote:
> > > > >
On 2018-10-27 21:47, Alexey Dobriyan wrote:
> On Fri, Oct 26, 2018 at 11:20:34PM +0200, Rasmus Villemoes wrote:
>> +#include
>
>> +#define linux_proc_banner \
>> +"%s version %s" \
>> +" (" LINUX_COMPILE_BY "@" LINUX_COMPILE_HOST ")" \
>> +" (" LINUX_COMPILER ") %s\n"
>
> Include doe
On Mon, 29 Oct 2018 23:15:42 +
"Grandbois, Brett" wrote:
> On 28/10/18 1:39 am, Boris Brezillon wrote:
> > Hi Brett,
> >
> > On Tue, 16 Oct 2018 00:57:41 +
> > "Grandbois, Brett" wrote:
> >
> >> Add support to expose the SPI boot flash on AMD Family 16h CPUs as
> >> a standard mtd devi
Hi Linus,
Please pull from the tag
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git \
pm-4.20-rc1-2
with top-most commit c4ac6889930d027ffa5cf77e0c202e7e97a4be06
Merge branches 'pm-cpuidle' and 'pm-cpufreq'
on top of commit bd6bf7c10484f026505814b690104cdef27ed460
Merge t
Hi Linus,
Please pull from the tag
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git \
acpi-4.20-rc1-2
with top-most commit 6a9b593d4b6f5994209456de7a3c2db0974b5dda
ACPI / PMIC: xpower: Add depends on IOSF_MBI to Kconfig entry
on top of commit bd6bf7c10484f026505814b690104cd
On 30/10/2018 07:12, Viresh Kumar wrote:
> On Mon, Oct 29, 2018 at 9:56 PM Daniel Lezcano
> wrote:
>>
>> When the function topology_parse_cpu_capacity() fails, we set the boolean
>> cap_parsing_failed to true and we free the raw_capacity. This is correct as
>> the function begins with a check agai
On 30-10-18, 08:55, Daniel Lezcano wrote:
> The workqueue is called from init_cpu_capacity_callback(). This one is
> called in the notifier callback. IOW the notification callback
> unregisters itself. But if it is not registered, it won't unregister,
> hence it won't call the workqueue and init_cp
Michael,
On Mon, 22 Oct 2018, Michael Kelley wrote:
> pit_shutdown() doesn't work on Hyper-V because of a quirk in the
> PIT emulation. After shutdown the emulated PIT continues to interrupt
> @18.2 HZ. This problem exists in all versions of Hyper-V and just
> had not previously been noticed. So
On 30/10/2018 00:12, Sebastian Andrzej Siewior wrote:
> On 2018-10-29 21:16:16 [+0100], Daniel Wagner wrote:
>> From: Daniel Wagner
>>
>> v4.4.162-rt176-rc1 stable review patch.
>> If anyone has any objections, please let me know.
>
> I though that we are going to route this via Greg/stable for v
On 30/10/2018 08:13, Viresh Kumar wrote:
> On 29-10-18, 17:23, Daniel Lezcano wrote:
>> In the case of assymetric SoC with the same micro-architecture, we
>> have a group of CPUs with smaller OPPs than the other group. One
>> example is the 96boards dragonboard 820c. There is no dmips/MHz
>> differ
This patch series intends to add flexcan support for IMX6 platforms.
ChangeLog:
V1-V2:
*using SPDX tag for new files and remove pinctrl-assert-gpios property.
Dong Aisheng (3):
ARM: dts: imx6sx-sdb: Add flexcan support
ARM: dts: imx6sx-sabreauto: Add flexcan support
ARM: dts: sabreauto: Ad
From: Dong Aisheng
The flexcan1 is pin conflict with fec. So we add a new dts file with
flexcan1 enabled with fec disabled for user to use.
Signed-off-by: Dong Aisheng
Signed-off-by: Joakim Zhang
---
.../boot/dts/imx6dl-sabreauto-flexcan1.dts| 14 ++
.../arm/boot/dts/imx6q-sabreauto-f
From: Dong Aisheng
CAN transceiver is different on RevA and RevB board.
It's active high on RevA while active low on Rev B.
Signed-off-by: Dong Aisheng
Signed-off-by: Joakim Zhang
---
arch/arm/boot/dts/imx6sx-sdb-reva.dts | 12
arch/arm/boot/dts/imx6sx-sdb.dts | 5
arch/ar
From: Dong Aisheng
The CAN transceiver on MX6SX Sabreauto board seems in sleep mode
by default after power up the board. User has to press the wakeup
key on ARD baseboard before using the transceiver, or it may not
work properly when power up the board at the first time(warm reset
does not have s
On 30-10-18, 09:39, Daniel Lezcano wrote:
> SCHED_CAPACITY_SCALE is the default value in this file.
>
> eg.
>
> DEFINE_PER_CPU(unsigned long, cpu_scale) = SCHED_CAPACITY_SCALE
> ...
> pr_err("cpu_capacity: partial information: fallback to 1024 for all
> CPUs\n");
> ...
>
> So I prefer to use the
Hi all,
Since yesterdays next, all my boards booting from NFS root (NFSv4)
experience infinite warnings:
[ 210.199561] [ cut here ]
[ 210.204169] WARNING: CPU: 1 PID: 191 at ../lib/iov_iter.c:1082
iov_iter_kvec+0x54/0x5c
[ 210.212048] Modules linked in:
[ 210.215094] CPU:
On Tue, Oct 30, 2018 at 3:21 AM, Joel Fernandes wrote:
> On Mon, Oct 29, 2018 at 3:11 PM Daniel Colascione wrote:
>>
>> Add a simple proc-based kill interface. To use /proc/pid/kill, just
>> write the signal number in base-10 ASCII to the kill file of the
>> process to be killed: for example, 'ec
Le 24/10/2018 à 19:15, Laurent Vivier a écrit :
> On 16/10/2018 17:22, Andrei Vagin wrote:
>> On Wed, Oct 10, 2018 at 06:14:30PM +0200, Laurent Vivier wrote:
>>> This patch allows to have a different binfmt_misc configuration
>>> for each new user namespace. By default, the binfmt_misc configuratio
s/dmpis/dmips/ in $subject
On 29-10-18, 17:23, Daniel Lezcano wrote:
> In the case of assymetric SoC with the same micro-architecture, we
asymmetric ?
> have a group of CPUs with smaller OPPs than the other group. One
> example is the 96boards dragonboard 820c. There is no dmips
On Tue, Oct 30, 2018 at 3:06 AM, Joel Fernandes wrote:
> On Mon, Oct 29, 2018 at 1:01 PM Daniel Colascione wrote:
>>
>> Thanks for taking a look.
>>
>> On Mon, Oct 29, 2018 at 7:45 PM, Joel Fernandes wrote:
>> >
>> > On Mon, Oct 29, 2018 at 10:53 AM Daniel Colascione
>> > wrote:
>> > >
>> > >
Hi Bhupesh,
On 10/30/18 at 12:33pm, Bhupesh Sharma wrote:
> > Why it's broken? Have you investigated and figured out why it's broken?
> > If fix, what patch will it look like? Does the patch prove it's not
> > worth using the current way?
> >
> > Have you thought about this in advance? Or still li
Commit-ID: 28fa741c27e6d57f6bf594ba3c444ce79e671e09
Gitweb: https://git.kernel.org/tip/28fa741c27e6d57f6bf594ba3c444ce79e671e09
Author: Colin Ian King
AuthorDate: Mon, 29 Oct 2018 23:32:11 +
Committer: Ingo Molnar
CommitDate: Tue, 30 Oct 2018 09:51:58 +0100
perf/core: Clean up inco
Commit-ID: 7847c7be0481558f17e3ef3b03f573677fd30d29
Gitweb: https://git.kernel.org/tip/7847c7be0481558f17e3ef3b03f573677fd30d29
Author: Juergen Gross
AuthorDate: Tue, 30 Oct 2018 07:33:01 +0100
Committer: Ingo Molnar
CommitDate: Tue, 30 Oct 2018 09:55:31 +0100
x86/paravirt: Remove unus
On Tue, Oct 30, 2018 at 5:00 AM, Aleksa Sarai wrote:
> On 2018-10-29, Daniel Colascione wrote:
>> Add a simple proc-based kill interface. To use /proc/pid/kill, just
>> write the signal number in base-10 ASCII to the kill file of the
>> process to be killed: for example, 'echo 9 > /proc/$$/kill'.
Pavel Machek 於 2018年10月30日 週二 下午3:15寫道：
>
> On Tue 2018-10-30 02:22:42, YueHaibing wrote:
> > Remove duplicated include.
> >
> > Signed-off-by: YueHaibing
>
> Acked-by: Pavel Machek
>
Hi Pavel and YueHaibin,
Thank you.
Acked-by: Greentime Hu
Hello Dear,
My name is Smadar Barber-Tsadik, I'm the Chief Executive Officer C.P.A of the
First International Bank of Israel (FIBI). I'm getting in touch with you in
regards to a very important and urgent matter. Kindly respond back at your
earliest convenience so I can provide you the details.
Hello Dear
Do you have the passion for humanitarian welfare?
Can you devote your time and be totally committed and devoted
to run multi-million pounds humanitarian charity project sponsored
totally by me; with an incentive/compensation accrual to you for
your time and effort and at no cost to yo
Hi Vincent,
On Fri, Oct 26, 2018 at 06:11:43PM +0200, Vincent Guittot wrote:
> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> index 6806c27..7a69673 100644
> --- a/kernel/sched/fair.c
> +++ b/kernel/sched/fair.c
> @@ -674,9 +674,8 @@ static u64 sched_vslice(struct cfs_rq *cfs_rq, struct
On Tue, Oct 23, 2018 at 02:43:04PM -0300, Shayenne da Luz Moura wrote:
> Remove unneeded parentheses around the arguments of ||. This reduces
> clutter and code behave in the same way.
> Change suggested by checkpatch.pl.
>
> vbox_main.c:119: CHECK: Unnecessary parentheses around 'rects[i].x2 <
>
PING
On Tue, Oct 16, 2018 at 05:06:07PM +0200, Jiri Olsa wrote:
> So the extra user build flags are propagated to libtraceevent.
>
> Cc: Arnaldo Carvalho de Melo
> Signed-off-by: Jiri Olsa
> ---
> tools/perf/Makefile.perf | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
ping
thanks,
jirka
On Tue, Oct 16, 2018 at 05:06:10PM +0200, Jiri Olsa wrote:
> So user could specify outside CFLAGS/LDFLAGS values.
>
> Cc: Signed-off-by: Len Brown
> Signed-off-by: Jiri Olsa
> ---
> tools/power/x86/x86_energy_perf_policy/Makefile | 6 +++---
> 1 file changed, 3 insertions(+
On Tue, Oct 23, 2018 at 11:30:11AM +0100, John Garry wrote:
> Hi all,
>
> I have stumbled upon this crash on my arm64 system:
>
> [7.040874] SMP: Total of 64 processors activated.
> [7.045720] CPU features: detected: GIC system register CPU interface
> [7.052240] CPU features: detecte
ping
thanks,
jirka
On Tue, Oct 16, 2018 at 05:06:11PM +0200, Jiri Olsa wrote:
> So user could specify outside CFLAGS values.
>
> Cc: Zhang Rui
> Cc: Markus Mayer
> Signed-off-by: Jiri Olsa
> ---
> tools/thermal/tmon/Makefile | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
ping
thanks,
jirka
On Tue, Oct 16, 2018 at 05:06:13PM +0200, Jiri Olsa wrote:
> So user could specify outside CFLAGS/LDFLAGS values.
>
> Cc: Len Brown
> Signed-off-by: Jiri Olsa
> ---
> tools/power/x86/turbostat/Makefile | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> dif
Kang,
On Thu, 25 Oct 2018, Kang, Luwei wrote:
> > > +#define SECONDARY_EXEC_PT_USE_GPA 0x0100
> > > +#define VM_EXIT_CLEAR_IA32_RTIT_CTL0x0200
> > > +#define VM_ENTRY_LOAD_IA32_RTIT_CTL0x0004
> >
> > Where are all of these bits documented? I'm look
On Tue, Oct 30, 2018 at 9:25 AM Bhardwaj, Rajneesh
wrote:
>
> + Srinivas
>
>
> On 19-Oct-18 5:42 PM, Andy Shevchenko wrote:
> > On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj
> > wrote:
> >> This adds support to show the Latency Tolerance Reporting for the IPs on
> >> the PCH as reported by the
The function could report a false positive if it gets preempted between reading
the XEL_MDIOCTRL_OFFSET register and checking for the timeout. In such a case,
the condition has to be rechecked to avoid false positives.
Therefore, check for expected condition even after the timeout occurred.
Sign
The function could report a false positive if it gets preempted between reading
the XAE_MDIO_MCR_OFFSET register and checking for the timeout. In such a case,
the condition has to be rechecked to avoid false positives.
Therefore, check for expected condition even after the timeout occurred.
Sign
On Mon, Oct 29, 2018 at 04:52:04PM -0700, Florian Fainelli wrote:
> If the architecture implements ARCH_HAS_PHYS_INITRD, make the FDT
> scanning code populate the physical address of the start of the FDT and
> its size.
>
> Signed-off-by: Florian Fainelli
> ---
> arch/arm/mm/init.c | 2 +-
> dri
ping
thanks,
jirka
On Mon, Oct 22, 2018 at 04:50:07PM +0200, Jiri Olsa wrote:
> On Tue, Oct 16, 2018 at 05:06:05PM +0200, Jiri Olsa wrote:
> > hi,
> > while hardening some of the tools rpm, we noticed we
> > can't pass build flags to some of them.
> >
> > Sending separate tools fixes for what w
On Tue, Oct 30, 2018 at 9:40 AM Bhardwaj, Rajneesh
wrote:
> Thanks for your review. My comments below.
>
> If you agree then i can quickly send v3 addressing all suggestions so we
> can make it in time for 4.20 merge window.
I don't like `quickly` part — usual way to make the last minute mistake
Hi,
On Tue, Oct 30, 2018 at 3:57 PM Zhenzhong Duan
wrote:
>
> Since retpoline capable compilers are widely available, make
> CONFIG_RETPOLINE hard depend on it.
>
> Change KBUILD to use CONFIG_RETPOLINE_SUPPORT to avoid conflict with
> CONFIG_RETPOLINE which is used by kernel.
>
> With all that
On 2018/10/30 15:31, Michal Hocko wrote:
> On Tue 30-10-18 13:45:22, Tetsuo Handa wrote:
>> Michal Hocko wrote:
>>> @@ -3156,6 +3166,13 @@ void exit_mmap(struct mm_struct *mm)
>>> vma = remove_vma(vma);
>>> }
>>> vm_unacct_memory(nr_accounted);
>>> +
>>> + /*
>
On 30/10/2018 10:30, Thomas Gleixner wrote:
>> This part is in the " Intel® Architecture Instruction Set Extensions and
>> Future Features Programming Reference"
>> https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>>
> Y
Hi Sven,
some tries to answer questions... (I am no expert in this but
I try my best)
On Thu, Oct 25, 2018 at 5:21 PM wrote:
> I had originally architected this driver to be much simpler, with everything
> running in the context of the userspace threads (except obviously the
> interrupt). But i
On 30/10/2018 09:26, Peter Zijlstra wrote:
On Tue, Oct 23, 2018 at 11:30:11AM +0100, John Garry wrote:
Hi all,
I have stumbled upon this crash on my arm64 system:
[7.040874] SMP: Total of 64 processors activated.
[7.045720] CPU features: detected: GIC system register CPU interface
[
On Wed, 24 Oct 2018, Luwei Kang wrote:
> This adds support for "output to Trace Transport subsystem"
> capability of Intel PT. It means that PT can output its
> trace to an MMIO address range rather than system memory buffer.
>
> Acked-by: Song Liu
> Signed-off-by: Luwei Kang
For patches 1-5:
This seems to be needed for virtio-gpu.
Signed-off-by: David Abdurachmanov
Reported-by: Michael Forney
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a344980287a5..b54f2ade769b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/r
Some arch-support.txt are out-of-date.
This also incl. riscv in sg-chain and pte_special tables.
Signed-off-by: David Abdurachmanov
---
Documentation/features/io/sg-chain/arch-support.txt | 4 ++--
.../features/locking/queued-spinlocks/arch-support.txt| 2 +-
Documentation/feat
On Mon, 29 Oct 2018, Paolo Bonzini wrote:
> On 24/10/2018 12:13, Alexander Shishkin wrote:
> > Luwei Kang writes:
> >> + /*
> >> + * Set guest state of MSR_IA32_RTIT_CTL MSR (PT will be disabled
> >> + * on VM entry when it has been disabled in guest before).
> >> + */
> >> + vmcs_write64(
This should improve virtio-gpu support for riscv.
David Abdurachmanov (2):
riscv: add ARCH_HAS_SG_CHAIN
doc: re-run features-refresh.sh
Documentation/features/io/sg-chain/arch-support.txt | 4 ++--
.../features/locking/queued-spinlocks/arch-support.txt| 2 +-
Documentation/
Hi!
> > > This makes keyboard/touchpad work on a DT MMP2 platform.
> > >
> > > I believe that it would be a good idea if this, once reviewed, went
> > > in
> > > via the input tree. The DT and CLK parts got reviews/acks.
> > >
> > > Changes from v1:
> > > - Basically none, just re-send, includin
if there are lots of irqs for a device and the register addresses for these
irqs is continuous, we can use this macro to initialize regmap_irq value.
Signed-off-by: Tony Xie
---
include/linux/regmap.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/regmap.h b/include/linu
Add support for the rk809 and rk817 regulator driver.
Their specifications are as follows：
1. The RK809 and RK809 consist of 5 DCDCs, 9 LDOs
and have the same registers for these components except dcdc5.
2. The dcdc5 is a boost dcdc for RK817 and is a buck for RK809.
3. T
Add device tree bindings documentation for Rockchip's RK809 & RK817 PMIC.
Signed-off-by: Tony Xie
Reviewed-by: Rob Herring
Acked-for-MFD-by: Lee Jones
---
Documentation/devicetree/bindings/mfd/rk808.txt | 44 +
1 file changed, 44 insertions(+)
diff --git a/Documentatio
The rk809 and rk817 are a Power Management IC (PMIC) for multimedia
and handheld devices. It contains the following components:
- Regulators
- RTC
- Clocking
Both RK809 and RK817 chips are using a similar register map,
so we can reuse the RTC and Clocking and regulators functionality.
Signe
Most of functions and registers of the rk817 and rk808 are the same,
so they can share allmost all codes.
Their specifications are as follows:
1) The RK809 and RK809 consist of 5 DCDCs, 9 LDOs and have the same registers
for these components except dcdc5.
2) The dcdc5 is a boost dcdc for
On Tue, Oct 30, 2018 at 06:39:24PM +0900, Masahiro Yamada wrote:
> Hi,
>
>
>
> On Tue, Oct 30, 2018 at 3:57 PM Zhenzhong Duan
> wrote:
> >
> > Since retpoline capable compilers are widely available, make
> > CONFIG_RETPOLINE hard depend on it.
> >
> > Change KBUILD to use CONFIG_RETPOLINE_SUPPO
This series adds support for various nodes for QCS404-EVB.
Based on next-20181030
Bjorn Andersson (7):
arm64: dts: qcom: qcs404: Add reserved-memory regions
arm64: dts: qcom: qcs404: Add RPM GLINK related nodes
arm64: dts: qcom: qcs404: Add PMS405 RPM regulators
arm64: dts: qcom: qcs404
Add base dts files for QCS404 chipset along with cpu, timer,
gcc and uart2 nodes.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs404-evb.dts | 21
arch/arm64/boot/dts/qcom/qcs404.dtsi| 175
3 f
From: Bjorn Andersson
Add RPM GLINK node and the RPM message ram, hwspinlock, APCS apps global
and smem nodes it depends on.
Signed-off-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 44
1 file changed, 44 insertio
From: Bjorn Andersson
Add the reserved memory regions in QCS404
Signed-off-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 41
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/a
Add the smp2p-adsp, smp2p-cdsp and smp2p-wcss nodes found in QCS404.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 60
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64/boot/dts/qcom/qcs40
From: Bjorn Andersson
Add the RPM regulators found in PMS405 which is used in qcs404-evb
Signed-off-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404-evb.dts | 97 +
1 file changed, 97 insertions(+)
diff --git a/arch/arm64/boot/
Add the pms405 DT file with spmi node.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/pms405.dtsi | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pms405.dtsi
diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi
b/arch/arm64/boot/dts/qcom
From: Bjorn Andersson
Add the QCS404 TLMM pinctrl node with its three tiles.
Signed-off-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64
From: Bjorn Andersson
Add the sdcc1 node and enable it for the QCS404-EVB.
Signed-off-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404-evb.dts | 64 +
arch/arm64/boot/dts/qcom/qcs404.dtsi| 17 +
2 files changed, 81 i
Add the GPIOs present on PMS405 chip.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/pms405.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi
b/arch/arm64/boot/dts/qcom/pms405.dtsi
index cdb4547c998b..18410d9f0f8f 100644
---
PMS405 is used in QCS405-EVB so include that with SPMI nodes
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404-evb.dts | 1 +
arch/arm64/boot/dts/qcom/qcs404.dtsi| 18 ++
2 files changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dts
b/a
RTC is found on PMIC PMS405 and is same as other PMIC used, so add the
rtc node with compatible as qcom,pm8941-rtc
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/pms405.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi
b/arch/arm64/boot/
From: Bjorn Andersson
Add the scm firmware node to QCS404
Signed-off-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64/boot/dts/qcom/qcs404.dtsi
i
From: Bjorn Andersson
Add the TrustZone based remoteproc nodes and their glink edges for
adsp, cdsp and wcss.
Signed-off-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 87
1 file changed, 87 insertions(+)
diff --g
Add the BAM DMA instance found in BLSP1 node of the QCS404
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index eb3c03ddaaa7..d56800
We can use BAM DAM for serial UART data transfers, so add it
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index d568003ee5b6..05f9ad63f6e2 1006
PMS405 also features PON block, so add PON and PWRKEY nodes
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/pms405.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi
b/arch/arm64/boot/dts/qcom/pms405.dtsi
index 18410d9f0f8f..2c
RNG hardware in QCS404 features (Execution Environment) EE for
HLOS to use, add the node for prng-ee for QCS404.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64/boot/d
> >> This part is in the " Intel® Architecture Instruction Set Extensions and
> >> Future Features Programming Reference"
> >> https://software.intel.com/sites/default/files/managed/c5/15/architec
> >> ture-instruction-set-extensions-programming-reference.pdf
> >>
> > Yet another PDF which will ch
RK809 and RK817 are power management IC chips for multimedia products.
most of their functions and registers are same, including the clkout
funciton.
Signed-off-by: Tony Xie
Acked-by: Stephen Boyd
---
drivers/clk/Kconfig | 9 ---
drivers/clk/clk-rk808.c | 64 +++
RK809 and RK817 are power management IC chips for multimedia products.
Most of their functions and registers are same, including the rtc.
Signed-off-by: Tony Xie
Acked-by: Alexandre Belloni
---
drivers/rtc/Kconfig | 4 +--
drivers/rtc/rtc-rk808.c | 68 ++
From: Ludovic Barre
The mmc framework follows the requirement of SD_Specification:
the STOP_TRANSMISSION is sent on multiple write/read commands
and the stop command (alone), not needed on other ADTC commands.
But, if an error happens on command or data step, some variants
require a stop command
Hi Pierre-Louis,
On 29-10-18 23:03, Pierre-Louis Bossart wrote:
On 10/29/18 2:08 PM, Dean Wallace wrote:
On 29-10-18, Andy Shevchenko wrote:
On Mon, Oct 29, 2018 at 7:52 PM Andy Shevchenko
wrote:
Cc: Pierre as well.
On Mon, Oct 29, 2018 at 7:48 PM Stephen Boyd wrote:
Quoting Dean Wallace
Hi Matias,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 11743c56785c751c087eecdb98713eef796609e0
commit: 73569e11032fc5a9b314b6351632cfca7793afd5 lightnvm: remove dependencies
on BLK_DEV_NVME and PCI
date: 3 we
Add the required peripheral clock for the efuse device.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4
2 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/
The first change of this patchset just adds add error message in case
of failure. If there is problem with the secure monitor, the
SM_EFUSE_USER_MAX call will be first one to fail so it is better if it
give us a clue to help debugging, instead af silently failing.
Next this series adds the periphe
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