Greetings,
I`m Aston Morgan an officer of the U.S Army presently serving
the US Army security forces in Kabul, Afghanistan. You may not know me
but I really need your help as I have some very important packages to
ship to you for safe keeping until the end of my mission here.
I will only explain f
On Mon, Oct 29, 2018 at 09:57:20AM +0300, Anatoly Trosinenko wrote:
> > How did the corruption occur?
>
> It is a fuzzed image. Most probably, it was artificially "patched" by
> fuzzer. Or do you mean "what particular bytes were changed"?
I wondered how this specific corruption occurred in the re
> How do I populate /vtmp? Mine is empty at this point. I imagine I should
put the cramfs image somewhere on the host, but I'm not that familiar
withkvm.
Oops, forgot to say, it is the /tmp/kvm-xfstests-$USER directory on
the host (it will be created when you first launch kvm-xfstests and it
is "l
Remove the surplus TAB in hv_do_fast_hypercall16().
Signed-off-by: Yi Wang
---
arch/x86/include/asm/mshyperv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h
index 0d6271c..1d0a777 100644
--- a/arch/x86/includ
From: Jan Luebbe
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).
Signed-off-by: Jan Luebbe
Signed-off-by: Chris Packham
---
MAINTAINERS
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham
---
drivers/edac/armada_xp_edac.c | 5 ++
From: Jan Luebbe
This include file will be used by the AURORA EDAC code.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h | 0
arch/arm/mm/cache-l2x0.c| 2 +-
2 file
From: Jan Luebbe
These defines will be used by subsequent patches to add support for the
parity check and error correction functionality in the Aurora L2 cache
controller.
Signed-off-by: Jan Luebbe
Signed-off-by: Chris Packham
---
.../include/asm/hardware/cache-aurora-l2.h| 48 +++
The aurora cache on the Marvell Armada-XP SoC supports ECC protection
for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
which can be used to enable this.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
Signed-off-by: Jan Luebb
From: Jan Luebbe
The macro name is too generic, so add a AURORA_ prefix.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
arch/arm/mm/cache-l2x0.c| 4 ++--
2 files changed,
From: Andreas Puhm
The probe function needs to verify the CvP enable bit in order to
properly determine if FPGA Manager functionality can be safely
enabled.
Fixes: 34d1dc17ce97 ("fpga manager: Add Altera CvP driver")
Signed-off-by: Andreas Puhm
Signed-off-by: Anatolij Gustschin
---
Changes in
The current plan is for these to go in via the ARM tree once appropriate
Reviews/Acks have been given.
This series adds drivers for the L2 cache and DDR RAM ECC functionality as
found on the MV78230/MV78x60 SoCs. Jan has tested these changes with the
MV78460 (on a custom board with a DDR3 ECC DIMM
> > +int kernel_unmap_pages_in_pgd(pgd_t *pgd, unsigned long address,
> > + unsigned long numpages)
> > +{
> > + int retval;
> > +
> > + /*
> > +* The typical sequence for unmapping is to find a pte through
> > +* lookup_address_in_pgd() (ideally, it should never
The aurora cache on the Marvell Armada-XP SoC supports the same tag
parity features as the other l2x0 cache implementations.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_PARITY_EN]
Signed-off-by: Jan Luebbe
---
arch/arm/mm/cache-l2x0.c | 7 +++
1
From: Jan Luebbe
We already have wrappers for x8 and x16, so add the missing x32 one.
Signed-off-by: Jan Luebbe
Reviewed-by: Borislav Petkov
Signed-off-by: Chris Packham
---
drivers/edac/debugfs.c | 11 +++
drivers/edac/edac_module.h | 5 +
2 files changed, 16 insertions(+)
Hi Kees,
On Sun, 28 Oct 2018 19:13:26 -0700
Kees Cook wrote:
> On Fri, Oct 12, 2018 at 2:22 AM, Boris Brezillon
> wrote:
> > On Fri, 12 Oct 2018 11:19:52 +0200
> > Arnd Bergmann wrote:
> >
> >> On Fri, Oct 12, 2018 at 11:16 AM Boris Brezillon
> >> wrote:
> >> >
> >> > Hi Arnd,
> >> >
> >>
During simultaneous running of playback and capture, we
got hit by incorrect value write on common register. This was due
to race condition between 2 streams.
Fixing this by locking the common register access.
Signed-off-by: Akshu Agrawal
---
sound/soc/amd/acp-pcm-dma.c | 29
On Sat, 27 Oct 2018 at 08:23, Julia Lawall wrote:
>
> The clk_ops structure is only stored in the ops field of a
> clk_init_data structure. This field is const, so the clk_ops
> structure can be const as well.
>
> Identified and transformed using Coccinelle.
>
> Signed-off-by: Julia Lawall
>
> -
On 23. 10. 18, 15:21, zhong jiang wrote:
> tx_empty is not used after setting its value. It is safe to remove
> the unused variable.
>
> Signed-off-by: zhong jiang
Reviewed-by: Jiri Slaby
> ---
> drivers/tty/serial/pch_uart.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers
SuBin
'onecell' is malloced in clk_boston_setup(), but not be freed
before leaving from the error handling cases.
Signed-off-by: Yi Wang
---
drivers/clk/imgtec/clk-boston.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imgtec/clk-boston.c b/drivers/clk/img
Hello!
On 10/29/2018 11:04 AM, Yi Wang wrote:
'onecell' is malloced in clk_boston_setup(), but not be freed
Is not freed.
before leaving from the error handling cases.
Signed-off-by: Yi Wang
[...]
MBR, Sergei
On Mon 29-10-18 13:16:16, miles.c...@mediatek.com wrote:
> From: Miles Chen
>
> The kbuf used by page owner is allocated by kmalloc(), which means it
> can use only normal memory and there might be a "out of memory"
> issue when we're out of normal memory.
>
> To solve this problem, use kvmalloc
Hello,
I am currently facing the requirements to trace OS events close to hardware
entry and exit from
interrupt.
There are currently arch-independent events defined for entry/exit from irq
handlers as
registered in Linux (irq_handler_entry, irq_handler_exit),
However that is of course a dif
On Mon 29-10-18 09:07:08, Michal Hocko wrote:
[...]
> Besides that, the following doesn't make much sense to me. It simply
> makes no sense to use vmalloc for sub page allocation regardless of
> HIGHMEM.
OK, it is still early morning here. Now I get the point of the patch.
You just want to (ab)use
Thumb-2 functions have the lowest bit set in the symbol value in the
symtab. When kallsyms are generated for the vmlinux, the kallsyms are
generated from the output of nm, and nm clears the lowest bit.
$ arm-linux-gnueabihf-readelf -a vmlinux | grep show_interrupts
95947: 8015dc89 686 FUNC
'onecell' is malloced in clk_boston_setup(), but is not freed
before leaving from the error handling cases.
Signed-off-by: Yi Wang
---
v2: fix syntax issue in comment, thanks to Sergei.
drivers/clk/imgtec/clk-boston.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --gi
On Sun, Oct 28, 2018 at 05:09:22PM +0100, Geert Uytterhoeven wrote:
> With gcc 4.1:
>
> drivers/regulator/bd718x7-regulator.c: In function ‘bd718xx_probe’:
> drivers/regulator/bd718x7-regulator.c:1020: warning: initialization from
> incompatible pointer type
> drivers/regulator/bd71
Hi,
On Sun, Oct 28, 2018 at 11:45 AM Hans de Goede wrote:
>
> Hi Linus,
>
> On 27-10-18 18:08, Linus Torvalds wrote:
> > Julian, Jiri,
> > On my laptop I'm getting a kernel page fault with the current git
> > tree, and I'm tentatively blaming commit
> >
> >9ee3e06610fd ("HID: i2c-hid: overr
Hi Wenwen,
Sorry for the late reply:
On 19/10/18 17:11, Wenwen Wang wrote:
> In chameleon_parse_cells(), to parse each cell, the descriptor type 'dtype'
> is acquired from the IO memory region pointed by 'p' through readl() in
> get_next_dtype(). Then 'dtype' is checked to see whether it is
> CHA
Hi,
On Sat, Oct 27, 2018 at 11:45 PM Jiri Kosina wrote:
>
> On Sat, 27 Oct 2018, Linus Torvalds wrote:
>
> > I wonder if there is some truly old historical legacy there, ie the old
> > PC keyboard support would have been configurable out only for expert
> > users to avoid errors, and maybe the HI
Hi Peter,
On Friday, October 26, 2018 7:45:29 PM CET Peter Korsgaard wrote:
> > "Federico" == Federico Vaga writes:
> Hi,
>
> >> > - } else
> >> > + } else {
> >> >
> >> > msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
> >> >
> >> > + }
> >>
>
On Sun, Oct 21, 2018 at 04:12:10PM +0200, Peter Korsgaard wrote:
> On Mon, Jun 25, 2018 at 6:14 PM Federico Vaga wrote:
> >
> > If the Interrupt Flag (IF) is not set, we should not handle the IRQ:
> > - the line can be shared with other devices
> > - it can be a spurious interrupt
> >
> > To avoid
Yeah, a no-op pkey_alloc flag tied to this patch to provide a way to
detect if pkey state is preserved on fork, since kernels without the
patch would report EINVAL. Something like
PKEY_ASSERT_FORK_INHERIT_STATE would make sense. Otherwise, it's
going to be quite painful to adopt this in userspace s
/linux/commits/Vincent-Whitchurch/ARM-module-Fix-function-kallsyms-on-Thumb-2/20181029-162842
base: git://git.armlinux.org.uk/~rmk/linux-arm.git for-next
config: i386-randconfig-x000-201843 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to
On Mon, Oct 29, 2018 at 11:59:59AM +0530, Ashish Mhetre wrote:
> From: Alex Van Brunt
>
> Accessed bit is used to age a page and in generic implementation there is
> flush_tlb while clearing the accessed bit.
> Flushing a TLB is overhead on ARM64 as access flag faults don't get
> translation tabl
On Mon 29-10-18 16:17:52, Balbir Singh wrote:
[...]
> I wonder if alloc_pool_huge_page() should also trim out it's logic
> of __GFP_THISNODE for the same reasons as mentioned here. I like
> that we round robin to alloc the pool pages, but __GFP_THISNODE
> might be an overkill for that case as well.
Add on-board LED support for Rock960 board based on the following
standard used by rest of the 96Boards:
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger
Add on-board LED support for Ficus board based on the following
standard used by other 96Boards:
red:user1 default-trigger: heartbeat
red:user2 default-trigger: mmc0/disk-activity (onboard-storage)
red:user3 default-trigger: mmc1 (SD-card)
red:user4 default-trigger: none, panic-indicator
red:w
On Thu, Oct 25, 2018 at 06:22:51PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:39 PM Maxime Ripard
> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:33PM +0530, Jagan Teki wrote:
> > > The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
> > > on the one on A31.
> > >
> > > Add A64
This patchset standardizes the onboard LEDs on 96Boards by maintaining
common labels and triggers as below:
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity (onboard-storage)
green:user3 default-trigger: mmc1 (SD card)
green:user4 default-trigger: none, pa
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger
On Thu, Oct 25, 2018 at 06:51:14PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:40 PM Maxime Ripard
> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:34PM +0530, Jagan Teki wrote:
> > > The A64 has a MIPI-DSI block which is similar to A31
> > > without mod clock.
> > >
> > > So, add dsi node
Hi Thierry,
What is the use case for the mailbox driver? What kind of entity will be
there consuming sent messages and sending messages to kernel?
--Pekka
On 10/26/2018 02:16 PM, Thierry Reding wrote:
From: Thierry Reding
Hi everyone,
this is a reworked version of Mikko's earlier proposal
Hi David,
On Mon, 29 Oct 2018 15:33:34 +1100 Stephen Rothwell
wrote:
>
> Hi Al, David,
>
> These have returned, so I have disabled CONFIG_SAMPLE_VFS again.
Here is the current set of errors I git today (this is from a PowerPC
allyesconfig build native compiler on a PowerPC64 LE machine):
samp
On 2018/10/29 上午10:42, Simon Guo wrote:
Hi,
I am using network device pass through mode with qemu x86(-device
vfio-pci,host=:xx:yy.z)
and “intel_iommu=on” in host kernel command line, and it shows the whole guest
memory
were pinned(vfio_pin_pages()), viewed by the “top” RES memory output
On Mon, Oct 29, 2018 at 2:31 PM Manivannan Sadhasivam
wrote:
>
> For all 96Boards, the following standard is used for onboard LEDs.
>
> green:user1 default-trigger: heartbeat
> green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
> green:user3 default-trigger: mmc1 (SD-card)
> green
On Fri, Oct 26, 2018 at 08:13:25PM +0530, Jagan Teki wrote:
> Short transfer write support for DCS and Generic transfer types
> share similar way to process command sequence in DSI block so
> add generic write 2 param transfer type macro so-that the panels
> which are requesting similar transfer ty
On Sat, Oct 27, 2018 at 07:47:36AM +0200, Julia Lawall wrote:
> The clk_ops structure is only stored in the ops field of a
> clk_init_data structure. This field is const, so the clk_ops
> structure can be const as well.
>
> Identified and transformed using Coccinelle.
>
> Signed-off-by: Julia La
I think these changes should cover them all.
David
---
diff --git a/samples/vfs/test-fs-query.c b/samples/vfs/test-fs-query.c
index 511541d12b9e..4635bf1eb3d4 100644
--- a/samples/vfs/test-fs-query.c
+++ b/samples/vfs/test-fs-query.c
@@ -27,6 +27,13 @@
#include
#include
+#ifndef __NR_fsopen
Hi Christophe,
Sorry for the delay, here are some answers from my previous comments.
Maybe you already addressed them, in this case please ignore them.
Also, please run and correct 'checkpatch.pl --strict' issues (mostly
uses of uint8_t instead of u8 but also a warning about the compatible).
Ove
On Mon, Oct 29, 2018 at 2:21 AM Paul E. McKenney wrote:
>
> On Mon, Oct 29, 2018 at 12:10:03AM +0100, Andrea Parri wrote:
> > Hopefully, with Paul's proper email address this time,
> >
> > Andrea
> >
> > On Mon, Oct 29, 2018 at 12:06:27AM +0100, Andrea Parri wrote:
> > > Hi,
> > >
> > > memory-b
UBIFS's recovery code strictly assumes that a deleted inode will never
come back, therefore it removes all data which belongs to that inode
as soon it faces an inode with link count 0 in the replay list.
Before O_TMPFILE this assumption was perfectly fine. With O_TMPFILE
it can lead to data loss
From: Alex Van Brunt
Accessed bit is used to age a page and in generic implementation there is
flush_tlb while clearing the accessed bit.
Flushing a TLB is overhead on ARM64 as access flag faults don't get
translation table entries cached into TLB's. Flushing TLB is not necessary
for this. Cleari
On 29/10/2018 07:34, Viresh Kumar wrote:
> On 26-10-18, 10:30, Daniel Lezcano wrote:
>> On 26/10/2018 06:11, Viresh Kumar wrote:
>>> On 25-10-18, 14:04, Daniel Lezcano wrote:
I think it is actually correct. The example is confusing on what the
numbers are. IIUC, it is:
(after no
Hi Josh,
I also have a few concerns here, as it is not clear to me precisely what is
required from arch code. Is there any documentation I should look at?
On Fri, Oct 26, 2018 at 10:37:04AM -0500, Josh Poimboeuf wrote:
> On Fri, Oct 26, 2018 at 04:21:57PM +0200, Torsten Duwe wrote:
> > Enhance th
On Mon, Oct 29, 2018 at 02:47:11PM +0530, Amit Kucheria wrote:
> On Mon, Oct 29, 2018 at 2:31 PM Manivannan Sadhasivam
> wrote:
> >
> > For all 96Boards, the following standard is used for onboard LEDs.
> >
> > green:user1 default-trigger: heartbeat
> > green:user2 default-trigger: mmc0/disk-act
Hi Sibi,
On 10/26/2018 03:25 PM, Sibi Sankar wrote:
> Add SCM DT node to enable SCM functionality on SDM845.
>
> Signed-off-by: Sibi Sankar
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> b/arch
On Mon, 29 Oct 2018, Liviu Dudau wrote:
> On Sat, Oct 27, 2018 at 07:47:36AM +0200, Julia Lawall wrote:
> > The clk_ops structure is only stored in the ops field of a
> > clk_init_data structure. This field is const, so the clk_ops
> > structure can be const as well.
> >
> > Identified and tran
From: Yuantian Tang
The QorIQ Layerscape SoC has several thermal sensors but the current
driver only supports one.
Massage the code to be sensor oriented and allow the support for
multiple sensors.
Signed-off-by: Yuantian Tang
---
v2:
- update the commit message
- refine the qoriq_tmu_regi
On Mon, Oct 29, 2018 at 5:29 AM Stephen Rothwell wrote:
>
> Hi all,
>
> Today's linux-next merge of the drivers-x86 tree got a conflict in:
>
> drivers/platform/x86/intel_telemetry_debugfs.c
>
> between commit:
>
> f2c4db1bd807 ("x86/cpu: Sanitize FAM6_ATOM naming")
>
> from Linus' tree and co
Hello Mark,
I see we got build warning from 0-Day tests. It seems to me the
bd718x7.c file lacks of inclusion.
I am not sure what has happened as this include was added to bd71837.c
file with commit
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git/commit/?h=for-next&id=df43
Hi Damian,
On Mon, 29 Oct 2018 07:33:19 +0100 Damian Tometzki wrote:
>
> on the site isnt available the new linux-next ?
> Only the old one.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
It seems to be there now (at least for me). Maybe just mirroring delays?
--
Ch
The example contains two values for the capacity currently, 446 in text
and 578 in code. The numbers are all correct but can confuse some of the
readers. This patch tries to explain how the numbers are calculated to
avoid same confusion going forward.
Acked-by: Daniel Lezcano
Signed-off-by: Vires
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger
On Mon, Oct 29, 2018 at 10:00:35AM +0100, Michal Hocko wrote:
> On Mon 29-10-18 16:17:52, Balbir Singh wrote:
> [...]
> > I wonder if alloc_pool_huge_page() should also trim out it's logic
> > of __GFP_THISNODE for the same reasons as mentioned here. I like
> > that we round robin to alloc the pool
Add on-board LED support for Ficus board based on the following
standard used by other 96Boards:
red:user1 default-trigger: heartbeat
red:user2 default-trigger: mmc0/disk-activity (onboard-storage)
red:user3 default-trigger: mmc1 (SD-card)
red:user4 default-trigger: none, panic-indicator
red:w
This patchset standardizes the onboard LEDs on 96Boards by maintaining
common labels and triggers as below:
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity (onboard-storage)
green:user3 default-trigger: mmc1 (SD card)
green:user4 default-trigger: none, pa
Add on-board LED support for Rock960 board based on the following
standard used by rest of the 96Boards:
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger
On Sun, Oct 28, 2018 at 10:11 PM Linus Torvalds
wrote:
>
> Arnd,
> I was kind of hoping/expecting to get an explicit ack for this from
> you, since it's a new architecture.
>
> Good to merge?
Yes.
For the pull request (in case you want to add it to the merge changelog):
I did a thorough review
On Mon, Oct 29, 2018 at 11:40:41AM +0200, Matti Vaittinen wrote:
> Should I just create another patch to you where this inclusion is done again
> or is there some better way to handle this? Can you cherry pick or
> re-apply the commit
Just send another patch, it's easiest.
signature.asc
Descrip
Hi Jianxin,
Jianxin Pan wrote
on Thu, 20 Sep 2018 16:50:49 +0800:
> From: Liang Yang
>
> Add initial support for the Amlogic NAND flash controller which found
> in the Meson-GXBB/GXL/AXG SoCs.
>
> Signed-off-by: Liang Yang
> Signed-off-by: Yixun Lan
> Signed-off-by: Jianxin Pan
> ---
I lo
On Mon, Oct 29, 2018 at 8:30 AM Boris Brezillon
wrote:
> On Sun, 28 Oct 2018 19:13:26 -0700 Kees Cook wrote:
> > On Fri, Oct 12, 2018 at 2:22 AM, Boris Brezillon
> > wrote:
> > > On Fri, 12 Oct 2018 11:19:52 +0200 Arnd Bergmann wrote:
> > > > On Fri, Oct 12, 2018 at 11:16 AM Boris Brezillon
>
On Sun, Oct 28, 2018 at 6:07 PM Al Viro wrote:
>
> On Thu, Sep 13, 2018 at 12:29:02PM +0200, Arnd Bergmann wrote:
>
> > I was hoping that the _ptrarg suffix gives enough warning here,
> > but maybe not. I was careful to only use it in cases that I
> > checked are safe, either using only pointer ar
Hello Dear
Do you have the passion for humanitarian welfare?
Can you devote your time and be totally committed and devoted
to run multi-million pounds humanitarian charity project sponsored
totally by me; with an incentive/compensation accrual to you for
your time and effort and at no cost to yo
Hi Naga,
Naga Sureshkumar Relli wrote on
Tue, 25 Sep 2018 17:50:28 +0530:
> This patch series adds the basic driver support for Arasan NAND Flash
> controller.
> We are reinitiating the patch series by fixing the comments given by Miquel
> and Boris.
> Major changes are exec_op() implementatio
On Fri, Oct 19, 2018 at 02:22:53PM +0100, Jon Hunter wrote:
> From: Jonathan Hunter
>
> The tps6586x driver creates an irqchip that is used by its various child
> devices for managing interrupts. The tps6586x-rtc device is one of its
> children that uses the tps6586x irqchip. When using the tps65
On 29/10/2018 09:25, Ashish Mhetre wrote:
> From: Alex Van Brunt
>
> Accessed bit is used to age a page and in generic implementation there is
> flush_tlb while clearing the accessed bit.
> Flushing a TLB is overhead on ARM64 as access flag faults don't get
> translation table entries cached in
Hi Thierry,
There is typically one entity (aux cpu or a VM running on CCPLEX) owning
the "empty" or producer side of mailbox (iow, waking up on empty) and
another entity owning the "full" or consumer side of mailbox (waking up
on full). An entity should not muck with the interrupts used by the
On Thu, Oct 18, 2018 at 08:17:10PM -0400, Doug Ledford wrote:
> On Thu, 2018-10-18 at 14:01 +0300, Leon Romanovsky wrote:
> > On Thu, Oct 18, 2018 at 10:02:58AM +0200, Gustavo A. R. Silva wrote:
> > > Cast *max_num_sg* to u64 in order to give the compiler complete
> > > information about the proper
On Mon 29-10-18 20:42:53, Balbir Singh wrote:
> On Mon, Oct 29, 2018 at 10:00:35AM +0100, Michal Hocko wrote:
[...]
> > These hugetlb allocations might be disruptive and that is an expected
> > behavior because this is an explicit requirement from an admin to
> > pre-allocate large pages for the fu
DAC may be switched between differential and single-ended output.
Signed-off-by: Kirill Marinushkin
---
sound/soc/codecs/pcm3060.c | 9 +
sound/soc/codecs/pcm3060.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/sound/soc/codecs/pcm3060.c b/sound/soc/codecs/pcm3060.c
index 494d9d
In the initial commit [1], I added differential outputs of the codec as
separate `+` and `-` widgets:
OUTL+
OUTR+
OUTL-
OUTR-
Later, in the commit [2], I added a control to switch the outputs between
differential and single-ended modes. Having this control, the `+` and `-`
separation in widgets s
On Mon, Oct 29, 2018 at 11:04:06AM +0200, Pekka Pessi wrote:
> Hi Thierry,
>
> What is the use case for the mailbox driver? What kind of entity will be
> there consuming sent messages and sending messages to kernel?
This is currently only used for the TCU. I'm sure there could be other
cases, but
On Sun, Oct 28, 2018 at 11:30 PM Wolfram Sang wrote:
>
> On Fri, Oct 19, 2018 at 09:59:57AM +0100, Charles Keepax wrote:
> > irq_create_mapping calls irq_find_mapping internally and will use the
> > found mapping if one exists, so there is no need to manually call this
> > from i2c_smbus_host_noti
On Mon, Oct 29, 2018 at 7:06 PM Tomasz Figa wrote:
>
> Hi Stanimir,
>
> On Mon, Oct 29, 2018 at 6:45 PM Stanimir Varbanov
> wrote:
> >
> > Hi Tomasz,
> >
> > On 10/22/2018 05:48 PM, Tomasz Figa wrote:
> > > Due to complexity of the video decoding process, the V4L2 drivers of
> > > stateful decode
My Beloved,
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my heart. As I informed you earlier, I am (Mrs.) Sharon Smith from Uzbekistan
and a widow to late Martin Smith; I am 63 years old, suffering from long time
Cancer of the breast. From all indications my
On Sun, Oct 28, 2018 at 11:31 PM Wolfram Sang wrote:
>
> On Fri, Oct 19, 2018 at 09:59:58AM +0100, Charles Keepax wrote:
> > The IRQ will be mapped in i2c_device_probe only if client->irq is zero and
> > i2c_device_remove does not clear this. When rebinding an I2C device,
> > whos IRQ provider has
Reorganize get_fdt lookup loop, clearly showing that:
- Nothing is done for table entries that do not have fdt_guid
- Once an entry with fdt_guid is found, break out of the loop
No functional changes.
Signed-off-by: Julien Thierry
Suggested-by: Joe Perches
Cc: Ard Biesheuvel
---
drivers/firmw
On 2018-10-27 14:06, Miguel Ojeda wrote:
> Hi Rasmus,
>
> On Sat, Oct 27, 2018 at 1:24 AM Rasmus Villemoes
> wrote:
>>
>> +/*
>> + * Optional
>
> I did quick check and gcc >= 4.1, clang >= 3.0, icc >= 13 compilers
> seem to support it (or at least recognize it, even if they just ignore
> it), so
On 29/10/2018 10:31, andy.t...@nxp.com wrote:
> From: Yuantian Tang
>
> The QorIQ Layerscape SoC has several thermal sensors but the current
> driver only supports one.
>
> Massage the code to be sensor oriented and allow the support for
> multiple sensors.
>
> Signed-off-by: Yuantian Tang
> -
On Mon, Oct 29, 2018 at 10:45 AM Arnd Bergmann wrote:
> One more general comment: I think this may well be the last new CPU
> architecture we ever add to the kernel. Both nds32 and c-sky are made
> by companies that also work on risc-v, and generally speaking risc-v
> seems to be killing off any o
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