On Thu, May 10, 2018 at 10:45 PM, Levin Du wrote:
> On 2018-05-10 8:50 PM, Robin Murphy wrote:
>>
>> On 10/05/18 10:16, d...@t-chip.com.cn wrote:
>>>
>>> From: Levin Du
>>>
>>> Adding a new gpio controller named "gpio-syscon10" to rk3328, providing
>>> access to the pins defined in the syscon GRF
Radim Krčmář writes:
> 2018-04-16 13:08+0200, Vitaly Kuznetsov:
>> Implement HvFlushVirtualAddress{List,Space} hypercalls in a simplistic way:
>> do full TLB flush with KVM_REQ_TLB_FLUSH and kick vCPUs which are currently
>> IN_GUEST_MODE.
>>
>> Signed-off-by: Vitaly Kuznetsov
>> ---
>> diff --
On Thu, May 10, 2018 at 3:46 PM, wrote:
> From: Thor Thayer
>
> Add qspi_clock
>The qspi_clk frequency is updated by U-Boot before starting Linux.
> Add QSPI interface node.
> Add QSPI flash memory child node.
>Setup the QSPI memory in 2 partitions.
>
> Signed-off-by: Thor Thayer
> ---
On 08/05/18 19:16, Dmitry Osipenko wrote:
GART aperture is shared by all devices, hence there is a single IOMMU
domain and group shared by these devices. Allocation of a group per
device only wastes resources and allowance of having more than one domain
is simply wrong because IOMMU mappings made
Hi Johan,
On Wed, May 09, 2018 at 11:44:18AM +0200, Johan Hovold wrote:
> Add support for controller runtime power management to serdev core. This
> is needed to allow slave drivers to manage the runtime PM state of the
> underlying serial controller when its driver, in turn, implements more
> agg
On Tue, May 8, 2018 at 5:11 PM, Catalin Marinas wrote:
> On Wed, May 02, 2018 at 07:25:17PM +0200, Andrey Konovalov wrote:
>> On Wed, May 2, 2018 at 5:36 PM, Kirill A. Shutemov
>> wrote:
>> > On Wed, May 02, 2018 at 02:38:42PM +, Andrey Konovalov wrote:
>> >> > Does having a tagged address he
On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote:
> Hi,
>
> I need one help.
> I am using i.MX7 Sabre board with kernel version 4.1.15
>
> Let's say I am interested in GPIO number: 21
> I wanted to set CPU affinity for particular GPIO->IRQ number, so I
> tried the below steps:
> root@1
On Thu, 2018-05-10 at 23:51 -0400, Theodore Y. Ts'o wrote:
> On Thu, May 10, 2018 at 08:50:07PM +0100, Dmitry Safonov wrote:
> > random uses __ratelimit() which calls ___ratelimit() with a
> > function
> > name. Depending on !RATELIMIT_MSG_ON_RELEASE it prints how many
> > messages were suppressed
>> Fixes: a09bd81b5413 ("net: aquantia: Limit number of vectors to actually
>> allocated irqs")
>> Signed-off-by: Colin Ian King
>
> This doesn't apply to net-next.
>
Colin, believe thats because you should target to net, not net-next.
BR, Igor
Hi Christoph,
On Fri, 2018-05-11 at 09:59 +0200, Christoph Hellwig wrote:
> Switch to the generic noncoherent direct mapping implementation.
>
> Signed-off-by: Christoph Hellwig
> ---
> arch/arc/Kconfig | 4 +
> arch/arc/include/asm/Kbuild| 1 +
> arch/arc/include/
On Thu, May 10, 2018 at 05:59:00PM +0100, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to spelling mistake in pr_warn message text
>
> Signed-off-by: Colin Ian King
> - pr_warn("VPE loader: elf size too big. Perhaps strip uneeded
> symbols\n");
> + pr_warn(
On 5/11/2018 6:55 AM, Håkon Bugge wrote:
>
>
>> On 10 May 2018, at 18:54, Hal Rosenstock wrote:
>>
>> On 5/10/2018 11:16 AM, Håkon Bugge wrote:
>>>
>>>
On 10 May 2018, at 16:01, Hal Rosenstock wrote:
On 5/10/2018 5:16 AM, Håkon Bugge wrote:
>
>
>> On 9 May 2018, at 13
On 20/04/18 19:37, ernest.zhang wrote:
> When use eMMC as boot device, the eMMC signaling voltage is tied to 1.8v
> fixed output voltage, bios can set o2 sd host controller PCI configuration
> register 0x308 bit4 to 1 to let driver skip 3.3v signaling voltage and
> direct use 1.8v singling voltage
* Johan Hovold [180511 08:09]:
> On Thu, May 10, 2018 at 09:48:31AM -0700, Tony Lindgren wrote:
> > If this solution works for GPS then this should also work for modems
> > that might produce data. And as long as the serdev consumer driver
> > can wake up the UART with pm_runtime_get(&serdev->ctrl
Hello folks,
I think I wrote the title in a misleading way.
Please change the title to something else such as,
"rcu: Report a quiescent state when it's in the state" or,
"rcu: Add points reporting quiescent states where proper" or so on.
On 2018-05-11 오후 5:30, Byungchul Park wrote:
We expect a
Hi Frank,
On 2018-05-10 18:04, Frank Mori Hess wrote:
> On Thu, May 10, 2018 at 4:31 AM, Marek Szyprowski
> wrote:
>> On 2018-05-09 19:48, Frank Mori Hess wrote:
>>> On Wed, May 9, 2018 at 9:19 AM, Marek Szyprowski
>>> wrote:
I understand that pl330 doesn't support real PAUSE, but as it has
On Fri, May 11, 2018 at 06:43:24AM -0400, Oza Pawandeep wrote:
> +void pcie_do_fatal_recovery(struct pci_dev *dev)
> +{
> + struct pci_dev *udev;
> + struct pci_bus *parent;
> + struct pci_dev *pdev, *temp;
> + pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
> + struct aer_b
On 08/05/18 19:16, Dmitry Osipenko wrote:
Introduce iotlb_sync_map() callback that is invoked in the end of
iommu_map(). This new callback allows IOMMU drivers to avoid syncing
on mapping of each contiguous chunk and sync only when whole mapping
is completed, optimizing performance of the mapping
Am Freitag, den 11.05.2018, 13:39 +0100 schrieb Russell King - ARM Linux:
> On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote:
> > Hi,
> >
> > I need one help.
> > I am using i.MX7 Sabre board with kernel version 4.1.15
> >
> > Let's say I am interested in GPIO number: 21
> > I wanted t
From: Eric Long
This patch adds the 'device_config' and 'device_prep_slave_sg' interfaces
for users to configure DMA, as well as adding one 'struct sprd_dma_config'
structure to save Spreadtrum DMA configuration for each DMA channel.
Signed-off-by: Eric Long
Signed-off-by: Baolin Wang
---
Chan
From: Eric Long
This is one preparation patch, we can use default DMA configuration to
implement the device_prep_dma_memcpy() interface instead of issuing
sprd_dma_config().
We will implement one new sprd_dma_config() function with introducing
device_prep_slave_sg() interface in following patch.
On Fri, May 11, 2018 at 05:56:27AM -0700, Tony Lindgren wrote:
> * Johan Hovold [180511 08:09]:
> > On Thu, May 10, 2018 at 09:48:31AM -0700, Tony Lindgren wrote:
> > > If this solution works for GPS then this should also work for modems
> > > that might produce data. And as long as the serdev con
On Fri, 11 May 2018 06:14:07 +0200
Juergen Gross wrote:
> Any reason not sending this patch to the Xen maintainers?
Nope, I guess I should have run the patch through "get_maintainer.pl".
>
> I can take it through the Xen tree. :-)
Thanks!
>
> Reviewed-by: Juergen Gross
Note, I'm going to
On 05/11/2018 04:07 AM, Christoph Hellwig wrote:
> Signed-off-by: Christoph Hellwig
> ---
> include/net/tcp.h | 4 ++--
> net/ipv4/af_inet.c | 3 ++-
> net/ipv4/tcp.c | 31 ++-
> net/ipv6/af_inet6.c | 3 ++-
> 4 files changed, 20 insertions(+), 21 deletion
On Sun, May 06, 2018 at 01:23:50PM +0200, Wolfram Sang
wrote:
> Signed-off-by: Wolfram Sang
> ---
> drivers/ntb/hw/idt/ntb_hw_idt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/ntb/hw/idt/ntb_hw_idt.c b/drivers/ntb/hw/idt/ntb_hw_idt.c
> index 8d98872d0983b7.
Here is an update of:
https://lkml.org/lkml/2018/5/10/346
Where, apart from some minor clean-ups, I've added a cpufreq_enqueue() wrapper
function for cpufreq_update_util() to be used in enqueue_task_fair().
That's because:
- it helps to keep more clean the enqueue_task_fair()
by collecting
Since the refactoring introduced by:
commit 8f111bc357aa ("cpufreq/schedutil: Rewrite CPUFREQ_RT support")
we aggregate FAIR utilization only if this class has runnable tasks.
This was mainly due to avoid the risk to stay on an high frequency just
because of the blocked utilization of a CPU no
Schedutil updates for FAIR tasks are triggered implicitly each time a
cfs_rq's utilization is updated via cfs_rq_util_change(), currently
called by update_cfs_rq_load_avg(), when the utilization of a cfs_rq has
changed, and {attach,detach}_entity_load_avg().
This design is based on the idea that "
When a task is enqueue the estimated utilization of a CPU is updated
to better support the selection of the required frequency.
However, schedutil is (implicitly) updated by update_load_avg() which
always happens before util_est_{en,de}queue(), thus potentially
introducing a latency between estimat
In order for the muxes to be usable with alternate modes,
the alternate mode devices will need also to be able to get
a handle to the muxes on top of the port devices. To make
that possible, the muxes need to be possible to request with
an identifier.
This will change the API so that the mux ident
This adds more complete handling of VDMs and registration of
partner alternate modes, and introduces callbacks for
alternate mode operations.
Only DFP role is supported for now.
Signed-off-by: Heikki Krogerus
---
drivers/usb/typec/tcpm.c | 156 +++
include/li
Instead of the tcpm specific mux states, using the generic
USB type-c connector state values.
Signed-off-by: Heikki Krogerus
---
drivers/usb/typec/mux/pi3usb30532.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/typec/mux/pi3usb30532.c
b/drivers/usb/
Before a device was created for every discovered SVID, but
this will create a device for every discovered mode of every
SVID. The idea is to make it easier to create mode specific
drivers once a bus for the alternate mode is added.
Signed-off-by: Heikki Krogerus
---
drivers/usb/typec/class.c | 1
Introducing a simple bus for the alternate modes. Bus allows
binding drivers to the discovered alternate modes the
partners support.
Signed-off-by: Heikki Krogerus
---
Documentation/ABI/obsolete/sysfs-class-typec | 48 +++
Documentation/ABI/testing/sysfs-bus-typec| 51 +++
Documentation/AB
Hi,
This is the third version of my proposal for more complete alternate
mode support. In this version I'm including a proposal for the mux
handling. Basically, I'm proposing that every supported alternate will
have its own mux handle. That should allow us to support multiple
alternate modes at th
On Fri, May 11, 2018 at 03:24:34AM +, Huaisheng HS1 Ye wrote:
> > From: owner-linux...@kvack.org [mailto:owner-linux...@kvack.org] On Behalf
> > Of Matthew
> > Wilcox
> > On Fri, May 11, 2018 at 12:10:25AM +0800, Huaisheng Ye wrote:
> > > -#define __GFP_DMA((__force gfp_t)___GFP_DMA)
>
From: Colin Ian King
Trivial fix to spelling mistake in dev_err message text
Signed-off-by: Colin Ian King
---
sound/soc/hisilicon/hi6210-i2s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/hisilicon/hi6210-i2s.c b/sound/soc/hisilicon/hi6210-i2s.c
index 07a57209
On Fri, May 11, 2018 at 12:23:22PM +0100, Suzuki K Poulose wrote:
> commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream
>
> Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
> from an erratum 1024718, which causes incorrect updates when DBM/AP
> bits in a page table entry is
On Fri, May 11, 2018 at 12:00:00PM +0200, Jacopo Mondi wrote:
> Add compatible string for R-Car D3 R8A7795 to list of SoCs supported by
> rcar-vin driver.
>
> Signed-off-by: Jacopo Mondi
Reviewed-by: Simon Horman
On Fri, May 11, 2018 at 5:50 AM, Andrea Greco
wrote:
> On 05/08/2018 06:16 PM, Rob Herring wrote:
>> On Sat, May 05, 2018 at 11:34:45PM +0200, Andrea Greco wrote:
>>> From: Andrea Greco
>>>
>>> Add support for com20022I/com20020, memory mapped chip version.
>>> Support bus: Intel 80xx and Motorol
On Fri, 11 May 2018 18:50:04 +0900
Sergey Senozhatsky wrote:
> On (05/11/18 11:17), Dmitry Vyukov wrote:
> >
> > From what I see, it seems that interrupts can be nested:
>
> Hm, I thought that in general IRQ handlers run with local IRQs
> disabled on CPU. So, generally, IRQs don't nest. Was I
Adds hv_evmcs pointer and implement copy_enlightened_to_vmcs12() and
copy_enlightened_to_vmcs12().
prepare_vmcs02()/prepare_vmcs02_full() separation is not valid for
Enlightened VMCS, do full sync for now.
Suggested-by: Ladi Prosek
Signed-off-by: Vitaly Kuznetsov
---
arch/x86/kvm/vmx.c | 428 +
When Enlightened VMCS is in use by L1 hypervisor we can avoid vmwriting
VMCS fields which did not change.
Our first goal is to achieve minimal impact on traditional VMCS case so
we're not wrapping each vmwrite() with an if-changed checker. We also can't
utilize static keys as Enlightened VMCS usag
It's been a while since RFCv1 (https://lwn.net/Articles/741846/). After the
initial submission I decided to implement Enlightened VMCS for KVM on
Hyper-V first and this is now fully merged. Time to resume this work.
This is an initial implementation of Enlightened VMCS for nested Hyper-V on
KVM. U
Per Hyper-V TLFS 5.0b:
"The L1 hypervisor may choose to use enlightened VMCSs by writing 1 to
the corresponding field in the VP assist page (see section 7.8.7).
Another field in the VP assist page controls the currently active
enlightened VMCS. Each enlightened VMCS is exactly one page (4 KB) in
s
From: Ladi Prosek
The state related to the VP assist page is still managed by the LAPIC
code in the pv_eoi field.
Signed-off-by: Ladi Prosek
Signed-off-by: Vitaly Kuznetsov
---
arch/x86/kvm/hyperv.c | 23 +--
arch/x86/kvm/hyperv.h | 4
arch/x86/kvm/lapic.c | 4 ++--
Enlightened VMCS is opt-in. The current version does not contain all
fields supported by nested VMX so we must not advertise the
corresponding VMX features if enlightened VMCS is enabled.
Userspace is given the enlightened VMCS version supported by KVM as
part of enabling KVM_CAP_HYPERV_ENLIGHTENE
Hi Israel,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 94d7dbf108813ea45a91e27e9a8bd231d5a23fa7
commit: 6082d9c9c94a408d7409b5f2e4e42ac9e8b16d0d net/mlx5: Fix
mlx5_get_vector_affinity function
date: 2 weeks ag
From: Colin Ian King
Trivial fix to spelling mistake in DEBUG_REQ message text
Signed-off-by: Colin Ian King
---
drivers/staging/lustre/lustre/ptlrpc/client.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/lustre/lustre/ptlrpc/client.c
b/drivers/staging/lu
Marc
Thanks for looping me in. Comments below.
On 03/05/18 03:02, Jia He wrote:
Hi Marc
Thanks for the review
On 5/2/2018 10:26 PM, Marc Zyngier Wrote:
[+ Suzuki]
On 02/05/18 08:08, Jia He wrote:
From: Jia He
In our armv8a server (QDF2400), I noticed a WARN_ON as follows:
[ 800.20285
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi Linus,
Please pull some more powerpc fixes for 4.17:
The following changes since commit b2d7ecbe355698010a6b7a15eb179e09eb3d6a34:
powerpc/kvm/booke: Fix altivec related build break (2018-04-27 16:36:03 +1000)
are available in the git reposit
On Fri, May 11, 2018 at 01:25:23PM +0200, Niklas Söderlund wrote:
> Hi Jacopo,
>
> Thanks for your work.
>
> On 2018-05-11 12:00:01 +0200, Jacopo Mondi wrote:
> > Describe VIN4 interface for R-Car D3 R8A77995 SoC.
> >
> > Signed-off-by: Jacopo Mondi
>
> Acked-by: Niklas Söderlund
>
> > ---
>
Hi Linus,
Please pull from the tag
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git \
pm-4.17-rc5
with top-most commit ef050374e1eedec45bd260e0ac9eb98f699267d2
Merge branches 'pm-pci' and 'pm-docs'
on top of commit 75bc37fefc4471e718ba8e651aa74673d4e0a9eb
Linux 4.17-rc4
Commit 0fa1c579349f ("of/fdt: use memblock_virt_alloc for early alloc")
inadvertently switched the DT unflattening allocations from memblock to
bootmem which doesn't work because the unflattening happens before
bootmem is initialized. Swapping the order of bootmem init and
unflattening could also f
Kees Cook writes:
> On Wed, May 9, 2018 at 4:43 AM, Michael Ellerman wrote:
>> From: Matthew Wilcox
>>
>> I had neglected to increment the error counter when the tests failed,
>> which made the tests noisy when they fail, but not actually return an
>> error code.
>>
>> Reported-by: Michael Elle
Em Thu, May 10, 2018 at 12:01:59PM +0800, Leo Yan escreveu:
> CoreSight doesn't allocate thread structure for unknown_thread in etm
> auxtrace, so unknown_thread is NULL pointer. If the perf data doesn't
> contain valid tid and then cs_etm__mem_access() uses unknown_thread
> instead as thread hand
Andrew Morton writes:
> On Wed, 9 May 2018 21:43:28 +1000 Michael Ellerman
> wrote:
>> From: Matthew Wilcox
>>
>> I had neglected to increment the error counter when the tests failed,
>> which made the tests noisy when they fail, but not actually return an
>> error code.
>>
>> Reported-by: M
On Fri, May 11, 2018 at 11:34 AM, Alexey Gladkov
wrote:
> From: Djalal Harouni
>
> This is a preparation patch that adds proc_fs_info to be able to store
> different procfs options and informations. Right now some mount options
> are stored inside the pid namespace which makes it hard to change o
Some Arizona CODECs have a small timing window where they will
NAK an I2C transaction if it happens before the boot done bit is
set. This can cause the read of the register containing the boot
done bit to fail until it is set. Since regmap_read_poll_timeout
will abort polling if a read fails it can
commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream
Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table entry is modified without a break-before-make
sequence. The work around is to disable
On Thu, May 10, 2018 at 4:23 PM, Steven Rostedt wrote:
> On Thu, 10 May 2018 07:14:26 +0200
> Dmitry Vyukov wrote:
>
>> > IMPORTANT: if you fix the bug, please add the following tag to the commit:
>> > Reported-by: syzbot+5702a7e6d4a13b3ac...@syzkaller.appspotmail.com
>> > It will help syzbot und
On 11/05/2018 08:59, Christoph Hellwig wrote:
Switch to the generic noncoherent direct mapping implementation for
the nommu dma map implementation.
Signed-off-by: Christoph Hellwig
---
arch/arc/Kconfig| 1 +
arch/arm/Kconfig| 4 +
arch/arm/mm/dma-mapping-nom
On Fri, May 11, 2018 at 11:37 AM, Alexey Gladkov
wrote:
> This allows to hide all files and directories in the procfs that are not
> related to tasks.
/proc/$pid/net and /proc/$pid/task/$tid/net aren't in scope for this
protection, even though they contain information about the whole
network name
Hi John,
On 2018/4/30 16:15, John Garry wrote:
> This series introduces 3 patches, to enable the
> HISILICON_LPC config in the arm64 defconfig
> and also add the relevant LPC DT entries.
>
> For hip06 UART support, we depend on this patch:
> https://lkml.org/lkml/2018/4/27/258
>
> John Garry (3)
Hi John,
On 2018/5/9 15:48, John Garry wrote:
> On 08/05/2018 12:17, Andy Shevchenko wrote:
>> On Tue, 2018-05-08 at 18:27 +0800, John Garry wrote:
>>> This patchset adds ACPI FW support for the UART on
>>> the LPC bus on the Huawei D03 development board.
>>>
>>> It also drops MFD API usage. It's
From: Colin Ian King
There is an earlier check and return if tmp_oh is null, hence the
finaly check to see if it is not null is redundant and can be
replaced with return 1 instead.
Detected by CoverityScan, CIK#1468855 ("Logically dead code")
Signed-off-by: Colin Ian King
---
fs/ocfs2/dlmglue
Hi Leo,
On 2018/5/9 5:02, Leo Yan wrote:
> On Wed, May 09, 2018 at 09:19:13AM +0530, Jassi Brar wrote:
>> On Wed, Apr 4, 2018 at 8:44 AM, Leo Yan wrote:
>>> From: Daniel Lezcano
>>>
>>> The current defconfig is inconsistent as it selects the mailbox and
>>> the clock for the hi6220 and the hi366
On Thu, May 10, 2018 at 04:13:59PM -0700, Luis R. Rodriguez wrote:
> The Linux VFS does not allow a way to set append/immuttable
^^
Typo, in all 3 patches.
> attributes to symlinks, this is just not possible. If this is
> detected inform
On 2018/5/11 18:46, Sowmini Varadhan wrote:
On (05/11/18 15:48), Yanjun Zhu wrote:
diff --git a/net/rds/ib_rdma.c b/net/rds/ib_rdma.c
index e678699..2228b50 100644
--- a/net/rds/ib_rdma.c
+++ b/net/rds/ib_rdma.c
@@ -539,11 +539,17 @@ void rds_ib_flush_mrs(void)
void *rds_ib_get_mr(struct s
Hi Yao,
On 2018/5/11 10:15, Yao Chen wrote:
> Add pcie msi interrupt attribute for hi3660 SOC.
>
> Signed-off-by: Yao Chen
Applied patch 2 into the hisilicon dt tree.
Thanks!
BR,
Wei
> ---
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a
On Tue, Mar 6, 2018 at 5:59 PM, syzbot
wrote:
> Hello,
>
> syzbot hit the following crash on upstream commit
> ce380619fab99036f5e745c7a865b21c59f005f6 (Tue Mar 6 04:31:14 2018 +)
> Merge tag 'please-pull-ia64_misc' of
> git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux
>
> So far this
From: Colin Ian King
Trivial fix to spelling mistake in dprintk message text
Signed-off-by: Colin Ian King
---
drivers/media/dvb-frontends/l64781.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/dvb-frontends/l64781.c
b/drivers/media/dvb-frontends/l64781
> Thanks that helped me to see the problem. On the other hand isn't this a
> bit of an overkill? AFAICS this affects only NEED_PER_CPU_KM which is !SMP
> and DEFERRED_STRUCT_PAGE_INIT makes only very limited sense on UP,
> right?
> Or do we have more such places?
I do not know other places, but m
On Tue, Apr 10, 2018 at 09:04:06PM +0800, Jia-Ju Bai wrote:
> pci_epf_test_write() is never called in atomic context.
>
> The call chain ending up at pci_epf_test_write() is:
> [1] pci_epf_test_write() <- pci_epf_test_cmd_handler()
>
> pci_epf_test_cmd_handler() is set as a parameter of INIT_DELA
From: Zhu Yi
Add Rohm BU21029 resistive touch panel controller support with I2C
interface.
Signed-off-by: Zhu Yi
Signed-off-by: Mark Jonas
Reviewed-by: Heiko Schocher
Reviewed-by: Rob Herring
---
Changes in v3:
- reviewed by Rob Herring
---
Changes in v2:
- make ABS_PRESSURE proportionally
Fill in the few extra bits and annotations needed to make the driver
work properly as a module, and jiggle the Kconfig to expose the
driver-level ARM_CCI_PMU option.
Signed-off-by: Robin Murphy
---
Preserving the current level of configurability does end up allowing a
rather pointless module con
The CCI/CCN drivers are licensed under GPLv2, but the MODULE_LICENSE()
tags are using the bare "GPL" string implying GPLv2 or later. Fix them
to match their actual file license.
Acked-by: Pawel Moll
Acked-by: Suzuki K Poulose
Signed-off-by: Robin Murphy
---
drivers/perf/arm-cci.c | 2 +-
drive
Now that it has been surgically removed from the MCPM port-control code,
we can let the CCI PMU driver be modular. Probing the PMU in the first
place still depends on the bus driver stub being built-in, but it's a
small price to pay compared to the major upheaval of completely reworking
the DT-hand
The CCI PMU driver bears some legacy remnants of the arm_pmu framework
from when it was split in c6f85cb4305b ("bus: cci: move away from
arm_pmu framework"). In particular this perf_pmu_{dis,en}able() dance
around pmu->add which was fixed for arm_pmu in a9e469d1c89b
("drivers/perf: arm_pmu: remove
Hello, Shuah.
On Thu, May 10, 2018 at 01:29:07PM -0600, Shuah Khan wrote:
> Don't pull them yet. If Roman can redo the patches on linux-kselftest next,
> he can pick up the SKIP changes.
So, what we can do is either fix that up during / after the merge
window or creating a separate branch which p
These patches create a top-level function, called at IOMMU initialization,
to create a debugfs directory for the IOMMU. Under this directory drivers
may create and populate-specific directories for their device internals.
Patch 1: general IOMMU enablement
Patch 2: basic AMD enablement to demonstra
Implement a skeleton framework for debugfs support in the
AMD IOMMU.
Signed-off-by: Gary R Hook
---
drivers/iommu/Makefile|5 +
drivers/iommu/amd_iommu_debugfs.c | 39 +
drivers/iommu/amd_iommu_init.c|6 --
drivers/iommu/amd_
Provide base enablement for using debugfs to expose internal data of an
IOMMU driver. When called, create the /sys/kernel/debug/iommu directory.
Emit a strong warning at boot time to indicate that this feature is
enabled.
This function is called from iommu_init, and creates the initial DebugFS
di
On Wed, May 09, 2018 at 06:22:41PM +0800, Lin Huang wrote:
> From: Chris Zhong
>
> We may support training outside firmware, so we need support
> dpcd read/write to get the message or do some setting with
> display.
>
> Signed-off-by: Chris Zhong
> Signed-off-by: Lin Huang
FTR, I've already d
On Tue, May 08, 2018 at 12:04:13AM +0200, Paul Kocialkowski wrote:
> +++ b/arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts
> @@ -0,0 +1,297 @@
> +/*
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
This really should be the first line, and with a C++ style comment, as
in:
// SPDX-License-Identifier: (G
On Fri, May 11, 2018 at 6:34 PM, Lucas Stach wrote:
> Am Freitag, den 11.05.2018, 13:39 +0100 schrieb Russell King - ARM Linux:
>> On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote:
>> > Hi,
>> >
>> > I need one help.
>> > I am using i.MX7 Sabre board with kernel version 4.1.15
>> >
>> >
On Fri, May 11, 2018 at 03:29:13PM +0100, Robin Murphy wrote:
> The CCI PMU driver bears some legacy remnants of the arm_pmu framework
> from when it was split in c6f85cb4305b ("bus: cci: move away from
> arm_pmu framework"). In particular this perf_pmu_{dis,en}able() dance
> around pmu->add which
On Wed, May 09, 2018 at 06:22:42PM +0800, Lin Huang wrote:
> the phy config values used to fix in dp firmware, but some boards
> need change these values to do training and get the better eye diagram
> result. So support that in phy driver.
>
FTR, I've previously reviewed this at
https://chromium-
This patch set implements an IMA namespace data structure that gets
created by first writing a '1' into IMA's securityfs unshare file at
/sys/kernel/security/ima/unshare and then by clone(). This patch set
lays down the foundation for namespacing the different aspects of IMA
(eg. IMA-audit, IMA-mea
From: Mehmet Kayaalp
The iint cache stores whether the file is measured, appraised, audited
etc. This patch moves the IMA_AUDITED flag into the per-namespace
ns_status, enabling IMA audit mechanism to audit the same file each time
it is accessed in a new namespace.
The ns_status is not looked up
On Wed, May 09, 2018 at 06:22:43PM +0800, Lin Huang wrote:
> If want to do training outside DP Firmware, need phy voltage swing
> and pre_emphasis value.
>
> Signed-off-by: Lin Huang
Adding Rob Herring so he has a hope of seeing this.
> ---
> Changes in v2:
> - rebase
>
> Documentation/device
From: Yuqiong Sun
Add a new CONFIG_IMA_NS config option that enables one to create a new IMA
namespace. We do this by writing a file into IMA's new securityfs 'unshare'
file, which will have a new child process get the IMA namespace. We create
the IMA namespace when a user writes a boolean '1' in
From: Mehmet Kayaalp
This patch adds an rbtree to the IMA namespace structure that stores a
namespaced version of iint->flags in ns_status struct. Similar to the
integrity_iint_cache, both the iint ns_struct are looked up using the
inode pointer value. The lookup, allocate, and insertion code is
From: Mimi Zohar
The AUDIT_INTEGRITY_RULE is used for auditing IMA policy rules and
the IMA "audit" policy action. This patch defines AUDIT_INTEGRITY_POLICY
to reflect the IMA policy rules.
Signed-off-by: Mimi Zohar
---
include/uapi/linux/audit.h | 3 ++-
security/integrity/ima/ima_p
Introduce a policy rule attribute called 'ns' that indicates that a rule
is supposed to apply to child namespaces of an IMA namespace. We support
this 'ns' attribute only for IMA-audit for now. IMA-measurement will get
support for this in a future version.
If 'uid=...' appears in a policy rule tha
Em Fri, May 11, 2018 at 02:18:01PM +0300, Adrian Hunter escreveu:
> On 10/05/18 23:47, Arnaldo Carvalho de Melo wrote:
> > Em Thu, May 10, 2018 at 05:19:22PM -0300, Arnaldo Carvalho de Melo escreveu:
> >> Em Thu, May 10, 2018 at 05:15:42PM -0300, Arnaldo Carvalho de Melo
> >> escreveu:
> >>> Em Th
On Thu, May 10, 2018 at 08:47:48PM +0200, Paul Cercueil wrote:
> Also remove the watchdog platform_device from platform.c, since it
> wasn't used anywhere anyway.
Nit: it'd be slightly nicer IMO if the patch body was a superset of the
subject line. It's fine to repeat what the subject says since t
On 05/11/2018 08:32 AM, Tejun Heo wrote:
> Hello, Shuah.
>
> On Thu, May 10, 2018 at 01:29:07PM -0600, Shuah Khan wrote:
>> Don't pull them yet. If Roman can redo the patches on linux-kselftest next,
>> he can pick up the SKIP changes.
>
> So, what we can do is either fix that up during / after t
On Fri, May 11, 2018 at 11:37:04AM +0530, Jagan Teki wrote:
> On Fri, May 11, 2018 at 11:20 AM, Chen-Yu Tsai wrote:
> > On Thu, May 10, 2018 at 10:43 PM, Jagan Teki
> > wrote:
> >> Amarula A64 Relic is Allwinner A64 based IoT device, which support
> >> - Allwinner A64 Cortex-A53
> >> - Mali-400M
On Wed, May 09, 2018 at 06:22:44PM +0800, Lin Huang wrote:
> DP firmware uses fixed phy config values to do training, but some
> boards need to adjust these values to fit for their unique hardware
> design. So if the phy is using custom config values, do software
> link training instead of relying
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