On 07/28/2017 12:02 AM, Mathieu Desnoyers wrote:
- On Jul 27, 2017, at 4:58 PM, Mathieu Desnoyers
mathieu.desnoy...@efficios.com wrote:
- On Jul 27, 2017, at 4:37 PM, Paul E. McKenney paul...@linux.vnet.ibm.com
wrote:
On Thu, Jul 27, 2017 at 11:04:13PM +0300, Avi Kivity wrote:
[..
This series includes:
- Clean up redundant pin data
- Add simple suspend / resume support
- Add a driver for a new SoC
Masahiro Yamada (6):
pinctrl: uniphier: remove unneeded EXPORT_SYMBOL_GPL()
pinctrl: uniphier: fix pin_config_get() for input-enable
pinctrl: uniphier: clean up GPIO
For LD11/20 SoCs (capable of per-pin input enable), the iectrl bit
number matches its pin number. So, this is redundant information.
Instead, we just need a flag to know if the iectrl gating exists or not.
With this refactoring, 5 bits in pin data will be saved.
Signed-off-by: Masahiro Yamada
-
Add pin configuration and pinmux support for UniPhier PXs3 SoC.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/Kconfig | 4 +
drivers/pinctrl/uniphier/Makefile| 1 +
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 989 +++
Save registers lost in the sleep when suspending, and restore them
when resuming.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 178 +++
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 1 +
drivers/pinctrl/uniphier/pinctrl-uniphie
All UniPhier pinctrl drivers are built-in. Exporting the symbol
is meaningless.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
b/drivers/pinctrl/uniphier/
For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are
located across multiple registers. So, the register offset must be
taken into account. Otherwise, wrong input-enable status is displayed.
While we here, rename the macro because it is a base address.
Fixes: aa543888ca8c ("pin
This patch adds tests for UFFD_FEATURE_SIGBUS feature. The
tests will verify signal delivery instead of userfault events.
Also, test use of UFFDIO_COPY to allocate memory and retry
accessing monitored area after signal delivery.
This patch also fixes a bug in uffd_poll_thread() where 'uffd'
is lea
On 7/30/17 12:07 AM, Mike Rapoport wrote:
On Thu, Jul 27, 2017 at 10:18:40PM -0400, Prakash Sangappa wrote:
This patch adds tests for UFFD_FEATURE_SIGBUS feature. The
tests will verify signal delivery instead of userfault events.
Also, test use of UFFDIO_COPY to allocate memory and retry
acces
On 07/29/2017 03:37 AM, Alexandru Gagniuc wrote:
Signed-off-by: Alexandru Gagniuc
---
arch/arc/boot/dts/adaptrum_anarion.dtsi | 107
arch/arc/boot/dts/adaptrum_anarion_fpga.dts | 49 +
2 files changed, 156 insertions(+)
create mode 100644 arch/
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt |
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Reviewed-by: Vivek Gautam
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8
1 file changed, 8 insertions(+)
diff --git
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
The core init is the similar to the existing SoC, however the
clocks and reset lines differ.
S
The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++
1 file changed, 3 insertions(+)
diff --
Hi all,
Changes since 20170728:
The rdma tree gained a build failure so I used the version from
next-20170728.
The drm tree gained a conflict against Linus' tree.
The rcu tree gained a conflict against the tip tree.
Non-merge commits (relative to Linus' tree): 3288
3279 files changed, 115355
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 133 +++-
1 file c
This patch is to implement the new ioctl VFIO_IOMMU_GET_DIRTY_BITMAP
to fulfill the requirement for vfio-mdev device live migration, which
need copy the memory that has been pinned in iommu container to the
target VM for mdev device status restore.
Signed-off-by: Yulei Zhang
---
drivers/vfio/vfi
Add definitions required to enable QMP phy support for IPQ8074.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 124
1 file changed, 124 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b
Presently, the phy pipe clock's name is assumed to be either
usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the
phy lane's number). However, this will not work if an SoC has
more than one instance of the phy. Hence, instead of assuming
the name of the clock, fetch it from the DT.
Revie
v6:
Added 'Reviewed-by: Vivek Gautam ' and fixed
white space issues as mentioned by Vivek.
phy: qcom-qmp: Fix phy pipe clock name
dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
v5:
dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
Renamed phy_phy cl
On Sun, Jul 30, 2017 at 7:45 PM, Joe Perches wrote:
> By default, debug logging is disabled by CC_DEBUG not being defined.
>
> Convert SSI_LOG_DEBUG to use no_printk instead of an empty define
> to validate formats and arguments.
>
> Fix fallout.
>
> Miscellanea:
>
> o One of the conversions now u
On 26/07/17 17:02, Ludovic Desroches wrote:
> When the device is non removable, the card detect signal is often use
use -> used
> for another purpose i.e. muxed to another SoC peripheral or used as a
> GPIO. It could lead to wrong behaviors depending the defaut value of
defaut -> default
> this
On Fri 28-07-17 15:41:47, Greg KH wrote:
> On Fri, Jul 28, 2017 at 03:53:35PM +0200, Michal Hocko wrote:
> > JFYI. We have encountered a regression after applying this patch on a
> > large ppc machine. While the patch is the right thing to do it doesn't
> > work well with the current vmalloc area s
Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness
The drvier is mostly based on s5p-g2d v4l2 m2m driver
And supports various operations from the
Adding required device node for USB3 QMP phy present on
msm8996 chipset to enable support for the same. This phy
provides super speed usb functionality for dwc3 controller
on msm8996.
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 4
arch/arm64/boot/dts/qcom
Add required device node for QMP phy based 3-lane PCIe phy
present on msm8996 chipset to enable support for the same.
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 4 ++
arch/arm64/boot/dts/qcom/msm8996.dtsi| 62
2 files chan
Adding device node for QUSB2 phy and the required infrastructure
to enable support for the same. This phy is used by dwc3 controller
present on msm8996.
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 8 +
arch/arm64/boot/dts/qcom/msm8996.dtsi| 51
Adding required device node for couple of DWC3 controllers
present on msm8996 chipset to enable High speed and Super
speed USB support.
Signed-off-by: Vivek Gautam
---
.../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi| 24 +
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 34 +
Adding patches to enable qusb2 and qmp phy controller for PCIe and USB,
and to enable USB 2.0 and 3.0 support on msm8996 chipset.
Enabling the support for apq8096-db820c board.
Patch series dependencies:
1) Glink-rpm device tree support for 8996:
https://www.spinics.net/lists/linux-arm-msm/msg2
On Sat 29-07-17 16:33:35, kbuild test robot wrote:
> Hi Michal,
>
> [auto build test ERROR on cgroup/for-next]
> [also build test ERROR on v4.13-rc2 next-20170728]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
> url:
> https://github
On Fri 28-07-17 13:48:28, Mike Kravetz wrote:
> On 07/26/2017 03:50 AM, Michal Hocko wrote:
> > Hi,
> > I've just noticed that alloc_gigantic_page ignores movability of the
> > gigantic page and it uses any existing zone. Considering that
> > hugepage_migration_supported only supports 2MB and pgd l
A sockaddr_in structure on the stack getting passed into rdma_ip2gid
triggers this warning, since we memcpy into a larger sockaddr_in6
structure:
In function 'memcpy',
inlined from 'rdma_ip2gid' at include/rdma/ib_addr.h:175:3,
inlined from 'addr_event.isra.4.constprop' at
drivers/infinib
Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness
The drvier is mostly based on s5p-g2d v4l2 m2m driver
And supports various operations from the
On Mon 31-07-17 12:13:33, Wei Wang wrote:
> Ballooned pages will be marked as MADV_DONTNEED by the hypervisor and
> shouldn't be given to the host ksmd to scan.
Could you point me where this MADV_DONTNEED is done, please?
> Therefore, it is not
> necessary to zero ballooned pages, which is very t
On Sat, Jul 29, 2017 at 1:22 AM, Greg KH wrote:
> Ok, do some of these need to go to Linus now for 4.13-final and to the
> stable trees to match up with the 3 that are already proposed for the
> stable trees? If so, which ones?
"fix proc->tsk check" is a fix for "c4ea41ba195d ("binder: use group
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