On Thu, Jul 20, 2017 at 10:39:10AM +0200, Ingo Molnar wrote:
>
> * Daniel Kiper wrote:
>
> > Hey Greg,
> >
> > On Wed, Jul 19, 2017 at 11:43:32AM +0200, Greg Kroah-Hartman wrote:
> > > 4.12-stable review patch. If anyone has any objections, please let me
> > > know.
> >
> > Why did you skip
Kernel text may be located in non-mirror regions (movable zone) when both
address range mirroring feature and KASLR are enabled.
The address range mirroring feature arranges such mirror region into
normal zone and other region into movable zone in order to locate
kernel code and data in mirror reg
;)
On Thu, Jul 20, 2017 at 10:02:33AM +0530, Anup Patel wrote:
> Not allowing No-IOMMU mode for devices already having
> iommu_ops on their bus is very conservative.
>
> We now have IOMMU (such as ARM SMMU) which can bypass
> transcations when IOMMU is not configured for a given
> device. In addition
On 07/20/2017 10:37 AM, H. Nikolaus Schaller wrote:
> Hi,
>
>> Am 18.07.2017 um 21:52 schrieb Sakari Ailus :
>>
>> On Tue, Jul 18, 2017 at 12:53:12PM +, Hugues FRUCHET wrote:
>>>
>>>
>>> On 07/18/2017 02:17 PM, H. Nikolaus Schaller wrote:
Hi,
> Am 18.07.2017 um 13:59 schrieb Ha
Hi, Takashi-san,
That's great!
Actually, SS4 PLUS device is a little different from SS4 device.
I added SS4 PLUS code as below.
Could you try it?
And I still wonder why this issue does not happen on original code though X
value is so large.
--- a/drivers/input/mouse/alps.c
+++ b/drivers/input
Hi Gustavo,
> Remove unnecessary static on local variable hst.
> Such variable is initialized before being used,
> on every execution path throughout the function.
> The static has no benefit and, removing it reduces
> the object file size.
>
> This issue was detected using Coccinelle and the
> f
On Thu 20-07-17 09:24:58, Vlastimil Babka wrote:
> On 07/14/2017 10:00 AM, Michal Hocko wrote:
> > From: Michal Hocko
> >
> > build_all_zonelists has been (ab)using stop_machine to make sure that
> > zonelists do not change while somebody is looking at them. This is
> > is just a gross hack becau
On 20/07/17 08:18, Viresh Kumar wrote:
> On 20-07-17, 01:17, Rafael J. Wysocki wrote:
>> On Thu, Jul 20, 2017 at 12:54 AM, Florian Fainelli
>> wrote:
>>> Hi,
>>>
>>> We have a particular ARM CPU design that is drawing quite a lot of
>>> current upon exit from WFI, and it does so in a way even b
* tip-bot for Tom Lendacky wrote:
> Commit-ID: 5997efb967565e858259401af394e8449629c1f0
> Gitweb: http://git.kernel.org/tip/5997efb967565e858259401af394e8449629c1f0
> Author: Tom Lendacky
> AuthorDate: Mon, 17 Jul 2017 16:10:17 -0500
> Committer: Ingo Molnar
> CommitDate: Tue, 18 Jul
It is no need to find the very beginning of the area within
alloc_vmap_area, which can be done by judging each node during the process
free_vmap_cache miss:
vmap_area_root
/ \
tmp_next U
/ (T1)
tmp
/
... (T2)
/
first
vmap_area_l
2017-07-18 12:20 GMT+02:00 Philippe CORNU :
> Rename the platform driver name from "stm" to "stm32-display"
> for a better readability in /sys/bus/platform/drivers entries.
>
> Note: We keep "stm" as drm_driver.name because it is better
> when using "modetest -M stm ..." (even if recent modetest pa
On Thu, 2017-07-20 at 09:00 +0200, Boris Brezillon wrote:
> Hi Philipp,
>
> On Wed, 19 Jul 2017 17:25:46 +0200
> Philipp Zabel wrote:
>
> > Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
> > reset lines") started to transition the reset control request API calls
> > to
2017-07-18 12:20 GMT+02:00 Philippe CORNU :
> The GCR_PCPOL/DEPOL/VSPOL/HSPOL defines are sufficient to
> describe the HS, VS, DE & PC signal polarities.
>
> Signed-off-by: Philippe CORNU
Reviewed-by: Benjamin Gaignard
> ---
> drivers/gpu/drm/stm/ltdc.c | 28 ++--
> 1 f
2017-07-18 12:20 GMT+02:00 Philippe CORNU :
> Lindent then checkpatch --strict cleanups
>
> Signed-off-by: Philippe CORNU
> ---
> drivers/gpu/drm/stm/ltdc.c | 172
> ++---
> 1 file changed, 85 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/dr
2017-07-18 12:20 GMT+02:00 Philippe CORNU :
> Constify drm funcs structures.
>
> Signed-off-by: Philippe CORNU
Reviewed-by: Benjamin Gaignard
> ---
> drivers/gpu/drm/stm/ltdc.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/g
2017-07-18 12:20 GMT+02:00 Philippe CORNU :
> Use devm_reset_control_get to avoid resource leakage.
> Also use platform_get_resource, which is more usual and
> consistent with platform_get_irq called later.
>
> Signed-off-by: Fabien Dessenne
> Signed-off-by: Philippe CORNU
Note that could be con
2017-07-18 12:20 GMT+02:00 Philippe CORNU :
Commit message is missing here
> Signed-off-by: Philippe CORNU
> ---
> drivers/gpu/drm/stm/ltdc.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index f4ed
2017-07-18 12:20 GMT+02:00 Philippe CORNU :
Please write a commit message
> Signed-off-by: Philippe CORNU
> ---
> drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> b/drivers/gpu/drm/stm/dw_mipi
* Andrew Morton wrote:
> On Wed, 19 Jul 2017 15:54:27 -0700 Davidlohr Bueso wrote:
>
> > On Wed, 19 Jul 2017, Andrew Morton wrote:
> >
> > >I do rather dislike these conversions from the point of view of
> > >performance overhead and general code bloat. But I seem to have lost
> > >that stru
2017-07-20 16:47 GMT+08:00 Minchan Kim :
> Hi Hui,
>
> On Thu, Jul 20, 2017 at 02:39:17PM +0800, Hui Zhu wrote:
>> Hi Minchan,
>>
>> I am sorry for answer late.
>> I spent some time on ubuntu 16.04 with mmtests in an old laptop.
>>
>> 2017-07-17 13:39 GMT+08:00 Minchan Kim :
>> > Hello Hui,
>> >
>>
On Thu, 20 Jul 2017 11:20:20 +0200,
Masaki Ota wrote:
>
> Hi, Takashi-san,
>
> That's great!
>
> Actually, SS4 PLUS device is a little different from SS4 device.
> I added SS4 PLUS code as below.
> Could you try it?
Yes, it works as expected. Feel free to take:
Tested-by: Takashi Iwai
> A
On Wed, Jul 19, 2017 at 01:34:11PM +0200, Rafael J. Wysocki wrote:
> On Wednesday, July 19, 2017 10:56:00 AM Peter Chen wrote:
> > On Tue, Jul 18, 2017 at 07:06:05PM +0200, Rafael J. Wysocki wrote:
> > > On Tue, Jul 18, 2017 at 6:29 AM, Peter Chen wrote:
> > > > On Mon, Jul 17, 2017 at 03:39:07PM
This adds a test to validate mirror functionality with mremap()
system call on shared anon mappings.
Suggested-by: Mike Kravetz
Signed-off-by: Anshuman Khandual
---
tools/testing/selftests/vm/Makefile| 1 +
.../selftests/vm/mremap_mirror_shared_anon.c | 54 +++
> On 2017. Jul 17., at 10:58, Vladimir Murzin wrote:
>
> Hi,
>
> This is follow-up for Christoph complain of overloading the current
> dma coherent infrastructure with the global pool. To address that I
> implemented Robin's idea of the new interface to the global pool and
> wire up it with (on
On 07/06/2017 02:25 PM, Pierre-Yves MORDRET wrote:
> This patchset adds support for the STM32 MDMA controller.
> The Master Direct memory access (MDMA) provides high-speed data transfer
> between memory and memory or between peripherals and memory.
> Contrary to STM32 DMA, the STM32 MDMA controll
The util-linux stable maintenance release v2.30.1 is available at
http://www.kernel.org/pub/linux/utils/util-linux/v2.30
Feedback and bug reports, as always, are welcomed.
Karel
util-linux 2.30.1 Release Notes
===
agetty:
- fix login name DEL/CTRL^U issue
ext4_alloc_file_blocks() does not use its mode parameter. Remove it.
Fixes: 0e8b6879f3c2 ("ext4: refactor ext4_fallocate code")
Signed-off-by: Tahsin Erdogan
---
fs/ext4/extents.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c
* Greg Kroah-Hartman wrote:
> On Thu, Jul 20, 2017 at 10:39:10AM +0200, Ingo Molnar wrote:
> >
> > * Daniel Kiper wrote:
> >
> > > Hey Greg,
> > >
> > > On Wed, Jul 19, 2017 at 11:43:32AM +0200, Greg Kroah-Hartman wrote:
> > > > 4.12-stable review patch. If anyone has any objections, please
* Greg Kroah-Hartman wrote:
> On Thu, Jul 20, 2017 at 10:52:36AM +0200, Ingo Molnar wrote:
> >
> > * Colin King wrote:
> >
> > > From: Colin Ian King
> > >
> > > Add in missing void return type, fixes sparse warning:
> > > "warning: 'hyperv_cleanup()' has implicit return type"
> > >
> > >
Hello!
On 7/20/2017 2:09 AM, Franklin S Cooper Jr wrote:
Hclk is the MCAN's interface clock. However, for OMAP based devices such as
DRA7 SoC family the interface clock is handled by hwmod. Therefore, this
interface clock is managed by hwmod driver via pm_runtime_get and
pm_runtime_put calls. T
On 07/06/2017 02:20 PM, Pierre-Yves MORDRET wrote:
> This patchset adds support for the STM32 DMA multiplexer.
> It allows to map any peripheral DMA request to any channel of the product
> DMAs.
> This IP has been introduced with STM32H7 SoC.
>
Gentle ping for driver review since DT Bindings ha
On 07/18/2017 06:00 PM, Konstantin Khlebnikov wrote:
> Pages are added into lru lists via per-cpu page vectors in order
> to combine these insertions and reduce lru lock contention.
>
> These pending pages cannot be isolated and moved into another lru.
> This breaks in some cases page activation a
Hello!
On 7/20/2017 2:36 AM, Franklin S Cooper Jr wrote:
Add documentation to describe usage of the new fixed transceiver binding.
This new binding is applicable for any CAN device therefore it exist as
Exists.
its own document.
Signed-off-by: Franklin S Cooper Jr
---
.../bindings/ne
Hi Philippe,
On Wednesday 19 Jul 2017 09:11:44 Philippe CORNU wrote:
> On 07/18/2017 03:39 PM, Laurent Pinchart wrote:
> > On Tuesday 18 Jul 2017 13:43:52 Philippe CORNU wrote:
> >
> >> This patch cleans up the Synopsys mipi dsi register list:
> >> - remove unused registers
> >
> > Is the docume
On Thu, Jul 20, 2017 at 02:40:37PM +0530, Keerthy wrote:
>
>
> On Thursday 20 July 2017 12:14 PM, Keerthy wrote:
> >
> >
> > On Wednesday 19 July 2017 04:40 PM, Johan Hovold wrote:
> >> On Tue, Jul 18, 2017 at 04:27:14PM +0530, Keerthy wrote:
> >>> Currently davinci_gpio_irq_setup return value
With X86_FEATURE_TOPOEXT, current logic default to using APIC ID
to calculate cpumask for shared_cpu_map. However, since APIC IDs
are not guarantee to be contiguous for cores across different L3,
such as in family17h system w/ downcore configuration.
This results in incorrect L3 shared_cpu_map.
In
Hello!
On 7/20/2017 2:36 AM, Franklin S Cooper Jr wrote:
Various CAN or CAN-FD IP may be able to run at a faster rate than
what the transceiver the CAN node is connected to. This can lead to
unexpected errors. However, CAN transceivers typically have fixed
limitations and provide no means to di
On Thu, Jul 20, 2017 at 9:18 AM, Viresh Kumar wrote:
> On 20-07-17, 01:17, Rafael J. Wysocki wrote:
>> On Thu, Jul 20, 2017 at 12:54 AM, Florian Fainelli
>> wrote:
>> > Hi,
>> >
>> > We have a particular ARM CPU design that is drawing quite a lot of
>> > current upon exit from WFI, and it does s
Hi Daniel,
On Tue, Jul 18, 2017 at 09:35:03AM +0200, Daniel Vetter wrote:
> On Tue, Jul 18, 2017 at 9:07 AM, Maxime Ripard
> wrote:
> > On Mon, Jul 17, 2017 at 02:57:19PM +0800, Chen-Yu Tsai wrote:
> >> On Mon, Jul 17, 2017 at 2:55 PM, Maxime Ripard
> >> wrote:
> >> > On Fri, Jul 14, 2017 at 04:
On 07/20/2017 10:29 AM, Guochun Mao wrote:
Add "mediatek,mt2712-nor" for nor flash node's compatible.
Signed-off-by: Guochun Mao
---
.../devicetree/bindings/mtd/mtk-quadspi.txt|1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mtd/mtk-quadspi.t
Gently Ping...
It's been two weeks.
> -Original Message-
> From: Dong Aisheng [mailto:aisheng.d...@nxp.com]
> Sent: Wednesday, July 05, 2017 10:35 AM
> To: linux-kernel@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org; daniel.lezc...@linaro.org;
> t...@linutronix.de; shawn...@ke
Hi,
Some user reported that this issue happened from kernel 4.10.7.
Because the below patch was applied on it.
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/?id=0186e6a4e501d39f5f90dd7e5887bc668aef06c4
So, I thought the cause of this issue is this patch.
Original
2017-07-19 20:46 GMT+03:00 Josh Poimboeuf :
>
> After doing some testing, I don't think this approach is going to work
> after all. In addition to forcing the stack frame, it also causes GCC
> to add an unnecessary extra instruction to the epilogue of each affected
> function:
>
> lea-0x10(
On Thursday 20 July 2017 03:20 PM, Johan Hovold wrote:
> On Thu, Jul 20, 2017 at 02:40:37PM +0530, Keerthy wrote:
>>
>>
>> On Thursday 20 July 2017 12:14 PM, Keerthy wrote:
>>>
>>>
>>> On Wednesday 19 July 2017 04:40 PM, Johan Hovold wrote:
On Tue, Jul 18, 2017 at 04:27:14PM +0530, Keerthy w
Pavel,
2017-07-20 10:10 GMT+02:00 Pavel Machek :
> On Mon 2017-07-17 23:28:11, Enric Balletbo i Serra wrote:
>> The minnie devices comes with an AUO B101EAN01 panel which is different
>> from default veyron devices, thus the power on/off timing sequence is
>> slightly different. The datasheet spec
On Thu, Jul 20, 2017 at 03:32:27PM +0530, Keerthy wrote:
> On Thursday 20 July 2017 03:20 PM, Johan Hovold wrote:
> > On Thu, Jul 20, 2017 at 02:40:37PM +0530, Keerthy wrote:
> >> On Thursday 20 July 2017 12:14 PM, Keerthy wrote:
> >>> On Wednesday 19 July 2017 04:40 PM, Johan Hovold wrote:
>
2017-07-19 17:25 GMT+02:00 Philipp Zabel :
> Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
> reset lines") started to transition the reset control request API calls
> to explicitly state whether the driver needs exclusive or shared reset
> control behavior. Convert all dr
On 19/07/2017 23:35, Christophe JAILLET wrote:
Goto the right label in case of error, otherwise there is a leak.
This has been introduced by c5cf9a9147ff. In this patch a goto has not been
updated.
Fixes: c5cf9a9147ff ("drm/i915: Create a kmem_cache to allocate struct i915_priolist
from")
Sign
On Thursday 20 July 2017 03:35 PM, Johan Hovold wrote:
> On Thu, Jul 20, 2017 at 03:32:27PM +0530, Keerthy wrote:
>> On Thursday 20 July 2017 03:20 PM, Johan Hovold wrote:
>>> On Thu, Jul 20, 2017 at 02:40:37PM +0530, Keerthy wrote:
On Thursday 20 July 2017 12:14 PM, Keerthy wrote:
> On
On Mon, Feb 01, 2016 at 04:36:38PM -0800, Eric Dumazet wrote:
> On Tue, 2016-02-02 at 00:08 +0100, Rasmus Villemoes wrote:
>
> > Thanks. (Is there a good way to tell gcc that avg*avg is actually a
> > 32x32->64 multiplication?)
>
> If avg is 32bit, compiler does that for you.
>
> u32 avg = ...
>
Hi!
> 2017-07-20 10:10 GMT+02:00 Pavel Machek :
> > On Mon 2017-07-17 23:28:11, Enric Balletbo i Serra wrote:
> >> The minnie devices comes with an AUO B101EAN01 panel which is different
> >> from default veyron devices, thus the power on/off timing sequence is
> >> slightly different. The datashe
Hi Todor,
On Mon, Jul 17, 2017 at 01:33:30PM +0300, Todor Tomov wrote:
> Add DT binding document for Qualcomm Camera subsystem driver.
>
> CC: Rob Herring
> CC: devicet...@vger.kernel.org
> Signed-off-by: Todor Tomov
> ---
> .../devicetree/bindings/media/qcom,camss.txt | 191
> +
Enable sdmmc on rv1108 evaluation board. Also
add pinctrl for sdmmc controller.
Signed-off-by: Andy Yan
---
arch/arm/boot/dts/rv1108-evb.dts | 4
arch/arm/boot/dts/rv1108.dtsi| 2 ++
2 files changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1
On Mon, Jul 17, 2017 at 01:33:30PM +0300, Todor Tomov wrote:
> Add DT binding document for Qualcomm Camera subsystem driver.
>
> CC: Rob Herring
> CC: devicet...@vger.kernel.org
> Signed-off-by: Todor Tomov
> ---
> .../devicetree/bindings/media/qcom,camss.txt | 191
>
On 20.07.2017 12:45, Vlastimil Babka wrote:
On 07/18/2017 06:00 PM, Konstantin Khlebnikov wrote:
Pages are added into lru lists via per-cpu page vectors in order
to combine these insertions and reduce lru lock contention.
These pending pages cannot be isolated and moved into another lru.
This b
This series adds support for ARM Coresight SoC-600 IP, which implements
Coresight V3 architecture. It also does some clean up of the replicator
driver namings used in the driver to prevent confusions to the user.
The SoC-600 comes with an improved TMC which supports new features,
including Save-Re
With new version of TMC ETR, there are differing set of
features supported by the TMC. Add the capability of a
given TMC ETR for making safer decisions at runtime.
The device configuration register of the TMC (DEVID) lists
some of the capabilities. So, we can detect some of them at
probe. However,
The Coresight SoC 600 TMC ETR supports save-restore feature,
where the values of the RRP/RWP and STS.Full are retained
when it leaves the Disabled state. Hence, we must program the
RRP/RWP and STS.Full to a proper value. For now, set the RRP/RWP
to the base address of the buffer and clear the STS.F
The coresight SoC 600 supports ETR save-restore which allows us
to restore a trace session by retaining the RRP/RWP/STS.Full values
when the TMC leaves the Disabled state. However, the TMC doesn't
have a scatter-gather unit in built.
Also, TMCs have different PIDs in different configurations (ETF,
Coresight SoC 600 defines a new configuration for TMC, Embedded Trace
Streamer (ETS), indicated by 0x3 in MODE:CONFIG_TYPE. This would break
the existing driver which will treat anything other than ETR/ETB as an
ETF. Fix the driver to check the configuration type properly and also
add a warning if
Add the peripheral ids for the Coresight SoC 600 TPIU, replicator
and funnel.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-dynamic-replicator.c | 5 +
drivers/hwtracing/coresight/coresight-funnel.c | 5 +
drivers/hwtracing/cor
This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheablitiy. Set this to Write-back Read and Write-allocate.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
-
TMC in Coresight SoC-600 advertises the AXI address width
in the device configuration register.
Bit 16 - AXIAW_VALID
0 - AXI Address Width not valid
1 - Valid AXI Address width in Bits[23-17]
Bits [23-17] - AXIAW. If AXIAW_VALID = b01 then
0x20 - 32bit AXI address bus
0x28 - 40bit AXI address
The SG unit in the TMC has been removed in Coresight SoC-600.
This is however advertised by DEVID:Bit 24 = 0b1. On the
previous generation, the bit is RES0, hence we can rely on the
DEVID to detect the support.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtr
If the ETR supports split cache encoding (i.e, separate bits for
read and write transfers) unlike the older version (where read
and write transfers use the same encoding in AXICTL[2-5]).
This feature is not advertised and has to be described by the
static mask associated with the device id.
Cc: Ma
Coresight TMC splits 64bit registers into a pair of 32bit registers
(e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-priv.h| 8
drivers/hwtracing/coresight/coresight
Add support for reading a lower and upper 32bits of a register
as a single 64bit register. Also add simplified macros for
direct register accesses.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-priv.h | 29 +++-
1 file chan
Expose the idfilter* registers of the programmable replicator.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-dynamic-replicator.c | 23 ++
1 file changed, 23 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-dynamic-rep
The way how default DMA pool is exposed has changed and now we need to
use dedicated interface to work with it. This patch makes alloc/release
operations to use such interface. Since, default DMA pool is not
handled by generic code anymore we have to implement our own mmap
operation.
Tested-by: An
* Linus Torvalds wrote:
> On Tue, Jul 18, 2017 at 2:21 PM, Dave Airlie wrote:
> >
> > Oh and just FYI, the machine I've tested this on has an mgag200 server
> > graphics card backing the framebuffer, but with just efifb loaded.
>
> Yeah, it looks like it needs special hardware - and particular
Hi,
This is follow-up for Christoph complain [1] of overloading the current
dma coherent infrastructure with the global pool. To address that I
implemented Robin's idea of the new interface to the global pool and
wire up it with (only existent user) ARM NOMMU. Since I have not
heard from Vitaly a
Christoph noticed [1] that default DMA pool in current form overload
the DMA coherent infrastructure. In reply, Robin suggested [2] to
split the per-device vs. global pool interfaces, so allocation/release
from default DMA pool is driven by dma ops implementation.
This patch implements Robin's ide
Expose DBALO,DBAHI and AXICTL registers
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c
b/drivers/hwtracing/coresight/coresight-tmc.c
index aa
The Linux coresight drivers define the programmable ATB replicator as
Qualcomm replicator, while this is designed by ARM. This can cause
confusion to a user selecting the driver. Cleanup all references to
make it explicitly clear. This patch :
1) Replace the compatible string for the replicator :
Use the new helpers for exposing coresight component registers,
choosing the 64bit variants for appropriate registers.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etb10.c | 22
.../hwtracing/coresight/coresight-etm3x-sysfs.
Use the new compatible for ATB programmable replicator in Juno.
Cc: Sudeep Holla
Cc: Mike Leach
Cc: Mathieu Poirier
Cc: Liviu Dudau
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
As per coresight standards, PIDR2 register has the following format :
[2-0] - JEP106_bits6to4
[3]- JEDEC, designer ID is specified by JEDEC.
However some of the drivers only use mask of 0x3 for the PIDR2 leaving
bits [3-2] unchecked, which could potentially match the component for
a differ
Replace the obsolete compatible string for Coresight programmable
replicator with the new one.
Cc: Andy Gross
Cc: David Brown
Cc: linux-arm-...@vger.kernel.org
Cc: Mathieu Poirier
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +-
1 f
From: Matthias Brugger
This patch adds the watchdog driver to the MT6796 SoC.
Signed-off-by: Matthias Brugger
---
arch/arm64/boot/dts/mediatek/mt6797.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
b/arch/arm64/boot/dts/mediatek/mt6797.dt
On Thu, 2017-06-08 at 22:59 +0200, Rasmus Villemoes wrote:
> On Thu, Jun 08 2017, Andy Shevchenko m> wrote:
> > The pointer can't be NULL since it's first what has been done in the
> > pointer().
> > - if (ZERO_OR_NULL_PTR(addr))
> > - return string(buf, end, NULL, spec);/* NULL
From: Matthias Brugger
This patch adds the binding for the MT6797 SoC.
Signed-off-by: Matthias Brugger
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
b/Documentation/devicetr
After adding the clock subsystem to the SOC, the dummy
clock clk32k is not longer needed. Delete it.
Signed-off-by: Matthias Brugger
---
arch/arm64/boot/dts/mediatek/mt6797.dtsi | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
b/arch/arm64/boot/
From: Matthias Brugger
This patch cleans up the binding documentation stating explicitly
the binding and it's fallback for every SoC.
Signed-off-by: Matthias Brugger
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --gi
On 07/19/2017 06:02 PM, Rob Herring wrote:
diff --git a/drivers/media/v4l2-core/v4l2-async.c
b/drivers/media/v4l2-core/v4l2-async.c
index 851f128eba22..0a385d1ff28c 100644
--- a/drivers/media/v4l2-core/v4l2-async.c
+++ b/drivers/media/v4l2-core/v4l2-async.c
@@ -47,9 +47,7 @@ static bool match_fw
Replace the obsolete compatible string for Coresight programmable
replicator with the new one.
Cc: Andy Gross
Cc: David Brown
Cc: linux-arm-...@vger.kernel.org
Cc: Mathieu Poirier
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +-
1
On Wed 19-07-17 10:26:45, Ross Zwisler wrote:
> On Wed, Jul 19, 2017 at 05:33:14PM +0200, Jan Kara wrote:
> > On Wed 28-06-17 16:01:50, Ross Zwisler wrote:
> > > Another major change is that we remove dax_pfn_mkwrite() from our fault
> > > flow, and instead rely on the page fault itself to make the
On 7/19/2017 7:04 PM, Logan Gunthorpe wrote:
>
>
> On 18/07/17 11:57 PM, Michael Ellerman wrote:
>> Seems fair enough, have you tested it at all?
>
> It's only been compile tested and the kbuild robot has beat up on it a bit.
>
Looks like the patch set does not compile on PPC (.config generated
Commit-ID: 11d8b05855f3749bcb6c57e2c4052921b9605c77
Gitweb: http://git.kernel.org/tip/11d8b05855f3749bcb6c57e2c4052921b9605c77
Author: Arnd Bergmann
AuthorDate: Wed, 19 Jul 2017 14:52:59 +0200
Committer: Ingo Molnar
CommitDate: Thu, 20 Jul 2017 10:46:23 +0200
perf/x86: Shut up false-po
Commit-ID: 5623452a0eaec1d44cc9f0770444a48847c9953f
Gitweb: http://git.kernel.org/tip/5623452a0eaec1d44cc9f0770444a48847c9953f
Author: Arnd Bergmann
AuthorDate: Wed, 19 Jul 2017 14:53:01 +0200
Committer: Ingo Molnar
CommitDate: Thu, 20 Jul 2017 10:46:24 +0200
x86/fpu/math-emu: Avoid bo
Commit-ID: 75e2f0a6b16141cb347f442033ec907380d4d66e
Gitweb: http://git.kernel.org/tip/75e2f0a6b16141cb347f442033ec907380d4d66e
Author: Arnd Bergmann
AuthorDate: Wed, 19 Jul 2017 14:53:00 +0200
Committer: Ingo Molnar
CommitDate: Thu, 20 Jul 2017 10:46:24 +0200
x86/fpu/math-emu: Fix poss
From: Steffen Trumtrar
Add binding documentation for the Freescale RNGC found on
some i.MX2/3 SoCs.
Signed-off-by: Steffen Trumtrar
Signed-off-by: Martin Kaiser
---
Changes in v4:
none
Changes in v3:
- add compatible string for imx35
- remove imx5 from the commit message,
I couldn't
The physical size of the panel is 105.5 (W) x 67.2 (H) x 4.05 (D) mm
but the active display area is 95.04 (W) x 53.856 (H) mm.
The width and height should be set to the active display area.
Signed-off-by: Jonathan Liu
---
drivers/gpu/drm/panel/panel-simple.c | 4 ++--
1 file changed, 2 insertio
From: Steffen Trumtrar
The driver is ported from Freescales Linux git and can be
found in the
vendor/freescale/imx_2.6.35_maintain
branch.
According to that code, the RNGC is found on Freescales i.MX3/5 SoCs.
The i.MX2x actually has an RNGB, which has no driver implementation
in Freesc
cp->cp_send_gen is treated as a normal variable, although it may be
used by different threads.
This is fixed by using {READ,WRITE}_ONCE when it is incremented and
READ_ONCE when it is read outside the {acquire,release}_in_xmit
protection.
Normative reference from the Linux-Kernel Memory Model:
From: Steffen Trumtrar
Add a devicetree entry for the Random Number Generator Version C (RNGC).
Signed-off-by: Steffen Trumtrar
Signed-off-by: Martin Kaiser
---
Changes in v4:
none
Changes in v3:
- remove clock-names from dtsi
Changes in v2:
- remove interrupt-names from dtsi
arch/ar
From: Colin Ian King
The function v4l2_fwnode_endpoint_parse_csi1_bus does not need to be
in global scope, so make it static. Also reformat the function arguments
as adding the static keyword made one of the source lines more than 80
chars wide and checkpatch does not like that.
Cleans up spars
Commit-ID: 0bc73048d7baecf94117d1a948853a627e6ba5c8
Gitweb: http://git.kernel.org/tip/0bc73048d7baecf94117d1a948853a627e6ba5c8
Author: Arnd Bergmann
AuthorDate: Wed, 19 Jul 2017 14:53:06 +0200
Committer: Ingo Molnar
CommitDate: Thu, 20 Jul 2017 10:46:25 +0200
x86/platform/intel-mid: Fi
On Thu, 2017-06-08 at 23:45 +0200, Arnd Bergmann wrote:
> On Thu, Jun 8, 2017 at 11:25 PM, Andy Shevchenko
> wrote:
> > On Thu, Jun 8, 2017 at 11:42 PM, Rasmus Villemoes
> > wrote:
> > > On Thu, Jun 08 2017, Andy Shevchenko
> > > wrote:
> > > > On Thu, Jun 8, 2017 at 9:41 PM, Alexandre Belloni
>
Commit-ID: d460131dd50599e0e9405d5f4ae02c27d529a44a
Gitweb: http://git.kernel.org/tip/d460131dd50599e0e9405d5f4ae02c27d529a44a
Author: Arnd Bergmann
AuthorDate: Wed, 19 Jul 2017 14:53:03 +0200
Committer: Ingo Molnar
CommitDate: Thu, 20 Jul 2017 10:46:24 +0200
x86/build: Silence the bui
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