On 31/05/17 17:06, Bartosz Golaszewski wrote:
> This series is a follow-up to [1].
>
> Some users of irq_alloc_generic_chip() are modules which can be
> removed (e.g. gpio-ml-ioh) but have no means of freeing the allocated
> generic chip.
>
> Last time it was suggested to provide irq_destroy_gene
On Wed, Jun 21, 2017 at 12:01 PM, Jeffy Chen wrote:
> We used to enable wakeup for cros-ec-spi devices unconditionally.
> Now we are using the more generic wakeup-source property to enable it.
Using wakeup-source property is still enabling this unconditionally.
What do you exactly mean here?
>
On Fri, Jun 16, 2017 at 01:54:36PM -0500, Tom Lendacky wrote:
> Add warnings to let the user know when bounce buffers are being used for
> DMA when SME is active. Since the bounce buffers are not in encrypted
> memory, these notifications are to allow the user to determine some
> appropriate actio
Remove the error handling of bridge_node because the bridge_node is
optional.
For example, In case of Exynos SoC, a bridge device such as mDNIe and
MIC could be placed between Display Controller and MIPI DSI device but
the bridge device is optional.
Signed-off-by: Hoegeun Kwon
---
Hi all,
Than
On Wed, Jun 21, 2017 at 06:01:48PM +0800, Jeffy Chen wrote:
> Use generic wakeup-source property to enable spi device wakeup.
If this is a generic property shouldn't it be in the driver core rather
than individual subsystems?
signature.asc
Description: PGP signature
On 21/06/17 10:00, Jiancheng Xue wrote:
From: Pengcheng Li
Add inno-usb2-phy driver for hi3798cv200 SoC.
Signed-off-by: Pengcheng Li
Signed-off-by: Jiancheng Xue
---
drivers/phy/Kconfig | 10 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-hisi-inno-usb2.c | 28
On Wed, 2017-05-31 at 01:07 -0300, Fabio Estevam wrote:
> On Tue, May 30, 2017 at 12:57 PM, Leonard Crestez
> wrote:
> >
> > From: Octavian Purdila
> >
> > This fixes an issue with imx6ull where setting the frequency to
> > 528Mhz
> > would actually set the ARM clock to 324Mhz.
> >
> > Signed-
On Wed, Jun 21, 2017 at 12:04:54AM +0200, Thomas Gleixner wrote:
> On Tue, 20 Jun 2017, Daniel Lezcano wrote:
> > The first patch adds the IRQF_TIMER flag to the timers which are percpu in
> > order to discard any timing measurement when the interrupt is coming from a
> > timer. All the timers chan
On Fri, 2017-06-16 at 16:33 +0200, Matthias Brugger wrote:
>
> On 16/06/17 15:45, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> >
> > Signed-off-by: YT Shen
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt2712-evb.dts |
On Wed, 2017-06-21 at 09:20 +, Zhang, Tina wrote:
> Thanks for all the comments. I'm planning to cook the next version of
> this patch set
How about posting only this patch instead of the whole series until
we've settled the interfaces?
> Could the following two works?
> #define VFIO_DEVICE_F
On 21/06/17 11:52, Bhushan Shah wrote:
On Wed, Jun 21, 2017 at 10:37:43AM +0100, Daniel Thompson wrote:
On 21/06/17 06:31, Bhushan Shah wrote:
In the lm3630a_chip_init we try to write to 0x50 register, which is
higher value then the max_register value, this resulted in regmap_write
return -EIO.
On Wed, Jun 21, 2017 at 10:37:43AM +0100, Daniel Thompson wrote:
> On 21/06/17 06:31, Bhushan Shah wrote:
> > In the lm3630a_chip_init we try to write to 0x50 register, which is
> > higher value then the max_register value, this resulted in regmap_write
> > return -EIO.
> >
> > Fix this by bumping
On 06/21/2017 03:31 AM, Jarkko Sakkinen wrote:
Consolidated all the "manual" TPM startup code to a single function
in order to make code flows a bit cleaner and migrate to tpm_buf.
Signed-off-by: Jarkko Sakkinen
Tested-by: Stefan Berger
FYI:
swtpm chardev --vtpm-proxy --tpmstate dir=/tmp
The 'rep' prefix suffers for a relevant "setup cost"; as a result
string copies with unrolled loops are faster than even
optimized string copy using 'rep' variant, for short string.
This change updates __copy_user_generic() to use the unrolled
version for small string length. The threshold length
The patch
ASoC: fsl: mpc5200_dma: remove unused psc_dma
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to L
The patch
ASoC: stm32: Add DT bindings for SPDIFRX interface
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent
The patch
ASoC: stm32: Add SPDIFRX support
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
t
The patch
spi/bcm63xx: Fix checkpatch warnings
has been applied to the spi tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
On Tue, Jun 20, 2017 at 9:48 PM, Theodore Ts'o wrote:
> Tahsin, when you think we've closed on the reviews, could you send out
> a complete set of all of the patches on a new mail thread, using git
> send-email so I can make sure I'm grabbing the final version of all of
> the patches in this patch
On Tue, Jun 20, 2017 at 07:07:10PM -0400, Zi Yan wrote:
> From: Zi Yan
>
> This patch adds thp migration's core code, including conversions
> between a PMD entry and a swap entry, setting PMD migration entry,
> removing PMD migration entry, and waiting on PMD migration entries.
>
> This patch ma
On Wed, Jun 21, 2017 at 12:53:03PM +0300, Kirill A. Shutemov wrote:
> > > > > > On Thu, Jun 15, 2017 at 05:52:22PM +0300, Kirill A. Shutemov wrote:
> > > > > > > We need an atomic way to setup pmd page table entry, avoiding
> > > > > > > races with
> > > > > > > CPU setting dirty/accessed bits. Th
Hi!
> > > > I think tglx had a plan for offsetting the time at some point so 32-bit
> > > > platform can pass 2038 properly.
> > >
> > > Yes, but there are still quite some issues to solve there:
> > >
> > > 1) How do you tell the system that it should apply the offset in the
> > >
What these architectures declare is the same as what can be found in
asm-generic/vga.h. So use that header instead.
Signed-off-by: Jiri Slaby
Acked-by: Max Filippov
Cc: Michal Simek
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: "H. Peter Anvin"
Cc: Chris Zankel
Cc: x...@kernel.org
Cc: linux-xte..
Provided the architectures do not need any special handling (they seem
not to support vga at all, actually), there is no need to have an
empty vga.h. Let them refer to the generic one instead.
Signed-off-by: Jiri Slaby
Acked-by: Geert Uytterhoeven
Acked-by: Martin Schwidefsky
Cc: David Howells
The ELM node in dm816x.dtsi needs to declare the correct compatible
value here as per the binding only one value is correct, and the current
driver handles it correctly. We then add pinmux information for the
NAND found on the EVM so that we do not rely on the ROM to do this for
us, and also so th
From: Mihail Grigorov
Commit 599c376c4932 ("ARM: dts: Fix gpio interrupts for dm816x")
corrected some problems with the MMC. However, it gets the write
protect pin backwards. It needs to be ACTIVE_HIGH not ACTIVE_LOW.
Cc: Rob Herring
Cc: Mark Rutland
Cc: Russell King
Cc: Tony Lindgren
Sign
A wide variety of TI platforms support NAND via the
CONFIG_MTD_NAND_OMAP2 driver (and related BCH options), so enable this.
In addition, multi_v7_defconfig supports the dm8168-evm and that
supports root being on a SATA drive, so build the DM816 AHCI driver into
the resulting kernel as well.
Cc: Ru
On 15.6.2017 20:54, Javier Martinez Canillas wrote:
> The at24 driver allows to register I2C EEPROM chips using different vendor
> and devices, but the I2C subsystem does not take the vendor into account
> when matching using the I2C table since it only has device entries.
>
> But when matching us
On 15.6.2017 20:54, Javier Martinez Canillas wrote:
> The at24 driver allows to register I2C EEPROM chips using different vendor
> and devices, but the I2C subsystem does not take the vendor into account
> when matching using the I2C table since it only has device entries.
>
> But when matching us
On Tue, Jun 20, 2017 at 07:07:11PM -0400, Zi Yan wrote:
> @@ -1220,6 +1238,9 @@ int do_huge_pmd_wp_page(struct vm_fault *vmf, pmd_t
> orig_pmd)
> if (unlikely(!pmd_same(*vmf->pmd, orig_pmd)))
> goto out_unlock;
>
> + if (unlikely(!pmd_present(orig_pmd)))
> + g
On Jun 20 2017 or thereabouts, Andrew Duggan wrote:
> The F54 driver is currently only using the first 6 bytes of F54 so there
> is no need to read all 27 bytes. Some Dell systems
> (Dell XP13 9333 and similar) have an issue with the touchpad or I2C bus
> when readiing reports larger then 16 bytes.
There is code duplicated over all architecture's headers for
futex_atomic_op_inuser. Namely op decoding, access_ok check for uaddr,
and comparison of the result.
Remove this duplication and leave up to the arches only the needed
assembly which is now in arch_futex_atomic_op_inuser.
This effective
On Mon, Jun 19, 2017 at 04:31:18PM +0200, Andreas Färber wrote:
> Am 19.06.2017 um 15:53 schrieb Daniel Lezcano:
> > On 18/06/2017 22:43, Andreas Färber wrote:
> >> Am 06.06.2017 um 18:33 schrieb Daniel Lezcano:
> >>> On Tue, Jun 06, 2017 at 02:54:02AM +0200, Andreas Färber wrote:
> The Action
In some scenarios, we should set some pins as input/output/pullup/pulldown
when the specified system goes into deep sleep mode, then when the system
goes into deep sleep mode, these pins will be set automatically by hardware.
Usually we can set the "sleep" state to set sleep related config, but on
This patch adds the pin control driver for Spreadtrum SC9860 platform.
Signed-off-by: Baolin Wang
---
Changes since v3:
- Use the generic "bia-pull-up" config.
- Use some generic sleep related config.
Changes since v2:
- Fix some compile warnings.
- Reimplement the pin_config_get() callback
This patch adds the binding documentation for Spreadtrum SC9860 pin
controller device.
Signed-off-by: Baolin Wang
---
Changes since v3:
- Use generic "bias-pull-up" instead of "sprd,pull-up".
- Change subject name.
- Use generic sleep related config.
- Add more explanation for sleep related c
On Wed, Jun 21, 2017 at 12:27:02PM +0100, Catalin Marinas wrote:
> On Wed, Jun 21, 2017 at 12:53:03PM +0300, Kirill A. Shutemov wrote:
> > > > > > > On Thu, Jun 15, 2017 at 05:52:22PM +0300, Kirill A. Shutemov
> > > > > > > wrote:
> > > > > > > > We need an atomic way to setup pmd page table entry
Hi
comments inline
On 21/06/17 10:11, Zhi Mao wrote:
1.fix clock control
- prepare top/main clk in mtk_pwm_probe() function,
it will increase power consumption
and in original code these clocks is only prepeare but never enabled
- pwm clock should be enabled before setting pwm regi
On Tue, 2017-06-20 at 22:58 -0700, Kees Cook wrote:
> The ELF_ET_DYN_BASE position was originally intended to keep loaders
> away from ET_EXEC binaries. (For example, running "/lib/ld-linux.so.2
> /bin/cat" might cause the subsequent load of /bin/cat into where the
> loader had been loaded.) With t
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Email: linux-kernel@vger.kernel.org
--
Hi
It's our birthday and we are celebrating 2 years of our outlet. We'd like to
offer you only 19.95 USD for all styles of Oakley and Ray Ban Sunglasses.
Please visit
On Tue, Jun 20, 2017 at 03:47:59PM -0400, Tejun Heo wrote:
> From 104b4e5139fe384431ac11c3b8a6cf4a529edf4a Mon Sep 17 00:00:00 2001
> From: Nikolay Borisov
> Date: Tue, 20 Jun 2017 21:01:20 +0300
>
> Currently, percpu_counter_add is a wrapper around __percpu_counter_add
> which is preempt safe du
The binding bus/ti-gpmc.txt has been moved to
memory-controllers/omap-gpmc.txt. Update all references to this in
order to make reading and understanding a given binding easier.
Cc: David Woodhouse
Cc: Brian Norris
Cc:Boris Brezillon
Cc: Marek Vasut
Cc: Richard Weinberger
Cc: Cyrille Pitchen
Use the current logging style.
Coalesce formats where appropriate.
Signed-off-by: simran singhal
---
drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c | 34 ++-
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c
The binding says that the compatible string must be "ti,am33xx-elm"
but the code checks only for, and all functioning users set, this as
"ti,am3352-elm" so correct the binding.
Cc: David Woodhouse
Cc: Brian Norris
Cc: Boris Brezillon
Cc: Marek Vasut
Cc: Richard Weinberger
Cc: Cyrille Pitchen
On 21/06/17 10:11, Zhi Mao wrote:
support multiple chip(MT2712, MT7622, MT7623)
This patch does more than add extra SoC support. It also
* adds PWM_CLK_DIV_MAX which really should go into its own patch
* adds mtk_pwm_com_reg which should also go into its own patch
more comments inline
Sign
On 20 June 2017 at 18:09, David Howells wrote:
> James Bottomley wrote:
>
>> Added by
>>
>> commit 436529562df2748fd9918f578205b22cf8ced277
>> Author: David Howells
>> Date: Mon Apr 3 16:07:25 2017 +0100
>>
>> X.509: Allow X.509 certs to be blacklisted
>>
>> Ironically it duplicates a UEFI
On Wed, Jun 21, 2017 at 11:28:00AM +0800, Wei Wang wrote:
> On 06/21/2017 12:18 AM, Michael S. Tsirkin wrote:
> > On Fri, Jun 09, 2017 at 06:41:41PM +0800, Wei Wang wrote:
> > > - if (!virtqueue_indirect_desc_table_add(vq, desc, num)) {
> > > + if (!virtqueue_indirect_desc_table_add(vq, desc, *num)
This driver is for GOODiX GTx5 series touchscreen controllers
such as GT8589, GT7589. This driver designed with hierarchial structure,
for that can be modified to support subsequent controllers easily.
Some zones of the touchscreen can be set to buttons(according to the
hardware). That is why it ha
Andrew Morton writes:
> On Tue, 20 Jun 2017 14:39:57 +0100 Punit Agrawal
> wrote:
>
>>
>> The architecture supports two flavours of hugepages -
>>
>> * Block mappings at the pud/pmd level
>>
>> These are regular hugepages where a pmd or a pud page table entry
>> points to a block of memo
Another deadlock path caused by recursive locking is reported.
This kind of issue was introduced since commit 743b5f1434f5 ("ocfs2:
take inode lock in ocfs2_iop_set/get_acl()"). Two deadlock paths
have been fixed by commit b891fa5024a9 ("ocfs2: fix deadlock issue when
taking inode lock at vfs entry
On 21/06/2017 at 08:34:43 +0200, Pavel Machek wrote:
> Hi!
>
> > > > > I think tglx had a plan for offsetting the time at some point so
> > > > > 32-bit
> > > > > platform can pass 2038 properly.
> > > >
> > > > Yes, but there are still quite some issues to solve there:
> > > >
> > > > 1)
> >
> > The right fix for mainline can be found here.
> > perf/x86/intel: enable CPU ref_cycles for GP counter perf/x86/intel,
> > watchdog: Switch NMI watchdog to ref cycles on x86
> > https://patchwork.kernel.org/patch/9779087/
> > https://patchwork.kernel.org/patch/9779089/
>
> Presumably the
On Tue, Jun 20, 2017 at 03:51:00PM -0400, Rik van Riel wrote:
> On Tue, 2017-06-20 at 21:26 +0300, Michael S. Tsirkin wrote:
> > On Tue, Jun 20, 2017 at 01:29:00PM -0400, Rik van Riel wrote:
> > > I agree with that. Let me go into some more detail of
> > > what Nitesh is implementing:
> > >
> > >
On Mon, Jun 19, 2017 at 10:02 PM, kbuild test robot wrote:
> Hi Xiaowei,
>
> [auto build test ERROR on pci/next]
> [also build test ERROR on v4.12-rc5 next-20170619]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
> url:
> https://githu
Em Wed, Jun 21, 2017 at 10:16:56AM +0200, Milian Wolff escreveu:
> On Mittwoch, 21. Juni 2017 03:07:39 CEST Arnaldo Carvalho de Melo wrote:
> > Hi Millian, can I take this as an Acked-by or Tested-by?
> I have no access to any PowerPC hardware. In principle the code looks
> fine, but that's all I
Ard Biesheuvel wrote:
> > This can be told to skip a particular algorithm for when the caller
> > has one precalculated. The precalculated hash can be passed to
> > is_hash_blacklisted(). This would typically be the case for a signed
> > X.509 message.
>
> This last part se
Hi Linus,
On ven., juin 16 2017, Linus Walleij wrote:
> On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
> wrote:
>
>> This commit makes sure the drivers for the Armada 7K/8K pin controllers
>> are enabled.
>>
>> Reviewed-by: Thomas Petazzoni
>> Signed-off-by: Gregory CLEMENT
>
> Acked-by:
On 06/20/2017 06:49 PM, David Hildenbrand wrote:
> On 20.06.2017 18:44, Rik van Riel wrote:
>> On Mon, 2017-06-12 at 07:10 -0700, Dave Hansen wrote:
>>
>>> The hypervisor is going to throw away the contents of these pages,
>>> right? As soon as the spinlock is released, someone can allocate a
>>>
On 20.06.17 09:49:32, Will Deacon wrote:
> Hi Robert,
>
> On Tue, Jun 20, 2017 at 08:34:39AM +0200, Robert Richter wrote:
> > On 07.06.17 12:50:12, Will Deacon wrote:
> >
> > > Thanks, I've pushed this out as:
> > >
> > > git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
> > > for-
Ping...
> -Original Message-
> From: Dong Aisheng [mailto:aisheng.d...@nxp.com]
> Sent: Tuesday, June 13, 2017 10:56 AM
> To: linux-ser...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> gre...@linuxfoundation.org; jsl...@suse.com; Andy Duan; ste
On 21 June 2017 at 14:49, David Howells wrote:
> Ard Biesheuvel wrote:
>
>> > This can be told to skip a particular algorithm for when the caller
>> > has one precalculated. The precalculated hash can be passed to
>> > is_hash_blacklisted(). This would typically be the case for a
On Wed, Jun 21, 2017 at 2:08 PM, Andrey Konovalov wrote:
> Hi,
>
> I've got the following error report while fuzzing the kernel with syzkaller.
>
> On commit 9705596d08ac87c18aee32cc97f2783b7d14624e (4.12-rc6+).
>
> It might be related to:
> https://groups.google.com/forum/#!topic/syzkaller/ZJaqAi
On 21.06.17 15:00:25, Robert Richter wrote:
> On 20.06.17 09:49:32, Will Deacon wrote:
> > Hi Robert,
> >
> > On Tue, Jun 20, 2017 at 08:34:39AM +0200, Robert Richter wrote:
> > > On 07.06.17 12:50:12, Will Deacon wrote:
> > >
> > > > Thanks, I've pushed this out as:
> > > >
> > > > git://git.k
On Tue 20-06-17 15:12:55, David Rientjes wrote:
[...]
> This doesn't prevent serial oom killing for either the system oom killer
> or for the memcg oom killer.
>
> The oom killer cannot detect tsk_is_oom_victim() if the task has either
> been removed from the tasklist or has already done cgroup_
On Tue, Jun 20, 2017 at 09:06:48PM +0200, Mike Galbraith wrote:
> On Tue, 2017-06-20 at 13:42 -0400, Rik van Riel wrote:
> > On Mon, 2017-06-19 at 04:12 +0200, Frederic Weisbecker wrote:
> > > Although idle load balancing obviously only concern idle CPUs, it can
> > > be a disturbance on a busy noh
Ping.
On Wed, 14 Jun 2017, Nicolas Pitre wrote:
> On Tue, 13 Jun 2017, Ingo Molnar wrote:
>
> > So I'm fine with most of the code movement - let's try this series
> > without any of the more controversial bits which should make future
> > arguments easier.
>
> Here it is. Big diffstat due to c
From: Colin Ian King
The return value ret is unitialized and garbage is being returned
for the three different error conditions when setting up the PCIe
BARs. Fix this by initializing ret to -ENOMEM to indicate that
the BARs failed to be setup correctly.
Detected by CoverityScan, CID#1437563 ("
On Wed, 14 Jun 2017 18:27:58 -0600
Michael Sartain wrote:
> Read/write/open calls weren't handling EINTR in trace-input.c
>
> This patch uses the standard GNU C TEMP_FAILURE_RETRY macro to handle EINTR
> return values, and updates read/write calls in trace-msg.c to match.
I understand that GNU
On 6/20/2017 3:49 PM, Thomas Gleixner wrote:
On Fri, 16 Jun 2017, Tom Lendacky wrote:
+config ARCH_HAS_MEM_ENCRYPT
+ def_bool y
+ depends on X86
That one is silly. The config switch is in the x86 KConfig file, so X86 is
on. If you intended to move this to some generic place outs
On Wed, 14 Jun 2017 18:27:59 -0600
Michael Sartain wrote:
> The tot variable in __do_write and do_read is incremented with the amount read
> / written, but subsequent times through the loop the calls continue to use the
> original data pointer.
>
> Signed-off-by: Michael Sartain
> ---
> trace-
This commit enables the newly introduced Marvell GICP and ICUs driver
for the 64-bit Marvell EBU platforms.
Signed-off-by: Thomas Petazzoni
Acked-by: Marc Zyngier
---
arch/arm64/Kconfig.platforms | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kco
The Marvell ICU unit is found in the CP110 block of the Marvell Armada
7K and 8K SoCs. It collects the wired interrupts of the devices located
in the CP110 and turns them into SPI interrupts in the GIC located in
the AP806 side of the SoC, by using a memory transaction.
Until now, the ICU was conf
Stephen Rothwell writes:
> Today's linux-next merge of the net-next tree got a conflict in:
>
> drivers/net/wireless/marvell/mwifiex/pcie.c
>
> between commit:
>
> c336cc0ee4eb ("PCI: Split ->reset_notify() method into
> ->reset_prepare() and ->reset_done()")
>
> from the pci tree and commit:
Hello,
The Marvell Armada 7K/8K SoCs are composed of two parts: the AP (which
contains the CPU cores) and the CP (which contains most
peripherals). The 7K SoCs have one CP, while the 8K SoCs have two CPs,
doubling the number of available peripherals.
In terms of interrupt handling, all devices in
This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files
to describe the ICU and GICP units, and use ICU interrupts for all
devices in the CP110 blocks.
Signed-off-by: Thomas Petazzoni
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 7 +++
.../boot/dts/marvell/armada-cp1
This commit adds the Device Tree binding documentation for the Marvell
ICU interrupt controller, which collects wired interrupts from the
devices located into the CP110 hardware block of Marvell Armada 7K/8K,
and converts them into SPI interrupts in the GIC located in the AP
hardware block, using t
This commit adds the Device Tree binding documentation for the Marvell
GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
using memory transactions. It is used by the ICU unit in the Marvell
CP110 block to turn wired interrupts inside the CP into SPI interrupts
at the GIC level
Hello,
On Wed, 21 Jun 2017 08:56:24 +0100, Marc Zyngier wrote:
> > +static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
> > +{
> > + struct irq_data *d = irq_get_irq_data(desc->irq);
> > + struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
> > + struct mvebu_icu *ic
On Wed, Jun 21, 2017 at 04:48:06PM +1000, Stephen Rothwell wrote:
> Hi Paul,
>
> After merging the rcu tree, today's linux-next build (x86_64 allnoconfig)
> produced this warning:
>
> kernel/cpu.c: In function 'boot_cpu_state_init':
> kernel/cpu.c:1778:6: warning: unused variable 'cpu' [-Wunused-
This commit adds a simple driver for the Marvell GICP, a hardware unit
that converts memory writes into GIC SPI interrupts. The driver provides
a number of functions to the ICU driver to allocate GICP interrupts, and
get the physical addresses that the ICUs should write to to set/clear
interrupts.
Hi Kalle,
On Wed, 21 Jun 2017 16:29:29 +0300 Kalle Valo wrote:
>
> Thanks, the fix looks good to me. I guess there's nothing I can do at
> the moment and Linus needs to fix this when he pulls from Dave (or
> Bjorn, whichever is the last)?
Right.
--
Cheers,
Stephen Rothwell
Hi Christoph,
On 2017-06-20 15:16, Christoph Hellwig wrote:
On Tue, Jun 20, 2017 at 11:04:00PM +1000, Stephen Rothwell wrote:
git://git.linaro.org/people/mszyprowski/linux-dma-mapping.git#dma-mapping-next
Contacts: Marek Szyprowski and Kyungmin Park (cc'd)
I have called your tree dma-mapping-
> drivers/net/ph/marvell.c
> marvell_set_loopback(struct phy_device *dev, bool enable)
> {
> /* do some device specific setting */
>
>
> return genphy_loopback(dev, enable);
> }
>
> I don't know if this makes sense or not?
Nope, you want something in phy.c like this. N
On Tue, 20 Jun 2017, Andy Lutomirski wrote:
> This patch uses PCID differently. We use a PCID to identify a
> recently-used mm on a per-cpu basis. An mm has no fixed PCID
> binding at all; instead, we give it a fresh PCID each time it's
> loaded except in cases where we want to preserve the TLB,
On Wed, 21 Jun 2017, Thomas Gleixner wrote:
> On Tue, 20 Jun 2017, Andy Lutomirski wrote:
> > + /* Set up PCID */
> > + if (cpu_has(c, X86_FEATURE_PCID)) {
> > + if (cpu_has(c, X86_FEATURE_PGE)) {
> > + cr4_set_bits(X86_CR4_PCIDE);
>
> So I assume that you made sur
Em Wed, Jun 21, 2017 at 01:20:52PM +0300, Adrian Hunter escreveu:
> On 12/06/17 16:56, Arnaldo Carvalho de Melo wrote:
> > Em Mon, Jun 12, 2017 at 04:04:44PM +0300, Adrian Hunter escreveu:
> >> On 26/05/17 11:17, Adrian Hunter wrote:
> >>> Hi
> >>>
> >>> Here are some patches to support Intel PT Po
On Tue, Jun 20, 2017 at 02:33:09PM -0700, kan.li...@intel.com wrote:
> From: Kan Liang
>
> Some users reported spurious NMI watchdog timeouts.
>
> We now have more and more systems where the Turbo range is wide enough
> that the NMI watchdog expires faster than the soft watchdog timer that
> upd
On Wed, 21 Jun 2017, Thomas Gleixner wrote:
> > + for (asid = 0; asid < NR_DYNAMIC_ASIDS; asid++) {
> > + if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) !=
> > + next->context.ctx_id)
> > + continue;
> > +
> > + *new_asid = asid;
> > +
Jia-Ju Bai writes:
> On 06/21/2017 02:11 PM, Kalle Valo wrote:
>> David Miller writes:
>>
>>> From: Jia-Ju Bai
>>> Date: Mon, 19 Jun 2017 10:48:53 +0800
>>>
The driver may sleep under a spin lock, and the function call path is:
netxen_nic_pci_mem_access_direct (acquire the lock by spin
On Tue, Jun 20, 2017 at 10:48:44PM +0200, Arnd Bergmann wrote:
> watchdog_update_cpus() is defined unconditionally, but only used when
> CONFIG_SYSCTL is defined:
>
> kernel/watchdog.c:608:12: error: 'watchdog_update_cpus' defined but not used
> [-Werror=unused-function]
>
> This adds another #i
On 21.06.2017 14:56, Christian Borntraeger wrote:
> On 06/20/2017 06:49 PM, David Hildenbrand wrote:
>> On 20.06.2017 18:44, Rik van Riel wrote:
>>> On Mon, 2017-06-12 at 07:10 -0700, Dave Hansen wrote:
>>>
The hypervisor is going to throw away the contents of these pages,
right? As soon
On Wed, Jun 21, 2017 at 12:40:28PM +, Liang, Kan wrote:
>
> > >
> > > The right fix for mainline can be found here.
> > > perf/x86/intel: enable CPU ref_cycles for GP counter perf/x86/intel,
> > > watchdog: Switch NMI watchdog to ref cycles on x86
> > > https://patchwork.kernel.org/patch/97790
Em Wed, Jun 21, 2017 at 01:17:19PM +0300, Adrian Hunter escreveu:
> +++ b/tools/perf/util/event.h
> @@ -252,6 +252,9 @@ enum auxtrace_error_type {
>PERF_AUXTRACE_ERROR_MAX
> };
> +/* Attribute type for custom synthesized events */
> +#define PERF_TYPE_SYNTH 30
Why don
On 6/20/2017 3:55 PM, Thomas Gleixner wrote:
On Fri, 16 Jun 2017, Tom Lendacky wrote:
Currently there is a check if the address being mapped is in the ISA
range (is_ISA_range()), and if it is then phys_to_virt() is used to
perform the mapping. When SME is active, however, this will result
in t
> The return value ret is unitialized and garbage is being returned
> for the three different error conditions when setting up the PCIe
> BARs. Fix this by initializing ret to -ENOMEM to indicate that
> the BARs failed to be setup correctly.
>
> Detected by CoverityScan, CID#1437563 ("Unitialized
2017-06-21 12:15 GMT+02:00 Arvind Yadav :
> Undo preparation of a clock source, if sti_hqvdp_start_xp70 and
> sti_hqvdp_atomic_check are not successful.
>
> Signed-off-by: Arvind Yadav
Applied on drm-misc-next, thanks,
Benjamin
> ---
> drivers/gpu/drm/sti/sti_hqvdp.c | 3 +++
> 1 file changed,
On 6/21/2017 2:37 AM, Thomas Gleixner wrote:
On Fri, 16 Jun 2017, Tom Lendacky wrote:
Currently there is a check if the address being mapped is in the ISA
range (is_ISA_range()), and if it is then phys_to_virt() is used to
perform the mapping. When SME is active, however, this will result
in th
On 21/06/17 14:54, Sergey Matyukevich wrote:
>> The return value ret is unitialized and garbage is being returned
>> for the three different error conditions when setting up the PCIe
>> BARs. Fix this by initializing ret to -ENOMEM to indicate that
>> the BARs failed to be setup correctly.
>>
>> D
On Wed, Jun 21, 2017 at 1:16 AM, Catalin Marinas
wrote:
> On Wed, Jun 14, 2017 at 06:12:03PM -0700, Thomas Garnier wrote:
>> Ensure the address limit is a user-mode segment before returning to
>> user-mode. Otherwise a process can corrupt kernel-mode memory and
>> elevate privileges [1].
>>
>> The
Commit-ID: 707188f5f2421a304324e6ef3aaf4413cfab0f3d
Gitweb: http://git.kernel.org/tip/707188f5f2421a304324e6ef3aaf4413cfab0f3d
Author: Bartosz Golaszewski
AuthorDate: Wed, 31 May 2017 18:06:56 +0200
Committer: Thomas Gleixner
CommitDate: Wed, 21 Jun 2017 15:53:10 +0200
irq/generic-chip
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