On 20/06/17 14:49, Christoph Hellwig wrote:
> On Wed, May 24, 2017 at 11:24:29AM +0100, Vladimir Murzin wrote:
>> This patch introduces default coherent DMA pool similar to default CMA
>> area concept. To keep other users safe code kept under CONFIG_ARM.
>
> I don't see a CONFIG_ARM in the code, a
Hi,
On jeu., juin 01 2017, Gregory CLEMENT
wrote:
> The new binding for the system controller on cp110 moved the clock
> controller into a subnode. This preliminary step will allow to add gpio
> and pinctrl subnodes.
>
> Reviewed-by: Thomas Petazzoni
> Signed-off-by: Gregory CLEMENT
Applie
On Mon, Jun 19, 2017 at 01:58:53PM -0700, Florian Fainelli wrote:
> On 06/18/2017 04:51 PM, Yury Norov wrote:
> > Hi Florian,
> >
> > Some questions and thoughts inline.
> >
> > Yury
> >
> > On Fri, Jun 16, 2017 at 05:07:42PM -0700, Florian Fainelli wrote:
> >> Define a generic fncpy() implement
Hi,
On Thu, Jun 15, 2017 at 04:38:34PM -0500, Rob Herring wrote:
> On Thu, Jun 15, 2017 at 1:33 PM, Bjorn Andersson
> wrote:
> > On Thu 15 Jun 09:26 PDT 2017, Sebastian Reichel wrote:
> >
> >> Hi,
> >>
> >> On Mon, Jun 12, 2017 at 04:32:03PM -0700, Bjorn Andersson wrote:
> > [..]
> >> > As such i
On Mon, Jun 19, 2017 at 06:43:48PM +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 19, 2017 at 06:18:18PM +0300, Yury Norov wrote:
> > One else thing I forgot to ask - now you have the generic
> > implementation for fncpy(), so do you really need to save arm
> > version of it?
>
> This was co
On 6/13/2017 8:32 AM, Jeffrey Hugo wrote:
On 6/7/2017 1:18 PM, Jeffrey Hugo wrote:
Co-authored-by: Austin Christ
Signed-off-by: Jeffrey Hugo
[V5]
-updated comment to explain the "why" behind the redo check
-fixed panic triggered from active_load_balance_cpu_stop()
[V4]
-restricted active cpu
for each gpio controller
Signed-off-by: Oleksij Rempel
---
arch/arm/boot/dts/imx6dl-riotboard.dts | 61 ++
1 file changed, 61 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts
b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 2cb72824e800..b9ecb3b37
On Mon, Jun 19, 2017 at 04:00:22PM +0200, Thomas Bogendoerfer wrote:
> From: Thomas Bogendoerfer
>
> Provide link partner advertising information.
> Removed testing for gigabit modes, which is useless for a fast ethernet phy.
>
> Signed-off-by: Thomas Bogendoerfer
Reviewed-by: Andrew Lunn
On Tue, 2017-06-20 at 06:55 +0200, Oleksij Rempel wrote:
> On 19.06.2017 13:35, Leonard Crestez wrote:
> > On Mon, 2017-06-19 at 07:02 +0200, Oleksij Rempel wrote:
> > >
> > > One of the Freescale recommended sequences for power off with
> > > external
> > > PMIC is the following:
> > > ...
> > >
Hi,
On 20.6.2017 15:08, Lorenzo Pieralisi wrote:
> commit 01cf9d524ff0 ("microblaze/PCI: Support generic Xilinx AXI PCIe Host
> Bridge IP driver") removed pcibios calls to:
>
> pcibios_setup_bus_self()
> pcibios_setup_bus_devices()
>
> Given that pcibios_fixup_bus() was the only caller of those
Hi,
On lun., juin 12 2017, Gregory CLEMENT
wrote:
> Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.
>
> The CP master being different between Armada 7k and Armada 8k. This
> commit introduces the intermediates files armada-70x0.dtsi and
> armada-80x0.dtsi.
>
> These new files w
Hi,
On lun., juin 12 2017, Gregory CLEMENT
wrote:
> Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs.
>
> The Armada 8K has two CP110 blocks, each having two GPIO controllers.
> However, in each CP110 block, one of the GPIO controller cannot be
> used: in the master CP110, o
On Tue, 2017-06-20 at 07:01 +0200, Oleksij Rempel wrote:
>
> On 19.06.2017 13:35, Leonard Crestez wrote:
> >
> > On Mon, 2017-06-19 at 07:02 +0200, Oleksij Rempel wrote:
> > >
> > > Export pm_power_off_prepare. It is needed to implement power off on
> > > Freescale/NXP iMX6 based boards with ext
Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
1. Errata ID #74
SMMU register alias Page 1 is not implemented
2. Errata ID #126
SMMU doesnt support unique IRQ lines and also MSI for gerror,
eventq and cmdq-sync
The following patchset does software workaround for these two
From: Linu Cherian
Cavium ThunderX2 implementation doesn't support second page in SMMU
register space. Hence, resource size is set as 64k for this model.
Signed-off-by: Linu Cherian
Signed-off-by: Geetha Sowjanya
---
drivers/acpi/arm64/iort.c | 15 ++-
1 files changed, 14 insert
From: Linu Cherian
Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
and PAGE0_REGS_ONLY option is enabled as an errata workaround.
This option when turned on, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets.
SMMU r
From: Geetha Sowjanya
Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
lines for gerror, eventq and cmdq-sync.
SHARED_IRQ option is set as a errata workaround, which allows to share the irq
line by register single irq handler for all the interrupts.
Signed-off-by: Geet
On Fri, May 19, 2017 at 12:57:08PM -0500, Dave Gerlach wrote:
> + .arm
> + .align 3
> +
> +ENTRY(ti_emif_sram)
Will you ever want to have any of this code as Thumb?
> +extern inline void ti_emif_offsets(void)
> +{
"extern inline" is frowned upon in the kernel - any reason this
can't be "
On Tue, Jun 20, 2017 at 02:05:53AM -0700, Hugh Dickins wrote:
> On Mon, 19 Jun 2017, Dave Jones wrote:
> >
> > I hacked up this harness to try and narrow it down more..
> >
> > #!/bin/bash
> >
> > . scripts/taint.sh
> >
> > while [ 1 ];
> > do
> > ./trinity -a64 -C1 -c mmap -N1 --e
Hi,
This patch fix all coding style error in driver/staging/ccree/ssi_aead.c.
From: Jhih-Ming Hunag
Move brace { to previous line for if.
Signed-off-by: Jhih-Ming Hunag
---
drivers/staging/ccree/ssi_aead.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index ca3f11f..6bcab5a 1
From: Jhih-Ming Hunag
Move else to follow close brace '}'
Signed-off-by: Jhih-Ming Hunag
---
drivers/staging/ccree/ssi_aead.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 57c7c68..c70e450 100644
From: Jhih-Ming Hunag
Remove improper space.
Signed-off-by: Jhih-Ming Hunag
---
drivers/staging/ccree/ssi_aead.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 6b9d
From: Jhih-Ming Hunag
Move * to close variable name instead of type.
Signed-off-by: Jhih-Ming Hunag
---
drivers/staging/ccree/ssi_aead.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 3d9957f..6b9de3
From: Jhih-Ming Hunag
Move '{' to next line for function.
Signed-off-by: Jhih-Ming Hunag
---
drivers/staging/ccree/ssi_aead.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 6bcab5a..3d9957f 100
From: Jhih-Ming Hunag
Add space around comma, brace, and opertor.
Signed-off-by: Jhih-Ming Hunag
---
drivers/staging/ccree/ssi_aead.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/cc
Hi Thomas,
On mar., juin 20 2017, Thomas Petazzoni
wrote:
> This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files
> to describe the ICU and GICP units, and use ICU interrupts for all
> devices in the CP110 blocks.
>
> Signed-off-by: Thomas Petazzoni
I've just tried to appl
On Mon, Jun 19, 2017 at 11:06 PM, Linus Torvalds
wrote:
> On Tue, Jun 20, 2017 at 2:42 AM, Jon Mason wrote:
>> Hello Linus,
>> Here are a few NTB bug fixes for 4.12.
>
> So I pulled this, mainly because it removed more lines than it added
> due to the revert.
>
> But generally I absolutely *hate*
On Tue, Jun 20, 2017 at 10:21:17PM +0800, Sean Wang wrote:
> Hi Herbert,
>
> thanks for effort reviewing on those patches.
>
> By the way, also loop in Torsten
>
> Could you kindly guide me how to determine appropriate
> rng->ops.quality value used by the driver?
>
> I have tested with rngtest
On Tue, 20 Jun 2017 12:57:36 +0200
Gerd Hoffmann wrote:
> On Tue, 2017-06-20 at 08:41 +, Zhang, Tina wrote:
> > Hi,
> >
> > Thanks for all the comments. Here are the summaries:
> >
> > 1. Modify the structures to make it more general.
> > struct vfio_device_gfx_plane_info {
> > __u64 st
[...]
> Am 19.06.2017 um 17:13 schrieb Markus Heiser :
>
>>> Typically I have a PY_ENV target in my projects, building a virtualenv
>>> in a folder named ./local.
[...]
>> Yeah, IMHO, it makes sense to have something like that at the main build,
>> as an optional feature,
> OK, I will prepare
On Tue, Jun 20, 2017 at 11:22:02AM +0100, Colin King wrote:
> From: Colin Ian King
>
> The pointer ilb_base_addr does not need to be in global scope, so make
> it static.
>
> Cleans up sparse warning:
> "symbol 'ilb_base_addr' was not declared. Should it be static?"
>
> Signed-off-by: Colin Ian
This allows the NAND driver to get the clock rate via clk_get_rate().
Signed-off-by: Masahiro Yamada
---
drivers/clk/uniphier/clk-uniphier-sys.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c
b/drivers/clk/uniphier/c
2017-06-20 15:48 GMT+02:00 Alexandre Belloni
:
> On 20/06/2017 at 15:44:58 +0200, Pavel Machek wrote:
>> On Tue 2017-06-20 13:37:22, Steve Twiss wrote:
>> > Hi Pavel,
>> >
>> > On 20 June 2017 14:26, Pavel Machek wrote:
>> >
>> > > Subject: Re: [PATCH 00/51] rtc: stop using rtc deprecated functions
Although header is included only once but still having an include guard
is a good practice. To avoid confusion, add SoC prefix to existing
Exynos5433 header include guard.
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. Just re-order patches in patchset and slightly adjust include
The DECON headers contain only defines for registers. There are no
other drivers using them so this should be put locally to the Exynos DRM
driver. Keeping headers local helps managing the code.
Suggested-by: Marek Szyprowski
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. Just r
On 6/19/17, 11:12 AM, "Arnaldo Carvalho de Melo" wrote:
Em Mon, Jun 19, 2017 at 09:38:25AM -0700, Mark Santaniello escreveu:
> With the new "brstackoff,dso" we get what we need: a simple offset into a
> specific dso/binary that uniquely identifies a branch/target:
You forgot
On 20.06.2017 16:44, Mark Rutland wrote:
On Fri, Jun 16, 2017 at 02:03:58AM +0300, Alexey Budankov wrote:
perf/core: use rb trees for pinned/flexible groups
By default, the userspace perf tool opens per-cpu task-bound events
when sampling, so for N logical events requested by the user, the tool
On Power systems with shared configurations of CPUs and memory, there
are some issues with association of additional CPUs and memory to nodes
when hot-adding resources. These patches address some of those problems.
powerpc/hotplug: On systems like PowerPC which allow 'hot-add' of CPU
or memory r
Currently there are a multiple files with the following code:
#define K(x) ((x) << (PAGE_SHIFT - 10))
... some code..
#undef K
This is mainly used to print out some memory-related statistics, where X is
given in pages and the macro just converts it to kilobytes. In the future
there is going to
powerpc/hotplug: On systems like PowerPC which allow 'hot-add' of CPU
or memory resources, it may occur that the new resources are to be
inserted into nodes that were not used for these resources at bootup.
In the kernel, any node that is used must be defined and initialized
at boot. In order to
powerpc/numa: Correct the currently broken capability to set the
topology for shared CPUs in LPARs. At boot time for shared CPU
lpars, the topology for each shared CPU is set to node zero, however,
this is now updated correctly using the Virtual Processor Home Node
(VPHN) capabilities information
Hi Ganapatrao,
On Tue, Jun 20, 2017 at 12:37:17PM +0530, Ganapatrao Kulkarni wrote:
> Add code to parse SRAT ITS Affinity sub table as defined in ACPI 6.2
> Later in per device probe, ITS devices are mapped to
> numa node using ITS id to proximity domain mapping.
>
> Signed-off-by: Ganapatrao Kul
Add support for the clocks provided by the CGU in the Ingenic JZ4770
SoC.
Signed-off-by: Paul Cercueil
Signed-off-by: Maarten ter Huurne
---
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/jz4770-cgu.c | 487 +
include/dt-bindings/clock/
Provide just enough bits (clocks, clocksource, uart) to allow a kernel
to boot on the JZ4770 SoC to a initramfs userspace.
Signed-off-by: Paul Cercueil
---
arch/mips/boot/dts/ingenic/jz4770.dtsi | 210 +
arch/mips/jz4740/Kconfig | 6 +
arch/mips/jz
Add a machtype ID for the JZ4780 SoC, which was missing, and one for the
newly supported JZ4770 SoC.
Signed-off-by: Paul Cercueil
---
arch/mips/include/asm/bootinfo.h | 2 ++
1 file changed, 2 insertions(+)
v2: No change
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bo
The GCW Zero (http://www.gcw-zero.com) is a retro-gaming focused
handheld game console, successfully kickstarted in ~2012, running Linux.
Signed-off-by: Paul Cercueil
---
arch/mips/boot/dts/ingenic/Makefile | 1 +
arch/mips/boot/dts/ingenic/gcw0.dts | 60 +
a
From: Paul Burton
Platforms using DT will typically call __dt_setup_arch from
plat_mem_setup. This in turn calls early_init_dt_scan. When
CONFIG_CMDLINE is set, this leads to its value being copied into
boot_command_line by early_init_dt_scan_chosen. If this happens before
the code setting up boo
Game Consoles Worldwide, mostly known under the acronym GCW, is the
creator of the GCW Zero open-source video game system.
Signed-off-by: Paul Cercueil
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
v2: It's 'Game Consoles
Previously, the clocks with a fixed divider would report their rate
as being the same as the one of their parent, independently of the
divider in use. This commit fixes this behaviour.
This went unnoticed as neither the jz4740 nor the jz4780 CGU code
have clocks with fixed dividers yet.
Signed-of
This makes sure that 'mips_machtype' will be initialized to the SoC
version used on the board.
Signed-off-by: Paul Cercueil
---
arch/mips/Kconfig | 1 +
arch/mips/jz4740/Makefile | 2 +-
arch/mips/jz4740/boards.c | 16
arch/mips/jz4740/setup.c | 34 +++
From: Maarten ter Huurne
We have seen MMC DMA transfers read corrupted data from SDRAM when
a burst interval ends at physical address 0x1000. To avoid this
problem, we remove the final page of low memory from the memory map.
Signed-off-by: Maarten ter Huurne
---
arch/mips/jz4740/setup.c |
From: Maarten ter Huurne
According to config2, the associativity would be 5-ways, but the
documentation states 4-ways, which also matches the documented
L2 cache size of 256 kB.
Signed-off-by: Maarten ter Huurne
---
arch/mips/mm/sc-mips.c | 9 +
1 file changed, 9 insertions(+)
v2: No
From: Paul Burton
jz4740_init_cmdline appends all arguments from argv (in fw_arg1) to
arcs_cmdline, up to argc (in fw_arg0). The common code in
fw_init_cmdline will do the exact same thing when run on a system where
fw_arg0 isn't a pointer to kseg0 (it'll also set _fw_envp but we don't
use it). R
In the devicetree, it is possible to specify the baudrate, parity,
bits, flow of the early console, by passing a configuration string like
this:
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:57600n8";
};
This, for instance, will configure the early console for a
On 6/19/2017 8:48 PM, AKASHI Takahiro wrote:
On Mon, Jun 19, 2017 at 05:51:08PM -0500, Li, Yi wrote:
Hi Greg,
On 6/17/2017 2:38 PM, Greg KH wrote:
On Tue, Jun 13, 2017 at 09:40:11PM +0200, Luis R. Rodriguez wrote:
On Tue, Jun 13, 2017 at 11:05:48AM +0200, Greg KH wrote:
On Mon, Jun 05, 201
The JZ4770 SoC's UART is no different from the other JZ SoCs, so this
commit simply adds the ingenic,jz4770-uart compatible string.
Signed-off-by: Paul Cercueil
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/serial/ingenic,uart.txt | 8 ++--
drivers/tty/serial/8250/8250_ingenic
The pointed string is never modified from within uart_parse_options, so
it should be marked as const in the function prototype.
Signed-off-by: Paul Cercueil
---
drivers/tty/serial/serial_core.c | 5 +++--
include/linux/serial_core.h | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
This commit permits the PLLs to be dynamically enabled and disabled when
their children clocks are enabled and disabled.
Signed-off-by: Paul Cercueil
---
drivers/clk/ingenic/cgu.c | 89 +++
1 file changed, 74 insertions(+), 15 deletions(-)
v2: No cha
The CGU common code does not modify the pointed clk_ops structure, so it
should be marked as const.
Signed-off-by: Paul Cercueil
---
drivers/clk/ingenic/cgu.h| 2 +-
drivers/clk/ingenic/jz4780-cgu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
v2: New patch in this series
The second PLL of the JZ4770 does not have a bypass bit.
This commit makes it possible to support it with the current common CGU
code.
Signed-off-by: Paul Cercueil
---
drivers/clk/ingenic/cgu.c | 3 ++-
drivers/clk/ingenic/cgu.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
v2: No ch
On 20.06.2017 16:36, Mark Rutland wrote:
On Mon, Jun 19, 2017 at 11:31:59PM +0300, Alexey Budankov wrote:
On 15.06.2017 22:56, Mark Rutland wrote:
On Thu, Jun 15, 2017 at 08:41:42PM +0300, Alexey Budankov wrote:
+static int
+perf_cpu_tree_iterate(struct rb_root *tree,
+ perf_cpu_
On Tue, Jun 20, 2017 at 05:32:16PM +0300, Leonard Crestez wrote:
> On Tue, 2017-06-20 at 06:55 +0200, Oleksij Rempel wrote:
> > On 19.06.2017 13:35, Leonard Crestez wrote:
> > > On Mon, 2017-06-19 at 07:02 +0200, Oleksij Rempel wrote:
> > > >
> > > > One of the Freescale recommended sequences for
On Tue 20-06-17 02:12:10, Tahsin Erdogan wrote:
> Ext4 ea_inode feature allows storing xattr values in external inodes to
> be able to store values that are bigger than a block in size. Ext4 also
> has deduplication support for these type of inodes. With deduplication,
> the actual storage waste is
On Tue, Jun 20, 2017 at 05:37:06PM +0300, Leonard Crestez wrote:
> On Tue, 2017-06-20 at 07:01 +0200, Oleksij Rempel wrote:
> >
> > On 19.06.2017 13:35, Leonard Crestez wrote:
> > >
> > > On Mon, 2017-06-19 at 07:02 +0200, Oleksij Rempel wrote:
> > > >
> > > > Export pm_power_off_prepare. It is
On Fri, Jun 16, 2017 at 01:52:32PM -0500, Tom Lendacky wrote:
> The boot data and command line data are present in memory in a decrypted
> state and are copied early in the boot process. The early page fault
> support will map these areas as encrypted, so before attempting to copy
> them, add decr
Hello,
On Tue, 20 Jun 2017 16:56:35 +0200, Gregory CLEMENT wrote:
> > +#include
>
> With this line you created a dependency with the patch "irqchip:
> irq-mvebu-icu: new driver for Marvell ICU". And without it the dtb is
> not buidable.
>
> So either I wait for the next kernel release to app
The expiry time of a posix cpu timer is supplied through sys_timer_set()
via a struct timespec. The timespec is validated for correctness.
In the actual set timer implementation the timespec is converted to a
scalar nanoseconds value. If the tv_sec part of the time spec is large
enough the convers
KASAN detected a multiplication overflow in the sys_setitimer() timeval
conversion. The same issue is possible the posix-cpu-timer sys_timer_set()
implementation.
In both cases the conversion of the tv_sec part overflows when multiplied
with NSEC_PER_SEC, i.e. 1e9.
This can be mitigated by using
The expiry time of a itimer is supplied through sys_setitimer() via a
struct timeval. The timeval is validated for correctness.
In the actual set timer implementation the timeval is converted to a
scalar nanoseconds value. If the tv_sec part of the time spec is large
enough the conversion to nanos
Hi Thomas,
On mar., juin 20 2017, Thomas Petazzoni
wrote:
> Hello,
>
> On Tue, 20 Jun 2017 16:56:35 +0200, Gregory CLEMENT wrote:
>
>> > +#include
>>
>> With this line you created a dependency with the patch "irqchip:
>> irq-mvebu-icu: new driver for Marvell ICU". And without it the dtb i
On Tue, Jun 20, 2017 at 03:05:39PM +0100, Will Deacon wrote:
> On Tue, Jun 20, 2017 at 02:54:15PM +0100, Marc Zyngier wrote:
> > On 20/06/17 14:30, Stefan Traby wrote:
> > > This is really trivial; there is a dup
> > > (1 << 16) in the code
> > >
> > > Signed-off-by: Stefan Traby
> > > ---
> > >
On Mon, Jun 19, 2017 at 10:22:14PM -0700, Darrick J. Wong wrote:
<>
> Fourth, the VFS entry points for things like read, write, truncate,
> utimes, fallocate, etc. all just bail out if S_IOMAP_FROZEN is set on a
> file, so that the block map cannot be modified. mmap is still allowed,
> as we've di
On 06/15/2017 03:09 PM, Stefano Stabellini wrote:
> Allocate a socket. Keep track of socket <-> ring mappings with a new data
> structure, called sock_mapping. Implement the connect command by calling
> inet_stream_connect, and mapping the new indexes page and data ring.
> Allocate a workqueue and
>> +
>> static int pvcalls_back_connect(struct xenbus_device *dev,
>> struct xen_pvcalls_request *req)
>> {
>> +struct pvcalls_fedata *fedata;
>> +int ret = -EINVAL;
>> +struct socket *sock;
>> +struct sock_mapping *map;
>> +struct xen_pvcalls_res
DMA support for half-duplex RS-485 never worked correctly on i.MX6Q/D
due to an undiscovered SMP-related bug, instead of the real data being
sent out, the rest of the transmit buffer is sent (xmit->tail jumps over
xmit->head in imx_transmit_buffer and UART_XMIT_SIZE bytes are sent out)
More details
If vfio_iommu_group_notifier() acquires a group reference and that
reference becomes the last reference to the group, then vfio_group_put
introduces a deadlock code path where we're trying to unregister from
the iommu notifier chain from within a callout of that chain. Use a
work_struct to release
At the point where the kvm-vfio pseudo device wants to release its
vfio group reference, we can't always acquire a new reference to make
that happen. The group can be in a state where we wouldn't allow a
new reference to be added. This new helper function allows a caller
to match a file to a grou
The driver core supports a BUS_NOTIFY_DRIVER_NOT_BOUND notification
sent if a driver fails to bind to a device. Extend IOMMU group
notifications to include a version of this.
Signed-off-by: Alex Williamson
Acked-by: Joerg Roedel
Reviewed-by: Eric Auger
---
drivers/iommu/iommu.c |3 +++
in
If a device is bound to a non-vfio, non-whitelisted driver while a
group is in use, then the integrity of the group is compromised and
will result in hitting a BUG_ON. This code tries to avoid this case
by mangling driver_override to force a no-match for the driver. The
driver-core will either fo
v3:
* Fix Alexey's nit in 2/, which becomes a bug in 3/. I posted the
intended correction for this, but 0-day builds broke on it and I'd
like to be sure we get all the automated testing possible, so v3.
Added Alexey's Rb.
Thanks,
Alex
v2:
* Added received acks and reviews, thanks!
On 06/15/2017 03:09 PM, Stefano Stabellini wrote:
> Just reply with success to the other end for now. Delay the allocation
> of the actual socket to bind and/or connect.
>
> Signed-off-by: Stefano Stabellini
> CC: boris.ostrov...@oracle.com
> CC: jgr...@suse.com
Reviewed-by: Boris Ostrovsky
Generally we don't know about vfio bus drivers until a device is
added to the vfio-core with vfio_add_group_dev(), this optional
registration with vfio_register_bus_driver() allows vfio-core to
track known drivers. Our current use for this information is to
know whether a driver is vfio compatible
This allows modules to match struct device.bus to amba_bustype for the
purpose of casting the device to an amba_device with to_amba_device().
Signed-off-by: Alex Williamson
Reported-by: Eric Auger
Cc: Russell King
---
drivers/amba/bus.c |1 +
1 file changed, 1 insertion(+)
diff --git a/dr
AMBA also supports driver_override, but amba_bustype was not exported
to be able to identify an amba device.
Signed-off-by: Alex Williamson
---
drivers/vfio/vfio.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/vfio/vfio.c b/drivers/vfio/vfio.c
index 20e57fecf652..36f0fcfde
Hook into vfio bus driver register/unregister support.
Signed-off-by: Alex Williamson
Reviewed-by: Eric Auger
Cc: Baptiste Reynal
Cc: Kirti Wankhede
---
drivers/vfio/mdev/vfio_mdev.c | 13 -
drivers/vfio/pci/vfio_pci.c |7 +++
drivers/vfio/platform/vfio
Unset-KVM and decrement-assignment only when we find the group in our
list. Otherwise we can get out of sync if the user triggers this for
groups that aren't currently on our list.
Signed-off-by: Alex Williamson
Reviewed-by: Alexey Kardashevskiy
Cc: Paolo Bonzini
Cc: Eric Auger
Cc: sta...@vge
On 06/15/2017 03:09 PM, Stefano Stabellini wrote:
> Call inet_listen to implement the listen command.
>
> Signed-off-by: Stefano Stabellini
> CC: boris.ostrov...@oracle.com
> CC: jgr...@suse.com
Reviewed-by: Boris Ostrovsky
> ---
> drivers/xen/pvcalls-back.c | 19 +++
> 1 file
On 06/19/2017 05:51 PM, Lee Jones wrote:
> On Fri, 16 Jun 2017, Fabrice Gasnier wrote:
>> STM32 Low Power Timer hardware block can be used for:
>> - PWM generation
>> - IIO trigger (in sync with PWM)
>> - IIO quadrature encoder counter
>> PWM and IIO timer configuration are mixed in the same regist
On 6/20/2017 2:38 AM, Borislav Petkov wrote:
On Fri, Jun 16, 2017 at 01:51:15PM -0500, Tom Lendacky wrote:
Add support to the early boot code to use Secure Memory Encryption (SME).
Since the kernel has been loaded into memory in a decrypted state, encrypt
the kernel in place and update the early
On Tue, Jun 20, 2017 at 12:52:10AM +0300, Kirill A. Shutemov wrote:
> On Mon, Jun 19, 2017 at 06:09:12PM +0100, Catalin Marinas wrote:
> > On Mon, Jun 19, 2017 at 07:00:05PM +0300, Kirill A. Shutemov wrote:
> > > On Mon, Jun 19, 2017 at 04:22:29PM +0100, Catalin Marinas wrote:
> > > > On Thu, Jun 1
From: Colin King
Date: Tue, 20 Jun 2017 11:35:50 +0100
> From: Colin Ian King
>
> The functions cvm_encrypt, cvm_decrypt, cvm_xts_setkey and
> cvm_enc_dec_init does not need to be in global scope, so make
> them static.
>
> Signed-off-by: Colin Ian King
Acked-by: David S. Miller
> static void __pvcalls_back_accept(struct work_struct *work)
> {
> + struct sockpass_mapping *mappass = container_of(
> + work, struct sockpass_mapping, register_work);
> + struct sock_mapping *map;
> + struct pvcalls_ioworker *iow;
> + struct pvcalls_fedata *fedata;
On 20/06/17 16:43, Will Deacon wrote:
> On Tue, Jun 20, 2017 at 03:05:39PM +0100, Will Deacon wrote:
>> On Tue, Jun 20, 2017 at 02:54:15PM +0100, Marc Zyngier wrote:
>>> On 20/06/17 14:30, Stefan Traby wrote:
This is really trivial; there is a dup
(1 << 16) in the code
Signed-of
On Tue, Jun 20, 2017 at 11:35 AM, Benjamin Gaignard
wrote:
> rtc_time_to_tm() and rtc_tm_to_time() are deprecated because they
> rely on 32bits variables and that will make rtc break in y2038/2016.
> Stop using those two functions to safer 64bits ones.
>
> Signed-off-by: Benjamin Gaignard
> CC:
On 06/20/2017 01:50 PM, Lee Jones wrote:
> On Fri, 16 Jun 2017, Fabrice Gasnier wrote:
>
>> Add documentation for STMicroelectronics STM32 Low Power Timer binding.
>>
>> Signed-off-by: Fabrice Gasnier
>> ---
>> .../devicetree/bindings/mfd/stm32-lptimer.txt | 51
>> ++
>>
On Tue, Jun 20, 2017 at 11:35 AM, Benjamin Gaignard
wrote:
> rtc_time_to_tm() and rtc_tm_to_time() are deprecated because they
> rely on 32bits variables and that will make rtc break in y2038/2016.
> Stop using those two functions to safer 64bits ones.
>
> Signed-off-by: Benjamin Gaignard
> CC:
On Tue, Jun 20, 2017 at 11:35 AM, Benjamin Gaignard
wrote:
> rtc_time_to_tm() and rtc_tm_to_time() are deprecated because they
> rely on 32bits variables and that will make rtc break in y2038/2016.
> Stop using those two functions to safer 64bits ones.
>
> Signed-off-by: Benjamin Gaignard
> CC:
On Tue, 2017-06-20 at 16:59 +0200, Torsten Duwe wrote:
> On Tue, Jun 20, 2017 at 10:21:17PM +0800, Sean Wang wrote:
> > Hi Herbert,
> >
> > thanks for effort reviewing on those patches.
> >
> > By the way, also loop in Torsten
> >
> > Could you kindly guide me how to determine appropriate
> > r
From: "Sergei A. Trusov"
On some x86 tablets with a Goodix touchscreen, the Windows logo on the
front is a capacitive home button. Touching this button results in a touch
with bit 4 of the first byte set, while only the lower 4 bits (0-3) are
used to indicate the number of touches.
Report a KEY_
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