From: Christian König
Most BIOS don't enable this because of compatibility reasons.
Manually enable a 64bit BAR of 64GB size so that we have
enough room for PCI devices.
v2: style cleanups, increase size, add resource name, set correct flags,
print message that windows was added
v3: add def
From: Christian König
Try to resize BAR0 to let CPU access all of VRAM.
v2: rebased, style cleanups, disable mem decode before resize,
handle gmc_v9 as well, round size up to power of two.
v3: handle gmc_v6 as well, release and reassign all BARs in the driver.
Signed-off-by: Christian König
From: Christian König
Just the defines and helper functions to read the possible sizes of a BAR and
update it's size.
See
https://pcisig.com/sites/default/files/specification_documents/ECN_Resizable-BAR_24Apr2008.pdf
and PCIe r3.1, sec 7.22.
This is useful for hardware with large local storage
On Fri, Jun 2, 2017 at 8:52 PM, Scott Branden
wrote:
> Use consistent license headers for Broadcom files by
> placing additional comments outside of standard legal header.
>
> Also, update legal header to 2017 format as "Broadcom Corporation"
> has changed to "Broadcom".
>
> Signed-off-by: Scott
From: Christian König
We use this mask multiple times in the bus setup.
v2: fix some style nit picks
Signed-off-by: Christian König
Reviewed-by: Andy Shevchenko
---
drivers/pci/pci.h | 4
drivers/pci/setup-bus.c | 12 +++-
2 files changed, 7 insertions(+), 9 deletions(-)
We are trying to get rid of DRIVER_ATTR(), and the caif driver's
attributes can be trivially changed to use DRIVER_ATTR_RO().
Cc: Dmitry Tarnyagin
Cc:
Signed-off-by: Greg Kroah-Hartman
---
drivers/net/caif/caif_spi.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
Adjust the order of rtl8153_runtime_enable() according to the
suggestion from the engineer.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index e569c48..32e83fd 10064
The MAC clock speed down could be enabled if the U1/U2 is disabled.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 34 +-
1 file changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index b8c904f..9a794
Use PLA 0xe000 bit 8 to check if disabling ALDPS is finished.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index f43b7a8..204f4b2 100644
--- a/drivers/net/usb/r81
Change from using napi_complete to napi_complete_done to allow for the
use of gro_flush_timeout in tuning network processing.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r81
Stop queuing rx packets if it is more than 1000.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index 204f4b2..fa29583 100644
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152
On Fri, Jun 2, 2017 at 5:03 PM, Richard Fitzgerald
wrote:
> These codecs have a variable number of I/O lines each of which
> is individually selectable to a wide range of possible functions.
>
> The functionality is slightly different from the traditional muxed
> GPIO since most of the functions
Move tp->rtl_ops.init() from rtl8152_resume() to rtl8152_reset_resume().
The initialization is only necessary for reset_resume().
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/n
On Freitag, 9. Juni 2017 04:52:43 CEST Andi Kleen wrote:
> On Thu, Jun 08, 2017 at 02:59:58PM +0200, Milian Wolff wrote:
> > But I notice that this functionality is missing in other places too. Most
> > notably, I would like to be able to configure `perf stat` in a similar
> > way.
> > Such that on
Hi John:
Thanks for the reviewing, I will fix it in next version.
Ding
On 2017/6/8 1:55, John Garry wrote:
> On 07/06/2017 10:16, Ding Tianhong wrote:
>
> Hi Ding,
>
> A few general style comments:
>
>> The PCIe Device Control Register use the bit 4 to indicate that
>> whether the device is
Only RTL8153 could set coalesce, so move the default setting for
rtl8152_probe() to r8153_init().
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152
Use another way to keep disabling the U2P3 for both RTL_VER_03 and
RTL_VER_04.
Move enabling U2P3 from r8153_init() to r8153_hw_phy_cfg(). The
engineer ask the setting should be done after PHY settings.
Disable U2P3 first in rtl8153_up().
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c |
Move the setting from r8153_first_init() to r8153_init(). It only needs to
be set once.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index 9a794db..e569c48 1006
On Mon, May 29, 2017 at 7:40 AM, Nikita Yushchenko
wrote:
> They originally wanted gpio-style access to use with userspace
> polling, and were not pleased with entire IIO thing.
The GPIO userspace ABI supports events with timestamps.
tools/gpio/gpio-event-mon.c
Yours,
Linus Walleij
On 2017/6/8 20:07, Will Deacon wrote:
> On Thu, Jun 08, 2017 at 12:52:07PM +0200, Vlastimil Babka wrote:
>> On 06/06/2017 07:58 PM, Will Deacon wrote:
>>> When migrating a transparent hugepage, migrate_misplaced_transhuge_page
>>> guards itself against a concurrent fastgup of the page by checking t
Enable lpm after r8153_init() and remove other enable/disable lpm.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index 9239dfb..b8c904f 100644
--- a/drivers/net/usb/r
Adjust some code to make it reasonable or satisfy the suggestion from
the engineers.
Hayes Wang (11):
r8152: add r8153_phy_status function
r8152: adjust lpm settings for RTL8153
r8152: adjust the settings about MAC clock speed down for RTL8153
r8152: move the setting of rx aggregation
r8
Use r8153_phy_status() to check phy status of RTL8153.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 37 +
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index fd31fab..9239dfb 100644
On Sat, Jun 3, 2017 at 4:44 PM, Chen-Yu Tsai wrote:
> The R_PIO on the A83T is almost the same as the one found on the A64,
> except that the CIR_RX function was moved from pin PL11 to pin PL12.
>
> Add a compatible string for it.
>
> Signed-off-by: Chen-Yu Tsai
Patch applied with Rob's ACK.
Y
On Mon, Jun 05, 2017 at 07:13:50AM +0100, Al Viro wrote:
> On Sun, Jun 04, 2017 at 12:42:52AM +0900, Greg Kroah-Hartman wrote:
> > On Sat, Jun 03, 2017 at 09:32:55AM +0200, Adam Borowski wrote:
> > > Hi!
> > > In a recent discussion, Linus and Al Viro said quite a bit of expletives
> > > about __pu
On Fri, Jun 9, 2017 at 9:30 AM, Andrew Jeffery wrote:
> Add the clock-names property in init_timer() to work-around Aspeed
> devicetrees from times prior to merging the Moxart/Aspeed and Faraday
> drivers.
>
> Signed-off-by: Andrew Jeffery
> ---
> Well, here's an implementation I knocked up. It's
On Mon, 2017-06-05 at 18:54 +0300, Kalle Valo wrote:
> > BTW, since you're taking an interest in this code now, can I
> > trouble you with a question? Looking at mwifiex_uninit_sw() (after
> > this patchset), you can see a loop like this:
> >
> > /* Stop data */
> > for (i = 0; i
On Wed, Jun 7, 2017 at 12:26 PM, Mateusz Jurczyk wrote:
> Add initialization of the flock flag in the fuse_file structure after it
> is allocated.
>
> Before the patch, the flock flag could remain uninitialized for the
> lifespan of the fuse_file allocation: it was not pre-set by kmalloc() or
> la
On Sat, Jun 3, 2017 at 4:44 PM, Chen-Yu Tsai wrote:
> The R_PIO on the A83T is almost the same as the one found on the A64,
> except that the CIR_RX function was moved from pin PL11 to pin PL12.
>
> Add a driver for it.
>
> Signed-off-by: Chen-Yu Tsai
Patch applied.
Yours,
Linus Walleij
On Sat, Jun 3, 2017 at 4:44 PM, Chen-Yu Tsai wrote:
> The A83T has 1 pingroup with 13 pins belonging to the R_PIO
> or special pin controller.
>
> Signed-off-by: Chen-Yu Tsai
Acked-by: Linus Walleij
Pls funnel this through the ARM SoC tree.
Yours,
Linus Walleij
The bridge_node is unnecessary between FIMD and DSIM. If don't remove
error handling, it will not work between FIMD and DSIM. So remove
error handling.
Signed-off-by: Hoegeun Kwon
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/exy
Since we've vastly expanded the atomic_t interface in recent years the
existing documentation is woefully out of date and people seem to get
confused a bit.
Start a new document to hopefully better explain the current state of
affairs.
The old atomic_ops.txt also covers bitmaps and a few more de
Greg Kroah-Hartman writes:
> We are trying to get rid of DRIVER_ATTR(), and the ipw2x00 driver's
> attributes can be trivially changed to use DRIVER_ATTR_RW().
>
> Cc: Stanislav Yakovlev
> Cc: Kalle Valo
> Cc:
> Cc:
> Signed-off-by: Greg Kroah-Hartman
Looks good to me. I assume that I shoul
On Fri, Jun 9, 2017 at 11:01 AM, A.S. Dong wrote:
>> >> > + u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
>> >> > + u32 clk = sport->port.uartclk;
>> >> > +
>> >> > + /*
>> >> > +* The idea is to use the best OSR (over-sampling rate)
>> possible.
>> >> > +
On Sun, Jun 04, 2017 at 12:15:15AM +1000, Aleksa Sarai wrote:
> When opening the slave end of a PTY, it is not possible for userspace to
> safely ensure that /dev/pts/$num is actually a slave (in cases where the
> mount namespace in which devpts was mounted is controlled by an
> untrusted process).
On Fri, Jun 9, 2017 at 11:29 AM, Pali Rohár wrote:
> On Thursday 08 June 2017 08:16:18 Darren Hart wrote:
>> On Sat, May 27, 2017 at 11:49:22PM +0300, Andy Shevchenko wrote:
>> > On Sat, May 27, 2017 at 11:48 PM, Pali Rohár wrote:
>> > > On Saturday 27 May 2017 15:33:14 Andy Shevchenko wrote:
>>
v5:
* Removed the 'NA' binding from documentation
v4:
* Split the clock patch and addressed a minor comment
in the clock driver as per stephen's feedback.
v3:
* Addressed review feedback from Bjorn for pinctrl
- Unified the names for qpic pads.
- Corrected the names for pwm p
On Mon, Jun 05, 2017 at 07:02:54PM +0200, Andreas Noever wrote:
> On Thu, May 18, 2017 at 9:42 AM, Colin King wrote:
> > From: Colin Ian King
> >
> > Trivial fix to spelling mistake in tb_sw_warn warning message
> >
> > Signed-off-by: Colin Ian King
> > ---
> > drivers/thunderbolt/eeprom.c | 2
This adds the necessary data for handling io voltage domains on the rk3228.
Signed-off-by: David Wu
---
.../devicetree/bindings/power/rockchip-io-domain.txt | 7 +++
drivers/power/avs/rockchip-io-domain.c | 14 ++
2 files changed, 21 insertions(+)
diff
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt
b/Documentation/devicetree/bindings/arm/qcom.txt
index 028d16e..0ed4d39 100644
--- a
From: Abhishek Sahu
This patch adds support for the global clock controller found on
the ipq8074 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |
From: Abhishek Sahu
These configs are required for booting kernel in qcom
ipq8074 boards.
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/
On Fri, Jun 09, 2017 at 12:25:44PM +0300, Kalle Valo wrote:
> Greg Kroah-Hartman writes:
>
> > We are trying to get rid of DRIVER_ATTR(), and the ipw2x00 driver's
> > attributes can be trivially changed to use DRIVER_ATTR_RW().
> >
> > Cc: Stanislav Yakovlev
> > Cc: Kalle Valo
> > Cc:
> > Cc:
From: Abhishek Sahu
Add the compatible strings and the include file for ipq8074 gcc
clock controller.
Acked-by: Rob Herring (bindings)
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Abhishek Sahu
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
include/dt-bindings/clock/q
Add initial device tree support for the Qualcomm IPQ8074 SoC and
HK01 evaluation board.
Signed-off-by: Manoharan Vijaya Raghavan
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts |
On Fri, Jun 9, 2017 at 12:03 PM, Greg Kroah-Hartman
wrote:
> We are trying to get rid of DRIVER_ATTR(), and the thinkpad_acpi
> driver's attributes can be trivially changed to use DRIVER_ATTR_RO() and
> DRIVER_ATTR_RW().
Which tree is it supposed to go through?
We might need an immutable tag / br
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.
Signed-off-by: Manoharan Vijaya Raghavan
Signed-off-by: Varadarajan Narayanan
---
.../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 172
drivers/pinctrl/qcom/Kconfig | 10
Few more nit picks!!
On 08/06/17 17:51, Oleksij Rempel wrote:
This is a driver for Low Power General Purpose Register (LPGPR)
available on i.MX6 SoCs in Secure Non-Volatile Storage (SNVS)
of this chip.
It is a 32-bit read/write register located in the low power domain.
Since LPGPR is located i
On 08/06/17 17:51, Oleksij Rempel wrote:
Documentation bindings for the Low Power General Purpose Register
available on i.MX6 SoCs in the Secure Non-Volatile Storage.
Signed-off-by: Oleksij Rempel
---
.../devicetree/bindings/nvmem/snvs-lpgpr.txt | 19 +++
1 file ch
On Fri, Jun 09, 2017 at 02:28:30AM +, Zhuo, Qiuxu wrote:
> Hi Xiaolong,
>
> Fixed this issue by 'EDAC, sb_edac: Avoid creating 'SOCK' EDAC memory
> controller' (you were also CCed by 'Reported-by').
> Thanks for this test case :-)
Xiaolong,
can you please run Qiuxu's patch to verify
On Fri, Jun 9, 2017 at 7:33 AM, Lee, Chun-Yi wrote:
> Kernel should decrements the reference count of acpi device
> when the scheduling of acpi hotplug work is failed, and
> evaluates _OST to notify BIOS the failure.
>
> v2:
> To simplify the code. (Andy Shevchenko)
>
> Cc: "Rafael J. Wysocki"
>
From: Abhishek Sahu
Add the compatible strings and the include file for ipq8074 gcc
clock controller.
Acked-by: Rob Herring (bindings)
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Abhishek Sahu
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
include/dt-bindings/clock/q
v6:
* Include Rob's Ack to the first patch.
v5:
* Removed the 'NA' binding from documentation
v4:
* Split the clock patch and addressed a minor comment
in the clock driver as per stephen's feedback.
v3:
* Addressed review feedback from Bjorn for pinctrl
- Unified the names for q
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.
Acked-by: Rob Herring (bindings)
Signed-off-by: Manoharan Vijaya Raghavan
Signed-off-by: Varadarajan Narayanan
---
.../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 172
drivers/pinctrl/qcom/Kc
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt
b/Documentation/devicetree/bindings/arm/qcom.txt
index 028d16e..0ed4d39 100644
--- a
From: Abhishek Sahu
These configs are required for booting kernel in qcom
ipq8074 boards.
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/
From: Abhishek Sahu
This patch adds support for the global clock controller found on
the ipq8074 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |
Add initial device tree support for the Qualcomm IPQ8074 SoC and
HK01 evaluation board.
Signed-off-by: Manoharan Vijaya Raghavan
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts |
On Tue, Jun 06, 2017 at 03:24:52PM +0300, Mika Westerberg wrote:
> Hi,
>
> This is fourth version of the patch series adding support for Thunderbolt
> security levels and NVM firmware upgrade. PCs running Intel Falcon Ridge or
> newer need these in order to connect devices if the security level is
On Thu, Jun 08, 2017 at 06:09:08PM +0530, Amit Pundir wrote:
> Hi,
>
> Following are the Android config fragment changes cherry-picked from
> Android common kernel for your consideration. Config fragments are
> folded or re-placed in sorted order wherever required.
I'll be glad to take these in m
Linus,
On 6/9/2017 2:26 PM, Linus Walleij wrote:
On Thu, Jun 1, 2017 at 1:27 PM, Varadarajan Narayanan
wrote:
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.
Signed-off-by: Manoharan Vijaya Raghavan
Signed-off-by: Varadarajan Narayanan
It's a g
On Mon, Jun 05, 2017 at 02:07:34PM -0500, Alan Tull wrote:
> From: Tobias Klauser
>
> Add COMPILE_TEST to the Kconfig entry for the Altera SoCFPGA FPGA
> Bridge. The Altera FPGA Freeze Bridge can also be used on Altera PEIe
> FPGAs, so the driver shouldn't depend on ARCH_SOCFPGA in the first plac
During implementation aio support for Checkpoint-Restore
in Userspace project (CRIU), we found, that current
kernel functionality does not allow to wait for
completion of all submitted requests. Checkpoint software
can't determine if there is no in-flight requests, i.e.
the process aio rings memory
From: Helmut Klein
This patch switches to the stable UART bindings but also add the correct
gate clock to the non-AO UART nodes for GXBB and GXL SoCs.
Signed-off-by: Helmut Klein
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 12 +---
arch/arm64/boot/d
The UART bindings needs specifying a SoC family, use the meson6 family
for the UART nodes like the other nodes.
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/meson.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/
Switch to the stable UART bindings by adding a XTAL node and using the
proper compatible strings.
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/meson8.dtsi | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/
Switch to the stable UART bindings by adding a XTAL node and using the
proper compatible strings.
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/meson8b.dtsi | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/ar
When opening the slave end of a PTY, it is not possible for userspace to
safely ensure that /dev/pts/$num is actually a slave (in cases where the
mount namespace in which devpts was mounted is controlled by an
untrusted process). In addition, there are several unresolvable
race conditions if users
From: Helmut Klein
This patch handle the stable UART bindings but also keeps compatibility
with the legacy non-stable bindings until all boards uses them.
Signed-off-by: Helmut Klein
Signed-off-by: Neil Armstrong
---
drivers/tty/serial/meson_uart.c | 109 +-
This patchset is a re-spin of Helmut Klein's v3 patchset at [0].
Initially, the original patchset was made to enable usage on the non-AO UARTS
not enabled by the Bootloader (uart_B and uart_C), but the patchset needed
an overall change to have clean and stable DT bindings.
The Amlogic Meson UART
On Mon, Jun 05, 2017 at 02:07:37PM -0500, Alan Tull wrote:
> From: Joshua Clayton
>
> altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
> interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.
>
> This is one of the simpler ways to set up an FPGA at runtime.
> The signa
Switch to the stable UART bindings by adding a XTAL node and using the
proper compatible strings.
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/meson6.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/me
Hi, Michal
I am not that familiar with hotplug and trying to catch up the issue
and your solution.
One potential issue I found is we don't check the physical boundary
when add_memory_resource().
For example, on x86-64, only 64T physical memory is supported currently.
Looks it is expanded after
From: Helmut Klein
Add the documentation for the device tree binding of Amlogic Meson Serial UART.
Signed-off-by: Helmut Klein
Signed-off-by: Neil Armstrong
---
.../bindings/serial/amlogic,meson-uart.txt | 38 ++
1 file changed, 38 insertions(+)
create mode 100644
On 06/08/2017 03:09 PM, Jerome Brunet wrote:
> Add Tsin A pins to bank DV and X.
> We don't have a driver for the tsin yet but since the tsin A pinmux is
> enabled by default at boot time, declaring this pinmux is required to
> properly operate on GPIOX.
>
> Without this change, GPIOX 8, 9, 10 and
On Thu, Jun 08, 2017 at 02:19:40PM +0200, Sebastian Reichel wrote:
> Hi,
>
> On Mon, Jun 05, 2017 at 08:04:45PM +0300, Evgeniy Polyakov wrote:
> > 05.06.2017, 16:52, "Andrew F. Davis" :
> > > Like other subsystems we should be able to define slave devices outside
> > > of the w1 directory. To do t
On 06/08/2017 03:55 PM, Jerome Brunet wrote:
> Remove the FIXME on clk81 mux and add all the documented parents
>
> Signed-off-by: Jerome Brunet
> ---
> drivers/clk/meson/gxbb.c | 13 -
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/meson/gxbb.c b/dri
Linus,
please pull sound fixes for v4.12-rc5 from:
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git
tags/sound-4.12-rc5
The topmost commit is ba3021b2c79b2fa9114f92790a99deb27a65b728
sound fixes for 4.12-rc5
This
Hello Grygorii, Javier,
2017-06-09 2:00 GMT+02:00 Javier Martinez Canillas :
> Hello Grygorii,
>
> [snip]
>
>>>
>>> For tps65218 couldn't instead of using mfd_add_devices() for all the
>>> sub-devs, had used of_platform_populate() for the ones that have
>>> device nodes and mfd_add_devices() only
On Fri, 09 Jun 2017, Greg Kroah-Hartman wrote:
> We are trying to get rid of DRIVER_ATTR(), and the thinkpad_acpi
> driver's attributes can be trivially changed to use DRIVER_ATTR_RO() and
> DRIVER_ATTR_RW().
>
> Cc: Henrique de Moraes Holschuh
> Cc: Darren Hart
> Cc: Andy Shevchenko
> Cc:
> C
Hi Greg,
This patchset contains few fixes to core, Broadcom OTP driver and a patch
for new compatible to support rockchip rk322x-efuse.
Can you please queue these for v4.13.
Thanks,
srini
Andrey Smirnov (1):
nvmem: core: Call put_device() in nvmem_unregister()
Finley Xiao (1):
nvmem: roc
From: Oza Pawandeep
- use data write offset to write otp data instead of read offset
- use OTP program command 0x8 to write otp with ECC rather than just
command 0xA without ECC
Fixes: 9d59c6e8ae27 ("nvmem: Add the Broadcom OTP controller driver")
Signed-off-by: Oza Pawandeep
Signed-off-by: Sco
From: Andrey Smirnov
Call put_device() in nvmem_unregister() to make sure nvmem_release
gets called freeing up allocated resources.
Cc: cphe...@gmail.com
Cc: Srinivas Kandagatla
Cc: Maxime Ripard
Signed-off-by: Andrey Smirnov
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/core.c | 1 +
Hi Geetha,
On Tue, May 30, 2017 at 05:33:41PM +0530, Geetha sowjanya wrote:
> From: Geetha Sowjanya
>
> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
> lines for gerror, eventq and cmdq-sync.
>
> This patch addresses the issue by checking if any interrupt sources ar
From: Finley Xiao
This adds the necessary data for handling eFuse on the rk322x.
Signed-off-by: Finley Xiao
Acked-by: Rob Herring
Signed-off-by: Srinivas Kandagatla
---
Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt | 1 +
drivers/nvmem/rockchip-efuse.c
From: Johan Hovold
Make sure to deregister and release the nvmem device and underlying
memory on registration errors.
Note that the private data must be freed using put_device() once the
struct device has been initialised.
Also note that there's a related reference leak in the deregistration
fu
From: Heiner Kallweit
Adding entries to nvmem_cells and deleting entries from it is
protected by nvmem_cells_mutex. Therefore this mutex should
also protect iterating over the list.
Signed-off-by: Heiner Kallweit
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/core.c | 8 +++-
1 file
On Thu, Jun 08, 2017 at 07:41:37PM +, Ard Biesheuvel wrote:
> This is a follow-up to patches from zhonjiang [0] and myself [1] that aim
> to solve a problem in the kcore code, which gets confused by the presence
> of block mappings in the vmalloc region.
>
> While fixing the crash is quite str
On Thu, Jun 08, 2017 at 09:55:30AM +1200, Chris Packham wrote:
> edac_op_state is a module parameter which affects the behaviour of the
> driver probe which can potentially be invoked as soon as the platform
> driver registration happens. Because of this we need to ensure that we
> sanity check the
On Fri, Jun 09, 2017 at 12:35:35PM +0300, Andy Shevchenko wrote:
> On Fri, Jun 9, 2017 at 12:03 PM, Greg Kroah-Hartman
> wrote:
> > We are trying to get rid of DRIVER_ATTR(), and the thinkpad_acpi
> > driver's attributes can be trivially changed to use DRIVER_ATTR_RO() and
> > DRIVER_ATTR_RW().
>
In some place in the driver regmap_update_bits was misused. Indeed the
last argument is not the value of the bit (or group of bits) itself but
the mask value inside the register.
So when setting the bit N, then the value must be BIT(N) and not 1.
CC: Chris Packham
CC: Ralph Sennhauser
Signed-of
Hello,
On Fri, 9 Jun 2017 12:03:18 +0200, Gregory CLEMENT wrote:
> regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
> -BIT(pin), 1);
> +BIT(pin), BIT(pin));
>
> return 0;
> }
> @@ -364,7 +364,7 @@ static int mvebu_gpio_direction_ou
On Fri, Jun 09, 2017 at 07:50:43PM +1000, Aleksa Sarai wrote:
> > > When opening the slave end of a PTY, it is not possible for userspace to
> > > safely ensure that /dev/pts/$num is actually a slave (in cases where the
> > > mount namespace in which devpts was mounted is controlled by an
> > > unt
On Thu, Jun 08, 2017 at 02:50:59PM +0200, Peter Zijlstra wrote:
> On Thu, Jun 08, 2017 at 12:24:33PM +0100, Will Deacon wrote:
> > [+ PeterZ]
> >
> > On Thu, Jun 08, 2017 at 01:07:02PM +0200, Vlastimil Babka wrote:
> > > On 06/08/2017 12:40 PM, Kirill A. Shutemov wrote:
> > > > On Thu, Jun 08, 201
Hi Thomas,
On ven., juin 09 2017, Thomas Petazzoni
wrote:
> Hello,
>
> On Fri, 9 Jun 2017 12:03:18 +0200, Gregory CLEMENT wrote:
>
>> regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
>> - BIT(pin), 1);
>> + BIT(pin), BIT(pin));
>>
>>
In some place in the driver regmap_update_bits was misused. Indeed the
last argument is not the value of the bit (or group of bits) itself but
the mask value inside the register.
So when setting the bit N, then the value must be BIT(N) and not 1.
CC: Chris Packham
CC: Ralph Sennhauser
Signed-of
On Fri, Jun 09, 2017 at 10:35:15AM +0100, Srinivas Kandagatla wrote:
>
> Few more nit picks!!
>
> On 08/06/17 17:51, Oleksij Rempel wrote:
> > This is a driver for Low Power General Purpose Register (LPGPR)
> > available on i.MX6 SoCs in Secure Non-Volatile Storage (SNVS)
> > of this chip.
> >
>
On Fri, Jun 09, 2017 at 11:03:13AM +0200, Greg Kroah-Hartman wrote:
> We are trying to get rid of DRIVER_ATTR(), and the s390 drivers'
> attributes can be trivially changed to use DRIVER_ATTR_RO() and
> DRIVER_ATTR_WO().
>
> Cc: Martin Schwidefsky
> Cc: Heiko Carstens
> Cc: Julian Wiedmann
> Cc
Hi Ralph,
On ven., juin 09 2017, Ralph Sennhauser wrote:
> Hi Thomas,
>
> Commit 2233bf7a92e7 ("gpio: mvebu: switch to regmap for register
> access") in next-20170607 breaks gpio-keys on an armada-385 (Linksys
> WRT3200ACM), noticed due to missing /dev/input/event0 and the below
> dmesg output
On Fri, Jun 9, 2017 at 11:59 AM, Christian König
wrote:
> From: Christian König
>
> This way we can savely call it on SI as well.
s/savely/safely
FWIW,
Reviewed-by: Andy Shevchenko
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 -
>
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