From: Borislav Petkov
Move the AMD pieces from the generic Makefile so that
$ make arch/x86/events/amd/.s
can work too. Otherwise you get
$ make arch/x86/events/amd/ibs.s
scripts/Makefile.build:44: arch/x86/events/amd/Makefile: No such file or
directory
make[1]: *** No rule to make ta
On Wed, Jan 25, 2017 at 10:13:32AM -0800, Alexander Duyck wrote:
> On Tue, Jan 24, 2017 at 8:35 PM, Mark Zhang wrote:
> > If the input parameters as saddr = 0xc0a8fd60,daddr = 0xc0a8fda1,len =
> > 80, proto = 17, sum =0x7eae049d.
> > The correct result should be 1, but original function return 0.
* r...@redhat.com wrote:
> From: Rik van Riel
>
> On Skylake CPUs I noticed that XRSTOR is unable to deal with states
> created by copyout_from_xsaves if the xstate has only SSE/YMM state, and
> no FP state. That is, xfeatures had XFEATURE_MASK_SSE set, but not
> XFEATURE_MASK_FP.
>
> The rea
* Lu Baolu wrote:
> Hi Ingo,
>
> On 01/26/2017 03:19 PM, Ingo Molnar wrote:
> > * Lu Baolu wrote:
> >
> >> Fair enough.
> >>
> >> USB connection is stable enough, unless the user unplugs the
> >> USB cable during debugging.
> > What does the hardware do in this case? The XHCI registers are in
* Ingo Molnar wrote:
> 1)
>
> the 'copyin/copyout' nomenclature needlessly departs from what the modern FPU
> code
> uses, which is:
The patch below implements this first step. Untested.
Thanks,
Ingo
>
>From c9459f7130a33c9d0108ca1f93306fb71772038f Mon Sep 17 00:00:00 2001
Fro
On 25.01.2017 15:06, Ville Syrjälä wrote:
> On Mon, Jan 23, 2017 at 10:15:16AM +0100, Andrzej Hajda wrote:
>> On 20.01.2017 14:55, Ville Syrjälä wrote:
>>> On Fri, Jan 20, 2017 at 07:52:24AM +0100, Andrzej Hajda wrote:
In case of interlace mode irq is generated for odd and even fields, but
>>>
On Mon, Jan 23, 2017 at 03:26:08PM +0530, Chaitra P B wrote:
> Small glitch/degraded performance in Crusader is improved with SAS
> drives by removing unnecessary spinlocks while clearing scsi command
> in drivers internal lookup table.
>
> Signed-off-by: Chaitra P B
> Signed-off-by: Suganath Pra
On Mon, Jan 23, 2017 at 03:26:07PM +0530, Chaitra P B wrote:
> Driver processes the event MPI26_EVENT_ACTIVE_CABLE_DEGRADED
> when a cable is present and is running at a degraded speed
> (below the SAS3 12 Gb/s rate). Prints added
> to inform the user that the cable is not running at
> optimal spee
> From: gre...@linuxfoundation.org [mailto:gre...@linuxfoundation.org]
> > > > It's interesting v4.4.44 is not impacted, but actually it needs both
> > > > the 2
> patches:
> > > > i.e. this patch, and the previous one:
> > > > Commit a389fcfd2cb5 ("Drivers: hv: vmbus: Fix signaling logic in
> > >
Exynos LPASS requires some clocks to be enabled to make any access to its
registers. This patch adds code for handling such clocks. For current set
of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
worked only because those clocks were enabled by bootloader and driver
probe() h
Add compatible for Exynos5433 SoC, so the driver will bind and let other
drivers to use PMU regmap.
Signed-off-by: Marek Szyprowski
---
drivers/soc/samsung/exynos-pmu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsun
When pin controller device is a part of power domain, there is no guarantee
that the power domain was not turned off and then on during boot process
before probing of the pin control driver. If it happened, then pin control
driver should ensure that pad retention is turned off during its probe call
On Thu, Jan 26, 2017 at 11:41:09AM +0800, Fam Zheng wrote:
> This implements the VIRTIO_SCSI_F_FC_HOST feature by reading the config
> fields and presenting them as sysfs fc_host attributes. The config
> change handler is added here because primary_active will toggle during
> migration.
This needs
Convert exisitng lpass-suspend/resume callbacks into runtime PM callbacks.
This way Exynos LPASS driver will be ready for use with power domains
enabled. LPASS will be runtime resumed/suspended as a result of its child
devices runtime PM transitions.
Signed-off-by: Marek Szyprowski
Acked-by: Krzy
Hello,
This patchset is a first step to add support for all power domains on
Exynos5433 SoCs. This patchset contains patches for Exynos pin control
driver and Exynos LPASS MFD driver, which are needed to make the
platform ready for adding power domains support.
Patches in this patchset depends on
Disable device on driver remove and release allocated regmap.
Signed-off-by: Marek Szyprowski
---
drivers/mfd/exynos-lpass.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index be264988bdc9..9dbbedad916f 100644
--- a/driv
Pad retention should be controlled from pin control driver, so remove it
from Exynos LPASS driver. After this change, no more access to PMU regmap
is needed, so remove also the code for handling PMU regmap.
Signed-off-by: Marek Szyprowski
Acked-by: Krzysztof Kozlowski
---
.../bindings/mfd/samsu
On Wed, Jan 25, 2017 at 04:26:08PM +0100, Jean Delvare wrote:
> The pinctrl-baytrail driver builds just fine as a module so give
> users this option.
>
> Signed-off-by: Jean Delvare
> Cc: Mika Westerberg
> Cc: Heikki Krogerus
OK by me. FWIW.
Reviewed-by: Heikki Krogerus
Thanks,
--
heikki
Hi Jassi,
On Thu, 2017-01-26 at 10:08 +0530, Jassi Brar wrote:
> On Wed, Jan 4, 2017 at 8:36 AM, HS Liao wrote:
>
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > new file mode 100644
> > index 000..747bcd3
> > --- /dev/null
> > +++ b/drivers/
This patch adds support for retention control for Exynos5433 SoCs. Three
groups of pins has been defined for retention control: common shared group
for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
separate control for FSYS and AUD pin banks, for which PMU retention
registers matc
Exynos5433 LPASS module requires some clocks for proper operation with
power domain.
Signed-off-by: Marek Szyprowski
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exyno
On Thu, Jan 26, 2017 at 9:18 AM, Marek Szyprowski
wrote:
> Hi Krzysztof,
>
>
> On 2017-01-25 20:50, Krzysztof Kozlowski wrote:
>>
>> On Wed, Jan 25, 2017 at 12:50:28PM +0100, Marek Szyprowski wrote:
>>>
>>> Exynos5433 LPASS module requires some clocks for proper operation with
>>> power domain.
>>
Hi Krzysztof,
On 2017-01-26 09:40, Krzysztof Kozlowski wrote:
On Thu, Jan 26, 2017 at 9:18 AM, Marek Szyprowski
wrote:
On 2017-01-25 20:50, Krzysztof Kozlowski wrote:
On Wed, Jan 25, 2017 at 12:50:28PM +0100, Marek Szyprowski wrote:
Exynos5433 LPASS module requires some clocks for proper ope
On Mon, 23 Jan 2017, Michael Schmitz wrote:
>
> Am 21.01.2017 um 20:37 schrieb Finn Thain:
>
> >
> > Actually, the fundamental problem you are describing is partly solved.
> > By polling for DMA completion with local irqs disabled, we mostly
> > avoid the need for the stdma.c "lock" because
On Tue, 2017-01-24 at 16:42 +0100, Amadeusz Sławiński wrote:
> cleanup patch to make use of ieee80211_ac_from_tid() to retrieve ac
> from
> ieee802_1d_to_ac[]
Applied.
johannes
On Wed, Jan 25, 2017 at 4:26 PM, Jean Delvare wrote:
> The pinctrl-baytrail driver builds just fine as a module so give
> users this option.
>
> Signed-off-by: Jean Delvare
> Cc: Mika Westerberg
> Cc: Heikki Krogerus
> Cc: Linus Walleij
> ---
> This was discussed almost one year ago, with no
/20170126-114655
config: i386-randconfig-h0-01261251 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
>> ERROR: "fc_release_transpo
Em Wed, 25 Jan 2017 16:37:28 +0100
Borislav Petkov escreveu:
> On Wed, Jan 25, 2017 at 12:04:04PM +, David Binderman wrote:
> > You'll have a very long wait to get a linux patch from me.
> >
> > I am happy for someone else to invent a patch.
>
> Ah ok, I thought you wanted to give it a tr
"pdev->ee_file" was allocated with devm_kmalloc() so freeing it with
kfree() is a double free. In fact, we don't need to free it at all.
Fixes: cfad6425382e ("eeprom: Add IDT 89HPESx EEPROM/CSR driver")
Signed-off-by: Dan Carpenter
diff --git a/drivers/misc/eeprom/idt_89hpesx.c
b/drivers/misc/
Hi Finn,
On Thu, Jan 26, 2017 at 9:47 AM, Finn Thain wrote:
> The difficulty will be arranging for disabled FDC & IDE interrupt sources
> during SCSI DMA, and disabled SCSI & IDE interrupt sources during FDC DMA.
> (Not all 5380 interrupts can be disabled; no idea about the IDE device or
> WD1772
Hi Mika and all,
On Wed, 25 Jan 2017 18:16:51 +0200, Mika Westerberg wrote:
> On Wed, Jan 25, 2017 at 04:26:08PM +0100, Jean Delvare wrote:
> > The pinctrl-baytrail driver builds just fine as a module so give
> > users this option.
> >
> > Signed-off-by: Jean Delvare
> > Cc: Mika Westerberg
>
Hi,
Here is a new attempt at getting the MMC controllers running, following the
work done by Andre.
This has been tested on a board with one SDIO device (a Marvell WiFi chip)
and a Kingston eMMC with 1.8V IOs.
For SDIO, the HS DDR mode works just fine. That serie also enables the
SDR104 mode to
The A64 MMC controllers need DATA0 to be masked while updating the clock,
otherwise any subsequent command will result in a timeout.
It's not really clear at this point what DATA0 is exactly, but this
behaviour is present in Allwinner's tree, and has been suggested by
Allwinner engineers as fixes
The A64 MMC controllers need to set a "new timings" bit when a new rate is
set.
The actual meaning of that bit is not clear yet, but not setting it leads
to some corner-case issues, like the CMD53 failing, which is used to
implement SDIO packet aggregation.
Signed-off-by: Maxime Ripard
---
driv
The MMC2 controller on the A64 is kind of a special beast.
While the general controller design is the same than the other MMC
controllers in the SoC, it also has a bunch of features and changes that
prevent it to be driven in the same way.
It has for example a different bus width limit, a differe
Add a bit more debug messages that can be helpful when debugging the clock
setup.
Also fill the actual_clock field in struct mmc_host to report properly the
current frequency in debugfs.
Signed-off-by: Maxime Ripard
---
drivers/mmc/host/sunxi-mmc.c | 23 +++
1 file changed,
From: Andre Przywara
The A64 has 3 MMC controllers, one of them being especially targeted to
eMMC. Among other things, it has a data strobe signal and a 8 bits data
width.
The two other are more usual controllers that will have a 4 bits width at
most and no data strobe signal, which limits it to
From: Andre Przywara
The Banana Pi M64 board is a typical single board computer based on the
Allwinner A64 SoC. Aside from the usual peripherals it features eMMC
storage, which is connected to the 8-bit capable SDHC2 controller.
Also it has a soldered WiFi/Bluetooth chip, so we enable UART1 and S
The MMC core assumes that the code will gate the clock when the bus
frequency is set to 0, which we've been ignoring so far.
Handle that.
Signed-off-by: Maxime Ripard
---
drivers/mmc/host/sunxi-mmc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sunxi-
Experience have shown that the using the autocalibration could severely
degrade the performances of the MMC bus.
Allwinner is using in its BSP a delay set to 0 for all the modes but HS400.
Remove the calibration code for now, and add comments to document our
findings.
Reviewed-by: Andre Przywara
The A64 only has a single set of pins for each MMC controller. Since we
already have boards that require all of them, let's add them to the DTSI.
Reviewed-by: Andre Przywara
Signed-off-by: Maxime Ripard
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 -
1 file changed
From: Andre Przywara
All Pine64 boards connect an micro-SD card slot to the first MMC
controller.
Enable the respective DT node and specify the (always-on) regulator
and card-detect pin.
As a micro-SD slot does not feature a write-protect switch, we disable
this feature.
Signed-off-by: Andre Prz
From: Andre Przywara
On many boards UART1 connects to a Bluetooth chip, so add the pinctrl
nodes for the only pins providing access to that UART. That includes
those pins for hardware flow control (RTS/CTS).
Signed-off-by: Andre Przywara
Signed-off-by: Maxime Ripard
---
arch/arm64/boot/dts/al
The SD specification documents that the clock frequency should only be
changed once gated (Section 3.2.3 - SD Clock Frequency Change Sequence).
The current code first modifies the parent clock, gates it and then
modifies the internal divider. This means that since the parent clock rate
might be ch
The eMMC controller seem to have a maximum frequency of 200MHz, while the
regular MMC controllers are capped at 150MHz.
Since older SoCs cannot go that high, we cannot change the default maximum
frequency, but fortunately for us we have a property for that in the DT.
This also has the side effect
On Wed 25-01-17 12:27:06, Ye Xiaolong wrote:
> On 01/24, Michal Hocko wrote:
> >On Mon 23-01-17 09:26:44, kernel test robot wrote:
> >>
> >> Greeting,
> >>
> >> FYI, we noticed a -11.1% regression of fsmark.files_per_sec due to commit:
> >>
> >>
> >> commit: 5e56dfbd837421b7fa3c6c06018c6701e270
On Fri, Jan 20, 2017 at 7:13 PM, Krzysztof Kozlowski wrote:
> Few changes in Exynos PMU driver including one that is needed by pinctrl
> driver for runtime PM. We want to move forward with the RPM for our drivers
> while keeping still DT ABI.
>
> This tag is also for Linus Walleij to pull - base
Bhumika Goyal writes:
> Declare usb_ep_ops structures as const as they are only stored in the
> ops field of an usb_ep structure. This field is of type const, so
> usb_ep_ops structures having this property can be made const too.
> Done using Coccinelle( A smaller version of the script)
For pxa2
On Thu, Jan 26, 2017 at 08:27:26AM +, Dexuan Cui wrote:
> > From: gre...@linuxfoundation.org [mailto:gre...@linuxfoundation.org]
> > > > > It's interesting v4.4.44 is not impacted, but actually it needs both
> > > > > the 2
> > patches:
> > > > > i.e. this patch, and the previous one:
> > > >
On Wed 25-01-17 23:05:37, ys...@foxmail.com wrote:
> From: Yisheng Xie
>
> Define isolate_movable_page as a static inline function when
> CONFIG_MIGRATION is not enable. It should return false
> here which means failed to isolate movable pages.
>
> This patch do not have any functional change bu
On Thu, Jan 26, 2017 at 09:55:36AM +0100, Linus Walleij wrote:
> On Wed, Jan 25, 2017 at 4:26 PM, Jean Delvare wrote:
>
> > The pinctrl-baytrail driver builds just fine as a module so give
> > users this option.
> >
> > Signed-off-by: Jean Delvare
> > Cc: Mika Westerberg
> > Cc: Heikki Krogerus
Hi,
Roger Quadros writes:
> Felipe,
>
> On 03/01/17 14:53, Felipe Balbi wrote:
>>
>> Hi,
>>
>> Roger Quadros writes:
>>> Mathias & Felipe,
>>>
>>> On 17/11/16 17:01, Roger Quadros wrote:
Hi,
Some XHCI controllers e.g. dwc3 based have a broken Port disable [1].
If the
Hi Linus,
On 2017-01-26 10:13, Linus Walleij wrote:
On Fri, Jan 20, 2017 at 7:13 PM, Krzysztof Kozlowski wrote:
Few changes in Exynos PMU driver including one that is needed by pinctrl
driver for runtime PM. We want to move forward with the RPM for our drivers
while keeping still DT ABI.
Thi
On Thu, Jan 26, 2017 at 08:57:30AM +0100, Sven Schmidt wrote:
>
> This patchset is for updating the LZ4 compression module to a version based
> on LZ4 v1.7.3 allowing to use the fast compression algorithm aka LZ4 fast
> which provides an "acceleration" parameter as a tradeoff between
> high compre
Remove unneeded variable used to store return value.
Generated by: scripts/coccinelle/misc/returnvar.cocci
Signed-off-by: Fengguang Wu
---
Is it correct to be returning 0 in the level == 0 case?
dabtree.c |9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
--- a/fs/xfs/scrub/da
On Wed, Jan 25, 2017 at 10:18:28PM +0200, Andy Shevchenko wrote:
> Adding Intel codename Apollo Lake platform device IDs for PCH.
Didn't this originate from Tan Jui Nee and not from you? Please make
sure you have the correct From: here and the other patch as well.
You can use 'git commit --amend
On 01/25/2017 12:50 PM, Marek Szyprowski wrote:
> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
>
> Signed-off-by: Marek Szyprowski
On Thu, 26 Jan 2017 10:19:31 +0100,
Mika Westerberg wrote:
>
> On Thu, Jan 26, 2017 at 09:55:36AM +0100, Linus Walleij wrote:
> > On Wed, Jan 25, 2017 at 4:26 PM, Jean Delvare wrote:
> >
> > > The pinctrl-baytrail driver builds just fine as a module so give
> > > users this option.
> > >
> > > S
On Wed 25-01-17 23:05:38, ys...@foxmail.com wrote:
> From: Yisheng Xie
>
> This patch is to extends soft offlining framework to support
> non-lru page, which already support migration after
> commit bda807d44454 ("mm: migrate: support non-lru movable page
> migration")
>
> When memory corrected
On Thu, Jan 26, 2017 at 10:05:06AM +0100, Jean Delvare wrote:
> Hi Mika and all,
>
> On Wed, 25 Jan 2017 18:16:51 +0200, Mika Westerberg wrote:
> > On Wed, Jan 25, 2017 at 04:26:08PM +0100, Jean Delvare wrote:
> > > The pinctrl-baytrail driver builds just fine as a module so give
> > > users this
> From: gre...@linuxfoundation.org [mailto:gre...@linuxfoundation.org]
> > > From: gre...@linuxfoundation.org [mailto:gre...@linuxfoundation.org]
> > > > > > It's interesting v4.4.44 is not impacted, but actually it needs
> > > > > > both the 2
> > > patches:
> > > > > > i.e. this patch, and the p
Hi Arnd, Olof,
2016-12-26 11:14 GMT+09:00 Masahiro Yamada :
> Enable the Cadence SD/SDIO/eMMC controller. This is used on
> Socionext UniPhier SoC family.
>
> Signed-off-by: Masahiro Yamada
Can you pick up this for ASOC, please?
>
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 i
If a value for tracing file is NULL,
segment fault error can occur using strlen().
Of course, currently the function don't be given NULL value.
But write_tracing_file() can be generally used.
So add the if statement.
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-by: Taeung Song
---
tools/perf/buil
Currently perf ftrace command will select 'function_graph' or 'function'.
So add ftrace.tracer config option to select tracer
# cat ~/.perfconfig
[ftrace]
tracer = function
# perf ftrace usleep 123456 | head -10
<...>-14450 [002] d... 10089.284231: finish_task_switch <-_
On 01/26/2017 09:33 AM, Marek Szyprowski wrote:
> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
>
> Signed-off-by: Marek Szyprowski
On 01/26/2017 08:43 AM, Michal Hocko wrote:
On Wed 25-01-17 21:16:42, Daniel Borkmann wrote:
On 01/25/2017 07:14 PM, Alexei Starovoitov wrote:
On Wed, Jan 25, 2017 at 5:21 AM, Michal Hocko wrote:
On Wed 25-01-17 14:10:06, Michal Hocko wrote:
On Tue 24-01-17 11:17:21, Alexei Starovoitov wrote
Lately commit a349764 made 'function_graph' be the default tracer.
So ftrace.tracer variable can't be NULL but the other code setting default
tracer remained. For this reason, remove it as below.
And use existing DEFAULT_TRACER instead of "function_graph".
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-o
Hi Arnd, Olof,
2016-12-21 1:04 GMT+09:00 Masahiro Yamada :
> Enable the block layer support for MTD devices.
>
> Signed-off-by: Masahiro Yamada
Please check this series, and pick it up for ASOC if it looks good.
Thanks,
>
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
On Thu, Jan 26, 2017 at 10:26:56AM +0100, Takashi Iwai wrote:
> I guess it would break things on some machines if the module loading
> order isn't setup properly. For example, it's known that
> pinctrl-cherrytrail breaks MMC or others if it's loaded too lately.
Yes, if you have rootfs on eMMC and
On Wed, Dec 14, 2016 at 11:19:55AM +0800, Caesar Wang wrote:
> The BOE 10.1" NV101WXMN51 panel is an WXGA TFT LCD panel.
>
> Signed-off-by: Caesar Wang
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> .../devicetree/bindings/display/panel/boe,nv101wxmn51.txt | 7
> +++
> 1
On Wed, Dec 14, 2016 at 11:19:56AM +0800, Caesar Wang wrote:
> 10.1WXGA is a color active matrix TFT LCD module using amorphous silicon
> TFT's as an active switching devices. It can be supported by the
> simple-panel driver.
>
> Read the panel default edid information:
>
> EDID MODE DETAILS
>
Hi.
2017-01-23 18:54 GMT+09:00 Masahiro Yamada :
> Hi.
>
> 2016-12-14 10:33 GMT+09:00 Masahiro Yamada :
>> The timer APIs this header needs are ktime_get(), ktime_add_us(),
>> and ktime_compare(). So, including seems enough.
>> This commit will cut unnecessary header file parsing.
>>
>> Signed-o
This patch shows the fault injection mount option in
f2fs_show_options().
Signed-off-by: Kaixu Xia
---
fs/f2fs/super.c |5 +
1 file changed, 5 insertions(+)
diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c
index 46fd30d..47880b4 100644
--- a/fs/f2fs/super.c
+++ b/fs/f2fs/super.c
@@ -540,6
* r...@redhat.com wrote:
> From: Rik van Riel
>
> Userspace may have programs, especially debuggers, that do not know
> how large the full XSAVE area space is. They pass in a size argument,
> and expect to not get more data than that.
>
> Unfortunately, the current copyout_from_xsaves does th
Hi Peter,
Here's a small update. One 'feature' that is added is kernel filters on
cpu events, so that one can trace scheduling paths and suchlike. While at
it, I also brushed up the filter structure a bit, iirc that's also what
Ingo wanted. And lastly there was one glitch in the filter parsing tha
Commit 2f5177f0fd7e ("sched/cgroup: Fix/cleanup cgroup teardown/init") moved
sched_online_group() from css_online() to css_alloc(). It exposes half-baked
task group into global lists before initializing generic cgroup stuff.
LTP testcase (third in cgroup_regression_test) written for testing
simila
The same LTP testcase triggers NULL deref css->cgroup->kn in the same place.
Commit a5bca2152036 ("cgroup: factor out cgroup_create() out of
cgroup_mkdir()") reordered cgroup construction. Now css created and
set online twice: first in cgroup_create(), second in cgroup_mkdir().
First happens befor
On Fri, Dec 02, 2016 at 09:52:06AM +0100, Gary Bisson wrote:
> Hi all,
>
> This series adds support for the Tianma TM070JDHG30 7" display (1280x800).
> http://usa.tianma.com/products-technology/product/tm070jdhg30-00
> https://boundarydevices.com/product/bd070lic2/
>
> The first patch adds Tianma
On Wed 25-01-17 14:59:45, Yisheng Xie wrote:
> We had considered all of the non-lru pages as unmovable before
> commit bda807d44454 ("mm: migrate: support non-lru movable page
> migration"). But now some of non-lru pages like zsmalloc,
> virtio-balloon pages also become movable. So we can offline s
On Thu, Jan 26, 2017 at 05:33:57AM +0100, Lukas Wunner wrote:
> On Wed, Jan 25, 2017 at 01:54:32PM +0100, Daniel Vetter wrote:
> > On Wed, Jan 25, 2017 at 06:10:57PM +0900, Michel Dänzer wrote:
> > > On 25/01/17 05:33 PM, Markus Trippelsdorf wrote:
> > > > On 2017.01.23 at 09:38 +1000, Dave Airlie
It is currently possible to configure a kernel address filter for a
event that excludes kernel from its traces (attr.exclude_kernel==1).
While in reality this doesn't make sense, the SET_FILTER ioctl() should
return a error in such case, currently it does not. Furthermore, it
will still silently d
This is a cosmetic patch that deals with the address filter structure's
ambiguous fields 'filter' and 'range'. The former stands to mean that the
filter's *action* should be to filter the traces to its address range if
it's set or stop tracing if it's unset. This is confusing and hard on the
eyes,
On Thu, Jan 26, 2017 at 10:20 AM, Marek Szyprowski
wrote:
> Hi Linus,
>
> On 2017-01-26 10:13, Linus Walleij wrote:
>>
>> On Fri, Jan 20, 2017 at 7:13 PM, Krzysztof Kozlowski
>> wrote:
>>
>>> Few changes in Exynos PMU driver including one that is needed by pinctrl
>>> driver for runtime PM. We wa
While supporting file-based address filters for cpu events requires some
extra context switch handling, kernel address filters are easy, since the
kernel mapping is preserved across address spaces. It is also useful as
it permits tracing scheduling paths of the kernel.
This patch allows setting up
* Ingo Molnar wrote:
> So this code:
>
> static inline int xstate_copyout(unsigned int pos, unsigned int count,
> void *kbuf, void __user *ubuf,
> const void *data, const int start_pos,
> const in
From: Daniel Borkmann
> Sent: 26 January 2017 09:37
...
> >> I assume that kvzalloc() is still the same from [1], right? If so, then
> >> it would unfortunately (partially) reintroduce the issue that was fixed.
> >> If you look above at flags, they're also passed to __vmalloc() to not
> >> trigger
On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
wrote:
> Patches in this patchset depends on each other. They are order in such a
> way to make the changes bisectable.
>
> Patch #3 has runtime dependency on #1.
> Patch #5 has runtime dependency on #3.
> Patch #6 has runtime dependency on #4.
>
Currently, the IPMMU/VMSA driver supports 32-bit I/O Virtual Addresses
only, and thus sets io_pgtable_cfg.ias = 32. However, it doesn't force
a 32-bit IOVA space through the IOMMU Domain Geometry.
Hence if a device (e.g. SYS-DMAC) rightfully configures a 40-bit DMA
mask, it will still be handed o
On Tue, Sep 06, 2016 at 04:46:16PM +0200, Maxime Ripard wrote:
> Netron DY is a brand of LCD panels found on SBCs and tablets.
>
> Signed-off-by: Maxime Ripard
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks.
Thierry
signa
On Mon, Jan 23, 2017 at 01:16:37PM -0500, Johannes Weiner wrote:
> We have an elaborate dirty/writeback throttling mechanism inside the
> reclaim scanner, but for that to work the pages have to go through
> shrink_page_list() and get counted for what they are. Otherwise, we
> mess up the LRU order
Am 25.01.2017 um 21:59 schrieb Jani Nikula :
>> But the problem I see here is, that the perl script generates a
>> reST output which I can't use. As an example we can take a look at
>> the man-page builder I shipped in the series.
>
> Sorry, I still don't understand *why* you can't use the same
On Tue, Sep 06, 2016 at 04:46:17PM +0200, Maxime Ripard wrote:
> The E231732 is a 7" panel with a resolution of 800x480.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/panel/panel-simple.c | 26 ++
> 1 file changed, 26 insertions(+)
This is missing a device tre
On Thu, Jan 19, 2017 at 4:05 PM, William Breathitt Gray
wrote:
> The ACCES 104-DIO-48E series provides registers where 8 lines of GPIO
> may be set at a time. This patch add support for the set_multiple
> callback function, thus allowing multiple GPIO output lines to be set
> more efficiently in
Hi Chen-Yu,
On Tue, Jan 24, 2017 at 10:32:20AM +0800, Chen-Yu Tsai wrote:
> The determine_rate helper used ccu_mux_helper_adjust_parent_for_prediv()
> to adjust the parent_rate to account for pre-dividers, but then passed
> the pristine parent clock rate from clk_hw_get_rate() to the round()
> cal
On Thu, Jan 19, 2017 at 4:05 PM, William Breathitt Gray
wrote:
> The ACCES 104-IDIO-16 series provides registers where 8 lines of GPIO
> may be set at a time. This patch add support for the set_multiple
> callback function, thus allowing multiple GPIO output lines to be set
> more efficiently in
On Thu, Jan 19, 2017 at 4:05 PM, William Breathitt Gray
wrote:
> The Diamond Systems GPIO-MM series provides registers where 8 lines of
> GPIO may be set at a time. This patch add support for the set_multiple
> callback function, thus allowing multiple GPIO output lines to be set
> more efficient
Hi,
On Tue, Jan 24, 2017 at 10:32:23AM +0800, Chen-Yu Tsai wrote:
> On the Allwinner A80 SoC, the PLL lock status indicators are grouped
> together in a separate register, as opposed to being scattered in each
> PLL's configuration register.
>
> Add a flag to support this.
>
> Signed-off-by: Che
On Thu, Jan 19, 2017 at 4:05 PM, William Breathitt Gray
wrote:
> The WinSystems WS16C48 provides registers where 8 lines of GPIO may be
> set at a time. This patch add support for the set_multiple callback
> function, thus allowing multiple GPIO output lines to be set more
> efficiently in groups
On Mon, Jan 23, 2017 at 01:16:38PM -0500, Johannes Weiner wrote:
> Memory pressure can put dirty pages at the end of the LRU without
> anybody running into dirty limits. Don't start writing individual
> pages from kswapd while the flushers might be asleep.
>
> Signed-off-by: Johannes Weiner
I do
On Thu 26-01-17 10:36:49, Daniel Borkmann wrote:
> On 01/26/2017 08:43 AM, Michal Hocko wrote:
> > On Wed 25-01-17 21:16:42, Daniel Borkmann wrote:
[...]
> > > I assume that kvzalloc() is still the same from [1], right? If so, then
> > > it would unfortunately (partially) reintroduce the issue that
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