From: Gustavo Padovan
Closing the timeline without waiting all fences to signal is not
a critical failure, it is just bad usage from userspace so avoid
calling WARN_ON in this case.
Signed-off-by: Gustavo Padovan
---
drivers/staging/android/sw_sync.c | 2 +-
1 file changed, 1 insertion(+), 1 d
From: Gustavo Padovan
SW_SYNC allows to run tests on the sync_file framework via debugfs on
/sync/sw_sync
Opening and closing the file triggers creation and release of a sync
timeline. To create fences on this timeline the SW_SYNC_IOC_CREATE_FENCE
ioctl should be used. To increment the timeline
From: Gustavo Padovan
Fix paths in the comments.
Signed-off-by: Gustavo Padovan
---
drivers/staging/android/sync_debug.c | 2 +-
drivers/staging/android/sync_debug.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/android/sync_debug.c
b/drivers/staging/a
Open call is ignoring the return code from reset call and can
potentially continue even though reset call failed.
If reset_required module parameter is set, this patch is going
to validate the return code and will abort open if reset fails.
Signed-off-by: Sinan Kaya
Reviewed-by: Baptiste Reynal
A recent change accidentally introduced a 64-bit division in torture_shutdown,
which fails to build on 32-bit architectures:
kernel/built-in.o: In function `torture_shutdown':
:(.text+0x4b29a): undefined reference to `__aeabi_uldivmod'
This converts the function to use ktime_t instead, which also
From: Gustavo Padovan
Sync Framework was de-staged to drivers/dma-buf/, so remove it entries
in the TODO file.
Signed-off-by: Gustavo Padovan
---
drivers/staging/android/TODO | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/staging/android/TODO b/drivers/staging/android/TODO
On 06/18/2016 07:04 PM, Marcel Ziswiler wrote:
Remove commas from unit addresses as suggested by Rob Herring upon me
posting initial Apalis TK1 support:
http://article.gmane.org/gmane.linux.ports.tegra/26608
Acked-by: Stephen Warren
The new PIO mode for the dwc audio driver causes a link failure
when it is built as a loadable module but the audio driver is built-in:
sound/built-in.o: In function `i2s_irq_handler':
:(.text+0x58c64): undefined reference to `dw_pcm_push_tx'
sound/built-in.o: In function `dw_i2s_probe':
:(.text+0
On Fri, Jun 17, 2016 at 12:04:34PM +0200, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong
> ---
> Documentation/devicetree/bindings/clock/qcom,gcc.txt | 1 +
> Documentation/devicetree/bindings/clock/qcom,lcc.txt | 1 +
> 2 files changed, 2 insertions(+)
Acked-by: Rob Herring
On Mon, Jun 20, 2016 at 04:28:23PM +0200, Peter Zijlstra wrote:
> On Mon, Jun 20, 2016 at 02:15:11PM +0200, Jiri Olsa wrote:
> > Adding dont_balance bool into struct sched_entity,
> > to mark tasks which are rebalanced based on affinity.
> >
> > It's used only when REBALANCE_AFFINITY feature is
>
so is there really an issue? sounds like KISS principle can apply
On Mon, Jun 20, 2016 at 7:46 AM, Thomas Gleixner wrote:
> On Mon, 20 Jun 2016, Arjan van de Ven wrote:
>> On Mon, Jun 20, 2016 at 6:56 AM, Thomas Gleixner wrote:
>> >
>> > 2) Cut off at 37hrs for HZ=1000. We could make this config
Hi,
On 06/20/2016 10:08 AM, Al Viro wrote:
> On Mon, Jun 20, 2016 at 09:25:12AM -0400, Oleg Drokin wrote:
>> It looks like this patch was totally forgotten?
>> I don't see it in neither vfs nor nfs trees and yet it fixes a very easy to
>> cause
>> crash in nfs code. And I think it's unrelated to
On Sat, Jun 18, 2016 at 04:56:18PM -0400, Brian Gerst wrote:
> thread_saved_pc() was using a completely bogus method to get the return
> address. Since switch_to() was previously inlined, there was no sane way
> to know where on the stack the return address was stored. Now with the
> frame of a s
The switch ID is located at address 0x3 of every Port Registers bank.
But not all Marvell switches have their Port Registers SMI Addresses
starting at 0x10. 88E6060 starts at 0x8 and 88E6390 starts at 0x0.
Add this data in the info structure and use it in the detection code.
Signed-off-by: Vivie
Extract the common detection code which assigns the info structure to
the chip given the read switch ID.
Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
---
drivers/net/dsa/mv88e6xxx.c | 64 +
1 file changed, 30 insertions(+), 34 deletions(-)
Use the optional variant to get the reset GPIO line, instead of checking
for the -ENOENT error.
Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
---
drivers/net/dsa/mv88e6xxx.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx.c b
After allocating the chip structure, pass it a compatible info pointer.
The compatible info structure will be used later to describe how to
access the switch registers and where to read the switch ID.
For the standard MDIO probe, get it from the device node data. For the
legacy DSA driver probing
When the SMI address of the switch chip is zero, the chip assumes to be
the only one on the SMI master bus and thus responds to all its known
SMI devices addresses (port registers, Global2, etc.)
When its SMI address is not zero, some chips (e.g. 88E6352) use an
indirect access through two SMI Com
The chip smi_mutex mutex is used to protect the access to the internal
switch registers, not only the Multi-chip Addressing Mode, as commented.
Since we will isolate SMI-specific pieces of code, avoid the confusion
now by renaming smi_mutex to reg_lock. No functional changes here.
Signed-off-by:
On Jun 20, 2016 6:02 AM, "Michal Hocko" wrote:
>
> On Fri 17-06-16 13:00:41, Andy Lutomirski wrote:
> > We should account for stacks regardless of stack size. Move it into
> > account_kernel_stack.
> >
> > Fixes: 12580e4b54ba8 ("mm: memcontrol: report kernel stack usage in cgroup2
> > memory.sta
From: Yisen Zhuang
Date: Mon, 20 Jun 2016 15:12:34 +0800
>
>
> 在 2016/6/15 18:30, Yisen Zhuang 写道:
>> Hi David,
>>
>> Thanks for your suggestions.
>>
>> Please see my comments below.
>>
>> Thanks,
>>
>> Yisen
>>
>> 在 2016/6/15 13:41, David Miller 写道:
>>> From: Yisen Zhuang
>>> Date: Mon,
Add an helper function to isolate SMI specific assignments and checks.
This function will later help choosing the different SMI accesses based
of the compatible info.
Since the chip structure is already allocated in the legacy probe, use
the mv88e6xxx_reg_read access routine instead of __mv88e6xx
The chip->ds and ds->slave_mii_bus assignments are common to both legacy
and new MDIO probing and are already done in the later setup code.
Remove the duplicated assignments from the MDIO probing code.
Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
---
drivers/net/dsa/mv88e6xxx.c | 3 -
On 06/17/2016 04:16 PM, Nick Dyer wrote:
> There are different datatypes available from a maXTouch chip. Add
> support to retrieve reference data as well.
>
> Signed-off-by: Nick Dyer
> ---
> drivers/input/touchscreen/atmel_mxt_ts.c | 58
>
> 1 file changed, 51
On 05/20/2016 04:03 PM, Aleksey Makarov wrote:
Hi Rafael,
Can you consider this patch set for queuing up please?
You approved ACPI part. I believe it's 2/4 and 3/4.
https://lkml.kernel.org/g/CAJZ5v0hdoLTfjrD8+WxSoxM48dqbZK2KwY_h+63kHKHKgO=j...@mail.gmail.com
1/4 is ACKed by Rob Herri
A cleanup to include the headers correctly caused another build problem:
arch/arm/mach-mvebu/kirkwood-pm.c:70:13: error: redefinition of
'kirkwood_pm_init'
arch/arm/mach-mvebu/kirkwood-pm.h:23:20: note: previous definition of
'kirkwood_pm_init' was here
The underlying issue is that kirkwood-pm.
Add an helper function to allocate the chip structure at the beginning
of the probe functions. It will be used to initialize the SMI access.
Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
---
drivers/net/dsa/mv88e6xxx.c | 39 +++
1 file changed, 27 in
From: Gustavo Padovan
Hi Greg,
This is the last step in the Sync Framwork de-stage task. It de-stage
the SW_SYNC validation framework and the sync_debug info debugfs file.
The first 3 patches are clean up and improvements and the rest is preparation
to de-stage and then finally the actual de-st
This patchset factorizes the legacy and new SMI probing and abstracts
the switch register accesses. This simplifies adding support for new
chips or alternative register accesses.
This will allow us to use a compatible chip info to describe how to
access the SMI device and its switch ID register at
On Mon, 2016-06-20 at 12:53 -0300, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Fix paths in the comments.
Why is it useful to have the path or filename embedded
in the file at
all?
On Thu 16-06-16 10:07:09, Dan Carpenter wrote:
> My static checker complains that this can underflow if arg is negative
> which is true.
>
> Signed-off-by: Dan Carpenter
How come? (1 << 30) fits even into 32-bit signed type. So where's the
problem?
It's not really possible to call d_splice_alias with a hashed
dentry no matter what, so remove the stale comment indicating
otherwise. The only user of this functionality was fixed
long ago according to Al.
Signed-off-by: Oleg Drokin
---
Catching this up before it gets forgotten again and confuse
On 06/20/2016 08:20 AM, Rosen, Rami wrote:
> Hi all,
>
> A very limited review below.
>
> +
> + /* get capabilities of particular feature */
> + ENA_ADMIN_GET_FEATURE = 8,
>
> Instead /* get capabilities SHOULD BE: /* set capabilities .
> +
> + /* get capabilities of particular
On Fri, Jun 17, 2016 at 11:51:03AM +0200, Neil Armstrong wrote:
> In case of OF probing, the driver fails to initialize :
> - gpio_chip.base must be -1
> - irq_summary must be either -1 or valid
> - There is no way to use the other configurations
>
> Add OF parsing function to complete the HW conf
From: Gustavo Padovan
SW_SYNC should never be used by other pieces of the kernel apart from
sync_debug as it is only a Sync File Validation Framework, so hide any
info to avoid confuse this with a standard kernel internal API.
Signed-off-by: Gustavo Padovan
---
drivers/staging/android/sw_sync.
2016-06-20 Joe Perches :
> On Mon, 2016-06-20 at 12:53 -0300, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > Fix paths in the comments.
>
> Why is it useful to have the path or filename embedded
> in the file at
> all?
I just kept it as is. Thinking about this now I don't see
this as
On 20/06/2016 17:09, Hans Verkuil wrote:
> On 06/17/2016 04:16 PM, Nick Dyer wrote:
>> @@ -2325,11 +2344,20 @@ static int mxt_vidioc_querycap(struct file *file,
>> void *priv,
>> static int mxt_vidioc_enum_input(struct file *file, void *priv,
>> struct v4l2_input *
+ linux-mmc, Ulf
On Mon, Jun 20, 2016 at 06:41:26PM +0530, Kishon Vijay Abraham I wrote:
> On Friday 13 May 2016 04:13 AM, Brian Norris wrote:
> > From: Shawn Lin
> >
> > According to the databook, 10.2us is the max time for dll to be ready to
> > work. However in testing, some chips need 20us f
On Fri, Jun 17, 2016 at 12:15:35PM +0200, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong
> ---
> .../bindings/pinctrl/qcom,mdm9615-pinctrl.txt | 152
> +
> 1 file changed, 152 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pinctrl/qcom,md
Hi Afzal,
On 06/20/2016 03:23 AM, Keerthy wrote:
>
>
> On Monday 20 June 2016 12:35 PM, Mohammed, Afzal wrote:
>> Hi,
>>
>> J, KEERTHY wrote on Monday, June 20, 2016 9:22 AM:
>>
>>> pruss hwmod RSTST register wrongly points to PWRSTCTRL register in
>>> case of
>>> am43xx. Fix the RSTST register
On 06/17/2016 04:16 PM, Nick Dyer wrote:
> Function 54 implements access to various RMI4 diagnostic features.
>
> This patch adds support for retrieving this data. It registers a V4L2
> device to output the data to user space.
>
> Signed-off-by: Nick Dyer
> ---
> drivers/input/rmi4/Kconfig
From: Thor Thayer
This patch set adds the Ethernet EDAC and memory initialization functions
for Altera's Arria10 peripherals. The ECC memory init functions are common
to all the peripheral memory buffers (to follow in later patches).
Thor Thayer (7):
EDAC, altera: Add panic flag check to A10 I
Hello Alessandro and Alexandre,
I noticed an interesting cmos_rtc.rtc.aie_timer on a Stratus machine
running the 4.6 kernel, with an expiration time that puts the alarm way
out into next year. This is easily reproducible on this machine by
setting a wakealarm sometime in the near future, then reb
On Fri, Jun 17, 2016 at 2:02 AM, Ingo Molnar wrote:
>
> * Kees Cook wrote:
>
>> From: Thomas Garnier
>>
>> Minor change that allows early boot physical mapping of PUD level virtual
>> addresses. The current implementation expects the virtual address to be
>> PUD aligned. For KASLR memory randomi
Signed-off-by: M'boumba Cedric Madianga
---
arch/arm/configs/stm32_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 709e606..411eb0a 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32
Hi,
On Mon, Jun 20, 2016 at 9:19 AM, Brian Norris wrote:
> + linux-mmc, Ulf
>
> On Mon, Jun 20, 2016 at 06:41:26PM +0530, Kishon Vijay Abraham I wrote:
>> On Friday 13 May 2016 04:13 AM, Brian Norris wrote:
>> > From: Shawn Lin
>> >
>> > According to the databook, 10.2us is the max time for dll
This patchset adds support for the I2C controller embedded in STM32F4xx SoC.
It enables I2C transfer in interrupt mode with Standard-mode and Fast-mode bus
speed.
Changes since v2:
- Group I2C pins definitions in the device tree (Maxime)
- Suffix I2C phandle with part number (Maxime)
- Remov busy
This patch adds support for the STM32F4 I2C controller.
Signed-off-by: M'boumba Cedric Madianga
---
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-stm32f4.c | 863 +++
3 files changed, 874 insertions(
Signed-off-by: M'boumba Cedric Madianga
---
arch/arm/boot/dts/stm32429i-eval.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index 6bfc595..e95657f 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/ar
Signed-off-by: Patrice Chotard
Signed-off-by: M'boumba Cedric Madianga
---
arch/arm/boot/dts/stm32f429.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 434d4b9..4eaa107 100644
--- a/arch/arm
On 06/20/2016 06:18 PM, Nick Dyer wrote:
> On 20/06/2016 17:09, Hans Verkuil wrote:
>> On 06/17/2016 04:16 PM, Nick Dyer wrote:
>>> @@ -2325,11 +2344,20 @@ static int mxt_vidioc_querycap(struct file *file,
>>> void *priv,
>>> static int mxt_vidioc_enum_input(struct file *file, void *priv,
>>>
This patch adds documentation of device tree bindings for the STM32 I2C
controller.
Signed-off-by: M'boumba Cedric Madianga
---
.../devicetree/bindings/i2c/i2c-stm32.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i
On Fri, Jun 17, 2016 at 12:25:19PM +0200, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong
> ---
> .../devicetree/bindings/phy/qcom,usb-hsic-phy.txt | 95
> ++
> 1 file changed, 95 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/phy/qcom,usb-hsi
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
to support a common compatibility string for all ethernet
FIFOs in the DT.
Signed-off-by: Thor Thayer
---
v2 Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to ethernet private data.
Hi,
On Mon, Jun 20, 2016 at 11:44 PM, Maxime Ripard
wrote:
> Hi,
>
> On Tue, Jun 14, 2016 at 09:19:58PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Jun 14, 2016 at 8:59 PM, Quentin Schulz
>> wrote:
>> > Hi,
>> >
>> > On 13/06/2016 15:04, Chen-Yu Tsai wrote:
>> >> Hi,
>> >>
>> >> On Mon, Jun 13, 2016 a
On Mon, Jun 20, 2016 at 12:03:37PM -0400, Vivien Didelot wrote:
> When the SMI address of the switch chip is zero, the chip assumes to be
> the only one on the SMI master bus and thus responds to all its known
> SMI devices addresses (port registers, Global2, etc.)
>
> When its SMI address is not
On 06/19, Andy Lutomirski wrote:
>
> On Sun, Jun 19, 2016 at 2:19 PM, Oleg Nesterov wrote:
> >
> > And this leads to another question, why do we actually need to set/clear
> > TS_COMPAT in set_personality_ia32() ??
>
> Something's clearly buggy there, considering that
> set_personality_64bit() doe
On 06/19, Andy Lutomirski wrote:
>
> On Sat, Jun 18, 2016 at 10:02 AM, Andy Lutomirski wrote:
> Step 1: for 4.7 and for -stable, introduce TS_I386_REGS_POKED. Set it
> in putreg32. Use it in syscall_get_error, get_nr_restart_syscall,
> etc. Clear it in do_signal.
do_signal() won't be necessari
Signed-off-by: Patrice Chotard
Signed-off-by: M'boumba Cedric Madianga
---
arch/arm/boot/dts/stm32f429.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 434d4b9..4eaa107 100644
--- a/arch/arm
On Mon, Jun 20, 2016 at 6:36 AM, Michal Hocko wrote:
> On Fri 17-06-16 13:00:42, Andy Lutomirski wrote:
>> If CONFIG_VMAP_STACK is selected, kernel stacks are allocated with
>> vmalloc_node.
>
> I like this! It also reduces demand for higher order (order-2) pages
> considerably which is a great pl
On Mon, Jun 20, 2016 at 04:30:03PM +0200, Peter Zijlstra wrote:
> On Mon, Jun 20, 2016 at 02:15:12PM +0200, Jiri Olsa wrote:
> > Introducing idle enter/exit balance callbacks to keep
> > balance.idle_cpus_mask cpumask of current idle cpus
> > in system.
> >
> > It's used only when REBALANCE_AFFINI
This patch adds support for the STM32F4 I2C controller.
Signed-off-by: M'boumba Cedric Madianga
---
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-stm32f4.c | 863 +++
3 files changed, 874 insertions(
This patchset adds support for the I2C controller embedded in STM32F4xx SoC.
It enables I2C transfer in interrupt mode with Standard-mode and Fast-mode bus
speed.
Changes since v2:
- Group I2C pins definitions in the device tree (Maxime)
- Suffix I2C phandle with part number (Maxime)
- Remov busy
This patch adds documentation of device tree bindings for the STM32 I2C
controller.
Signed-off-by: M'boumba Cedric Madianga
---
.../devicetree/bindings/i2c/i2c-stm32.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i
On Mon, Jun 20, 2016 at 8:24 AM, Oleg Nesterov wrote:
> On 06/19, Andy Lutomirski wrote:
>>
>> On Sat, Jun 18, 2016 at 10:02 AM, Andy Lutomirski
>> wrote:
>> Step 1: for 4.7 and for -stable, introduce TS_I386_REGS_POKED. Set it
>> in putreg32. Use it in syscall_get_error, get_nr_restart_syscal
On 13 June 2016 at 20:16, Chunyan Zhang wrote:
> CoreSight STM device allows direct mapping of the channel regions to
> userspace for zero-copy writing. To support this ability, the STM
> freamwork has provided a hook 'mmio_addr', this patch just implemented
> this hook for CoreSight STM.
>
> This
On Fri, Jun 17, 2016 at 04:21:05PM +0530, Laxman Dewangan wrote:
> The clock IP used on the Maxim PMICs max77686 and max77802 are
> same. The configuration of clock register is also same except
> the number of clocks.
>
> Define the common DT binding file for the clocks of Maxim PMICs
> MAX77686 a
On Mon, Jun 20, 2016 at 09:50:26AM -0600, Stephen Warren wrote:
> On 06/18/2016 07:04 PM, Marcel Ziswiler wrote:
> > Remove commas from unit addresses as suggested by Rob Herring upon me
> > posting initial Apalis TK1 support:
> >
> > http://article.gmane.org/gmane.linux.ports.tegra/26608
>
> Ack
Setting TS_COMPAT in ptrace is wrong: if we happen to do it during
syscall entry, then we'll confuse seccomp and audit. (The former
isn't a security problem: seccomp is currently entirely insecure if a
malicious ptracer is attached.) As a minimal fix, this patch adds a
new flag TS_I386_REGS_POKED
Am Montag, 20. Juni 2016, 11:01:47 schrieb Theodore Ts'o:
Hi Theodore,
>
> So simply doing chacha20 encryption in a tight loop in the kernel
> might not be a good proxy for what would actually happen in real life
> when someone calls getrandom(2). (Another good question to ask is
> when someone
On Fri, Jun 17, 2016 at 04:21:06PM +0530, Laxman Dewangan wrote:
> Maxim has used the same clock IP on multiple PMICs like MAX77686,
> MAX77802, MAX77620. Only differences are the number of clocks
> from these PMICs like MAX77686 has 3 clocks output, MAX776802 have
> two clock output and MAX77620 h
On Fri, Jun 17, 2016 at 12:42:09PM +0200, Neil Armstrong wrote:
> Add Sierra Wireless as swi vendor prefix.
>
> Signed-off-by: Neil Armstrong
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/
On 06/20/2016 10:40 AM, Thierry Reding wrote:
On Mon, Jun 20, 2016 at 09:50:26AM -0600, Stephen Warren wrote:
On 06/18/2016 07:04 PM, Marcel Ziswiler wrote:
Remove commas from unit addresses as suggested by Rob Herring upon me
posting initial Apalis TK1 support:
http://article.gmane.org/gmane.
Heiko,
On Sat, Jun 18, 2016 at 5:20 AM, Heiko Stübner wrote:
> Am Montag, 13. Juni 2016, 16:04:34 schrieb Douglas Anderson:
>> The "phyctrl_frqsel" is described in the Arasan datasheet [1] as "the
>> frequency range of DLL operation". Although the Rockchip variant of
>> this PHY has different ra
of SPI protocols
supported by the SPI controller. Using both this list and the SFDP
settings, the spi-nor framework can now select the best match for SPI
protocols supported by both the memory and the controller.
This series of patches is based onto next-20160620.
It was tested on a sama5d2
The patch checks whether the Quad Enable bit is already set in the Status
Register. If so, the function exits immediately with a successful return
code. Otherwise, a message is now printed telling we're setting the
non-volatile bit.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi-nor/spi-nor.
This patch provides an alternative mean to support memory above 16MiB
(128Mib) by replacing 3byte address op codes by their associated 4byte
address versions.
Using the dedicated 4byte address op codes doesn't change the internal
state of the SPI NOR memory as opposed to using other means such as
This patch documents the DT bindings for the driver of the Atmel QSPI
controller embedded inside sama5d2x SoCs.
Signed-off-by: Cyrille Pitchen
Acked-by: Rob Herring
Acked-by: Nicolas Ferre
---
.../devicetree/bindings/mtd/atmel-quadspi.txt | 32 ++
1 file changed, 32 in
On Mon, Jun 20, 2016 at 09:25:18AM -0700, Doug Anderson wrote:
> On Mon, Jun 20, 2016 at 9:19 AM, Brian Norris
> wrote:
> > Ulf,
> >
> > I see I didn't CC you or linux-mmc on this patch series. Please let me
> > know if I should resend, or if you can pick these up off of LKML -- Doug
> > gave nic
The set_quad_mode() function is no longer used, so we remove it.
This patch is not squashed into the previous patch on purpose for
readiness issue and to ease the review process of the whole series.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi-nor/spi-nor.c | 24
This patch changes the prototype of spi_nor_scan(): its 3rd parameter
is replaced by a const struct spi_nor_modes pointer, which tells the
spi-nor framework about which SPI protocols are supported by the SPI
controller.
Besides, this patch also introduces a new spi_nor_basic_flash_parameter
struct
path cleanup in
> gen_pci_parse_request_of_pci_ranges() instead.
>
> Signed-off-by: Bjorn Helgaas
The kernelci.org bot has reported[0] new qemu-aarch64
(arm64-defconfig) boot failures[1][2] in next-20160620. I've
bisected[3] this boot failure down to this patch, and confirmed
reverting it on
This patch adds supports for SFDP (JESD216B) 4-byte Address Instruction
Table. This table is optional but when available, we parse it to get the
4-byte address op codes supported by the memory.
Using these op codes is stateless as opposed to entering the 4-byte
address mode or setting the Base Addr
On Sat, Jun 18, 2016 at 01:58:30PM +0530, Bhaktipriya Shridhar wrote:
> alloc_workqueue replaces deprecated create_workqueue().
>
> A dedicated workqueue has been used since the workitem (viz
> &fault->work), is involved in IO page-fault handling.
> WQ_MEM_RECLAIM has been set to guarantee forward
This patch adds support the the JESD216B standard and parse the SFDP
tables to dynamically initialize the spi_nor_basic_flash_parameter
structure.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi-nor/spi-nor.c | 423 +-
include/linux/mtd/spi-nor.h |
This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI
controller.
Signed-off-by: Cyrille Pitchen
Acked-by: Nicolas Ferre
---
drivers/mtd/spi-nor/Kconfig | 9 +
drivers/mtd/spi-nor/Makefile| 1
Hello Sir/Madam,
You have been chosen to benefit from Bernard Arnault Philanthropic Donation.
For more contact the email below.
Email:: bernardarnaul...@gmail.com
Faithfully,
Bernard Arnault
Before this patch, m25p80_read() supported few SPI protocols:
- regular SPI 1-1-1
- SPI Dual Output 1-1-2
- SPI Quad Output 1-1-4
On the other hand, all other m25p80_*() hooks only supported SPI 1-1-1.
This patch adds support to all currently existing SPI protocols to
cover as many protocols as po
Hi,
On 20-06-16 18:30, Chen-Yu Tsai wrote:
Hi,
On Mon, Jun 20, 2016 at 11:44 PM, Maxime Ripard
wrote:
Hi,
On Tue, Jun 14, 2016 at 09:19:58PM +0800, Chen-Yu Tsai wrote:
On Tue, Jun 14, 2016 at 8:59 PM, Quentin Schulz
wrote:
Hi,
On 13/06/2016 15:04, Chen-Yu Tsai wrote:
Hi,
On Mon, Jun 13
On Thu, 2016-06-16 at 23:26 +0200, Daniel Lezcano wrote:
> The init functions do not return any error. They behave as the following:
>
> - panic, thus leading to a kernel crash while another timer may work and
>make the system boot up correctly
>
> or
>
> - print an error and let t
On 20/06/16 11:19, Mars Cheng wrote:
On Mon, 2016-06-20 at 10:31 +0200, Matthias Brugger wrote:
On 14/06/16 04:20, Mars Cheng wrote:
This adds basic chip support for MT6755 SoC.
Signed-off-by: Mars Cheng
---
arch/arm64/boot/dts/mediatek/Makefile |1 +
arch/arm64/boot/dts/m
Use the optional variant to get the reset GPIO line, instead of checking
for the -ENOENT error.
Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
---
drivers/net/dsa/mv88e6xxx.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx.c b
In the MDIO probing function, dev is already assigned to &mdiodev->dev
and np is already assigned to mdiodev->dev.of_node, so use them.
Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
---
drivers/net/dsa/mv88e6xxx.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
The chip->ds and ds->slave_mii_bus assignments are common to both legacy
and new MDIO probing and are already done in the later setup code.
Remove the duplicated assignments from the MDIO probing code.
Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
---
drivers/net/dsa/mv88e6xxx.c | 3 -
When the SMI address of the switch chip is zero, the chip assumes to be
the only one on the SMI master bus and thus responds to all its known
SMI devices addresses (port registers, Global2, etc.)
When its SMI address is not zero, some chips (e.g. 88E6352) use an
indirect access through two SMI Com
Replace goto err_gpio by return ret
Signed-off-by: Helen Koike
---
Changes since v1:
- this is a new patch in the series
sound/soc/codecs/tpa6130a2.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c
ind
The switch ID is located at address 0x3 of every Port Registers bank.
But not all Marvell switches have their Port Registers SMI Addresses
starting at 0x10. 88E6060 starts at 0x8 and 88E6390 starts at 0x0.
Add this data in the info structure and use it in the detection code.
Signed-off-by: Vivie
Add an helper function to isolate SMI specific assignments and checks.
This function will later help choosing the different SMI accesses based
of the compatible info.
Since the chip structure is already allocated in the legacy probe, use
the mv88e6xxx_reg_read access routine instead of __mv88e6xx
The mv88e6xxx_table array and the mv88e6xxx_lookup_info function are
static, so remove the table and size arguments from the lookup function.
Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
---
drivers/net/dsa/mv88e6xxx.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletio
The chip smi_mutex mutex is used to protect the access to the internal
switch registers, not only the Multi-chip Addressing Mode, as commented.
Since we will isolate SMI-specific pieces of code, avoid the confusion
now by renaming smi_mutex to reg_lock. No functional changes here.
Signed-off-by:
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