Hi Jiancheng,
On 26 February 2016 at 05:11, Jiancheng Xue wrote:
[..]
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> index 0dc9275..c86d7cf 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -37,6 +37,12 @@ config SPI_FSL_QUADSPI
>
Hi,
On Fri, Mar 4, 2016 at 3:46 PM, Karl Palsson wrote:
>> + /*
>> + * Sleep for 10-15 ms after the reset to let it finish.
>> + *
>> + * It's been confirmed on at least one version of the controller
>> + * that this is a requirement that this is a requirement in order for
The primary use case for devm_memremap_pages() is to allocate an
memmap array from persistent memory. That capabilty requires
vmem_altmap which requires SPARSEMEM_VMEMMAP.
Also, without SPARSEMEM_VMEMMAP the addition of ZONE_DEVICE expands
ZONES_WIDTH and triggers the:
"Unfortunate NUMA and NUMA
On Sat, Mar 05, 2016 at 12:28:38AM +, David Woodhouse wrote:
> On Fri, 2016-03-04 at 16:22 -0800, Brian Norris wrote:
> >
> > ...but, does anyone care about XIP / MTD_XIP then, if the first two
> > examples we have both have long-standing build issues?
>
> I think there are people trying to m
From: Vishal Verma
If firmware doesn't implement any of the ARS commands, take that to
mean that ARS is unsupported, and continue to initialize regions without
bad block lists. We cannot make the assumption that ARS commands will be
unconditionally supported on all NVDIMMs.
Reported-by: Haozhong
Andrew, sorry, ignore this, I fumble fingered a ^R in bash and sent
this. I'm going to include this in a pull request to Linus.
On Fri, Mar 4, 2016 at 4:46 PM, Dan Williams wrote:
> From: Vishal Verma
>
> If firmware doesn't implement any of the ARS commands, take that to
> mean that ARS is uns
+ others
On Fri, Feb 26, 2016 at 11:50:28AM +0100, Rafał Miłecki wrote:
> From: Brian Norris
>
> Using KSEG0ADDR makes code highly MIPS dependent and not portable.
> Thanks to the fix a68f376 ("MIPS: io.h: Define `ioremap_cache'") we can
> use ioremap_cache which is generic and supported on MIPS
Hi,
This is a redesign of the patch series that fixes various interface
problems with the existing "zero out this part of a block device"
code. BLKZEROOUT2 is gone.
The first patch is still a fix to the existing BLKZEROOUT ioctl to
invalidate the page cache if the zeroing command to the underlyi
After much discussion, it seems that the fallocate feature flag
FALLOC_FL_ZERO_RANGE maps nicely to SCSI WRITE SAME; and the feature
FALLOC_FL_PUNCH_HOLE maps nicely to the devices that have been
whitelisted for zeroing SCSI UNMAP. Both flags require that
FALLOC_FL_KEEP_SIZE are set, both return E
Invalidate the page cache (as a regular O_DIRECT write would do) to avoid
returning stale cache contents at a later time.
v5: Refactor the 4.4 refactoring of the ioctl code into separate functions.
Split the page invalidation and the new ioctl into separate patches.
Signed-off-by: Darrick J. Wong
Make sure that the offset and length arguments that we're using to
construct WRITE SAME and DISCARD requests are actually aligned to the
logical block size. Failure to do this causes other errors in other
parts of the block layer or the SCSI layer because disks don't support
partial logical block
On Fri, Mar 04, 2016 at 04:03:04PM -0800, Paul E. McKenney wrote:
> On Fri, Mar 04, 2016 at 02:45:01PM -0800, Luis R. Rodriguez wrote:
> > The current documentation refers to using set_memory_wc() as a
> > possible hole strategy when you have overlapping ioremap() regions,
> > that's incorrect as s
Hi Linus, please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm libnvdimm-fixes
...to receive one straggling fix for NVDIMM support.
The KVM/QEMU enabling for NVDIMMs has recently reached the point where
it is able to accept some ACPI _DSM requests from a guest VM. How
Hi,
On Fri, Mar 4, 2016 at 4:33 PM, Doug Anderson wrote:
> Michael,
>
> On Fri, Mar 4, 2016 at 4:09 PM, Michael Niewoehner
> wrote:
From testing and trying to make sense of the documentation, it appears
that a 10 ms delay is needed after resetting the core to make sure that
every
In commit b70af9bef49b ("mtd: nand: increase ready wait timeout and
report timeouts"), we increased the likelihood of scheduling during
nand_wait(). This makes us more likely to hit the time_before(...)
condition, since a lot of time may pass before we get scheduled again.
Now, the loop was alread
This is a driver for ACPI-based keyboard backlight LEDs found on
Chromebooks. The driver locates \\_SB.KBLT ACPI device and exports
backlight as "chromeos::kbd_backlight" LED class device in sysfs.
Signed-off-by: Simon Que
Signed-off-by: Duncan Laurie
Signed-off-by: Dmitry Torokhov
---
Changes
Hi Roger,
On Fri, Feb 19, 2016 at 11:15:25PM +0200, Roger Quadros wrote:
> The OMAP GPMC module has certain registers dedicated for NAND
> access and some NAND bits mixed with other GPMC functionality.
>
> For the NAND dedicated registers we have the struct gpmc_nand_regs.
>
> The NAND driver ne
+ Boris
On Fri, Feb 19, 2016 at 11:15:39PM +0200, Roger Quadros wrote:
> The GPMC WAIT pin status are now available over gpiolib.
> Update the omap_dev_ready() function to use gpio instead of
> directly accessing GPMC register space.
>
> Signed-off-by: Roger Quadros
> ---
> .../devicetree/bindi
On Fri, Mar 4, 2016 at 5:23 PM, Dmitry Torokhov
wrote:
> This is a driver for ACPI-based keyboard backlight LEDs found on
> Chromebooks. The driver locates \\_SB.KBLT ACPI device and exports
> backlight as "chromeos::kbd_backlight" LED class device in sysfs.
>
> Signed-off-by: Simon Que
> Signed-
On Thu, 2016-03-03 at 13:53 -0800, Dan Williams wrote:
> On a platform where 'Persistent Memory' and 'System RAM' are mixed
> within a given sparsemem section, trim the namespace and notify about the
> sub-optimal alignment.
>
> Cc: Toshi Kani
> Cc: Ross Zwisler
> Signed-off-by: Dan Williams
>
Hi Adrian,
On 2016/3/4 20:12, Adrian Hunter wrote:
[...]
I don't know that disabling clocks is necessarily the right thing to do if
the resume fails. You might want to consider what happens if the system
tries to use the device when it is in that state. It's been a long time
since I did any
On Fri, Feb 19, 2016 at 11:15:32PM +0200, Roger Quadros wrote:
> Add compatible id and interrupts. The NAND interrupts are
> provided by the GPMC controller node.
>
> Signed-off-by: Roger Quadros
> ---
> Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 17 +
> 1 file changed
From: Liang Zhen
This is implementation of LNet Drop Rule, which can randomly drop
LNet messages at specified rate.
LNet Drop Rule can only be applied to receive side of message. User
can add drop_rule either on end point of cluster (client/server) or
on LNet routers.
Here are lctl command to c
This batch merges the remaining LNet patches from the OpenSFS
branch for the upstream client. Once merged the LNet code
will be up to date with the latest production code. Only style
issues are remaining. Still future patches being developed
for LNet will be landed to the upstream client as soon as
Sometime ago a patch was submitted to duplicate the
proc_call_handler code in the LNet layer. This was
due to the thinking libcfs was not used by the LNet
layer. This was a wrong assumption so lets make LNet
use the lprocfs_call_handler from the libcfs layer.
Signed-off-by: James Simmons
---
...
Using proc_call_handler as a function name is way too generic.
Rename to lprocfs_call_handler to avoid possible collisions.
Signed-off-by: James Simmons
---
drivers/staging/lustre/lustre/libcfs/module.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/dri
A couple of sparse warnings.
On Fri, Feb 19, 2016 at 11:15:31PM +0200, Roger Quadros wrote:
> Move NAND specific device tree parsing to NAND driver.
>
> The NAND controller node must have a compatible id, register space
> resource and interrupt resource.
>
> Signed-off-by: Roger Quadros
> ---
>
From: Sebastien Buisson
Fix 'data race condition' defects found by Coverity version 6.5.0:
Data race condition (MISSING_LOCK)
Accessing variable without holding lock. Elsewhere,
this variable is accessed with lock held.
Signed-off-by: Sebastien Buisson
Intel-bug-id: https://jira.hpdd.intel.com/
From: James Nunez
Several error messages are missing newline characters
at the end of the message. Newlines are added where
necessary and other minor corrections; no punctuation
at the end of an error message, add a return code to
the end of error messages, device name at the beginning,
etc.
The
From: Frank Zago
One of the __user was missed in being applied to upstream
client. This is broken out of patch 11819.
Signed-off-by: Frank Zago
Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-5396
Reviewed-on: http://review.whamcloud.com/11819
Reviewed-by: James Simmons
Reviewed-by: Dmitry
The ln_refcount test was changed into an assert.
Signed-off-by: James Simmons
---
drivers/staging/lustre/lnet/lnet/api-ni.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/lustre/lnet/lnet/api-ni.c
b/drivers/staging/lustre/lnet/lnet/api-ni.c
index 739
From: Liang Zhen
Incoming lnet message can be delayed for seconds if it can match
any of LNet Delay Rules.
User can add/remove/list Delay Rule by lctl commands:
- lctl net_delay_add
Add a new Delay Rule to LNet, options
<-s | --source SRC_NID>
<-d | --dest DST_NID>
<<-r | --rate RATE_NUM
From: Sebastien Buisson
Fix 'NULL pointer dereference' defects found by Coverity version
6.5.3:
Dereference after null check (FORWARD_NULL)
For instance, Passing null pointer to a function which dereferences
it.
Dereference before null check (REVERSE_INULL)
Null-checking variable suggests that it
From: Sebastien Buisson
Fix 'data race condition' defects found by Coverity version 6.5.0:
Data race condition (MISSING_LOCK)
Accessing variable without holding lock. Elsewhere,
this variable is accessed with lock held.
Signed-off-by: Sebastien Buisson
Intel-bug-id: https://jira.hpdd.intel.com/
On Sat, 2016-03-05 at 01:34 +0100, Arnd Bergmann wrote:
> On Friday 04 March 2016 16:25:07 Joe Perches wrote:
> > > diff --git a/drivers/target/iscsi/cxgbit/cxgbit_ddp.c
> > > b/drivers/target/iscsi/cxgbit/cxgbit_ddp.c
[]
> > > @@ -179,7 +179,7 @@ cxgbit_dump_sgl(const char *cap, struct scatterlis
On 3/4/2016 10:23 AM, Douglas Anderson wrote:
> From testing and trying to make sense of the documentation, it appears
> that a 10 ms delay is needed after resetting the core to make sure that
> everything is stable and consistent. Let's add it.
>
> In my testing (on rk3288) this allows us to rev
On Fri, Mar 4, 2016 at 6:48 PM, Toshi Kani wrote:
> On Thu, 2016-03-03 at 13:53 -0800, Dan Williams wrote:
>> On a platform where 'Persistent Memory' and 'System RAM' are mixed
>> within a given sparsemem section, trim the namespace and notify about the
>> sub-optimal alignment.
>>
>> Cc: Toshi Ka
On Fri, Mar 4, 2016 at 1:32 AM, Diego Viola wrote:
> On Thu, Mar 3, 2016 at 6:19 PM, Diego Viola wrote:
>> On Thu, Mar 3, 2016 at 6:14 PM, Diego Viola wrote:
>>> On Thu, Mar 3, 2016 at 2:55 AM, Diego Viola wrote:
On Thu, Mar 3, 2016 at 12:19 AM, Diego Viola wrote:
> On Wed, Mar 2, 201
On Fri, Feb 26, 2016 at 01:57:24AM +0100, Boris Brezillon wrote:
> Use the mtd_set_ecclayout() helper instead of directly assigning the
> mtd->ecclayout field.
>
> Signed-off-by: Boris Brezillon
> ---
> drivers/mtd/nand/nand_base.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> dif
Sorry, another small thing I noticed.
On Fri, Feb 19, 2016 at 11:15:31PM +0200, Roger Quadros wrote:
> Move NAND specific device tree parsing to NAND driver.
>
> The NAND controller node must have a compatible id, register space
> resource and interrupt resource.
>
> Signed-off-by: Roger Quadros
Phy is mandatory requirement for arasan,sdhci-5.1, so we introduce
generic phy support for sdhci-of-arasan.
This version is rebased on Ulf's next to make it applied cleanly.
Also, we fix some preexisting problems of err handling suggested by Adrian.
Shawn Lin (2):
Documentation: bindings: add
This patch adds Generic PHY access for sdhci-of-arasan. Driver
can get PHY handler from dt-binding, and power-on/init the PHY.
Currently, it's just mandatory for arasan,sdhci-5.1.
Signed-off-by: Shawn Lin
Serise-changes: 6
- rebase on Ulf's next
- fix some preexisting problems of err handling su
This patch adds phys and phy-names for sdhci-of-arasan as required
properties for arasan,sdhci-5.1, and details the example as well.
Signed-off-by: Shawn Lin
Acked-by: Rob Herring
---
Changes in v6:
- add Rob's Acked-by tag
Changes in v2:
- Keep phy as a mandatory requirement for arasan,sdhci
On Mon, Feb 29, 2016 at 06:25:12PM +0200, Roger Quadros wrote:
> On 19/02/16 23:15, Roger Quadros wrote:
> > Hi,
> >
> > @Tony
> > Patches 15 and 24 are new and will need your review.
> > I've modified patch 22 to include the new am335x boards introduced since
> > v4.4.
> >
> > Patches are based
This patchset allows the degeneration of per-cpu counters back to
global counters when:
1) The number of CPUs in the system is large, hence a high cost for
calling percpu_counter_sum().
2) The initial count value is small so that it has a high chance of
excessive percpu_counter_sum() cal
Per-cpu counters are used in quite a number of places within
the kernel. On large system with a lot of CPUs, however, doing a
percpu_counter_sum() can be very expensive as nr_cpu cachelines will
need to be read. In __percpu_counter_compare(), the chance of calling
percpu_counter_sum() also increas
Small XFS filesystems on systems with large number of CPUs can incur a
significant overhead due to excessive calls to the percpu_counter_sum()
function which needs to walk through a large number of different
cachelines.
This patch uses the newly added percpu_counter_set_limit() API to
potentially
On 03/04/2016 10:58 PM, Namhyung Kim wrote:
Hi Taeung,
On Fri, Mar 04, 2016 at 09:45:44PM +0900, Taeung Song wrote:
Hi, Namhyung and all
(I'm modifying this patch to be tidy)
I have a mere question about name of a variable for
current config list that contains section list which has key-valu
On Mar 4, 2016, at 9:09 PM, James Simmons wrote:
> From: Frank Zago
>
> One of the __user was missed in being applied to upstream
> client. This is broken out of patch 11819.
It was not, the bug was fixed in another way.
> Signed-off-by: Frank Zago
> Intel-bug-id: https://jira.hpdd.intel.com
On Fri, Mar 4, 2016 at 4:56 PM, Darrick J. Wong wrote:
>
> + bs_mask = (bdev_logical_block_size(bdev) >> 9) - 1;
> + if ((sector & bs_mask) || ((sector + nr_sects) & bs_mask))
> + return -EINVAL;
This test may _work_, but it's kind of crazily overly complicated.
The san
On Fri, Mar 4, 2016 at 4:56 PM, Darrick J. Wong wrote:
> + /* Only punch if the device can do zeroing discard. */
> + if ((mode & FALLOC_FL_PUNCH_HOLE) &&
> + (!blk_queue_discard(q) || !q->limits.discard_zeroes_data))
> + return -EOPNOTSUPP;
I'm ok with this, b
On Fri, Feb 12, 2016 at 11:29:04PM +0100, Robert Jarzmik wrote:
> When the driver is initialized in a pure device-tree platform, the
> driver's probe fails allocating the dma channel :
> [ 525.624435] pxa3xx-nand 4310.nand: no resource defined for data DMA
> [ 525.632088] pxa3xx-nand 4310
On Fri, Mar 4, 2016 at 4:56 PM, Darrick J. Wong wrote:
> +
> + /* We can't change the bdev size from here */
> + if (!(mode & FALLOC_FL_KEEP_SIZE))
> + return -EOPNOTSUPP;
Oh, and this I think is wrong.
The thing is, FALLOC_FL_KEEP_SIZE is only supposed to matter if the
On Fri, Mar 4, 2016 at 4:55 PM, Darrick J. Wong wrote:
>
> This is a redesign of the patch series that fixes various interface
> problems with the existing "zero out this part of a block device"
> code. BLKZEROOUT2 is gone.
I replied to two of the patches with small nits, but on the whole I
like
Hi Arnd,
[auto build test WARNING on staging/staging-testing]
[also build test WARNING on v4.5-rc6 next-20160304]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Arnd-Bergmann/isdn-icn-remove
On Tue, Sep 22, 2015 at 04:34:25PM +0200, Christophe Leroy wrote:
> @@ -137,6 +130,45 @@ static inline __wsum csum_add(__wsum csum, __wsum addend)
> #endif
> }
>
> +/*
> + * This is a version of ip_compute_csum() optimized for IP headers,
> + * which always checksum on 4 octet boundaries. ihl
On Fri, Mar 04, 2016 at 02:05:56PM +0530, Jayachandran Chandrashekaran Nair
wrote:
> On Fri, Mar 4, 2016 at 4:21 AM, Bjorn Helgaas wrote:
> > Hi Tomasz, Jayachandran, et al,
> >
> > On Tue, Feb 16, 2016 at 02:53:31PM +0100, Tomasz Nowicki wrote:
> >> From: Jayachandran C
> >>
> >> Move pci_mmcfg
On Tue, Mar 01, 2016 at 03:09:37PM +0800, Zhao Qiang wrote:
> Add IC, SI and SIRAM document of QE to
> Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2
> - Add interrupt-controller in Required properties
> - delete addres
On Tue, Mar 01, 2016 at 03:09:38PM +0800, Zhao Qiang wrote:
> Add ucc hdlc document to
> Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2
> - use ucc-hdlc instead of ucc_hdlc
> - add more information to properties.
>
On Tue, Mar 01, 2016 at 12:42:47PM -0500, Yendapally Reddy Dhananjaya Reddy
wrote:
> Add a binding for Broadcom iproc pwm controller
>
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy
>
> ---
> Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt | 2 +-
> 1 file changed, 1 insertion(+),
On Tue, Mar 01, 2016 at 03:09:40PM +0800, Zhao Qiang wrote:
> cpm_qe is supported on both powerpc and arm.
> and the QE code has been moved from arch/powerpc into
> drivers/soc/fsl, so move cpm_qe binding from powerpc/fsl
> to soc/fsl
>
> Signed-off-by: Zhao Qiang
> ---
I already acked this. In
On Tue, Mar 01, 2016 at 09:29:14PM +0800, HS Liao wrote:
> This adds documentation for the MediaTek Global Command Engine (GCE) unit
> found in MT8173 SoCs.
>
> Signed-off-by: HS Liao
> ---
> .../devicetree/bindings/soc/mediatek/gce.txt | 34
>
> 1 file changed, 34
On Tue, Mar 01, 2016 at 10:38:18AM -0600, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Add the device tree binding string needed to support the Altera L2
> cache on the Arria10 chip.
>
> Signed-off-by: Thor Thayer
> ---
> .../bindings/arm/altera/socfpga-eccmgr.txt |
On Tue, Mar 01, 2016 at 03:09:39PM +0800, Zhao Qiang wrote:
> Add uqe_serial document to
> Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2
> - modify tx/rx-clock-name specification
> Changes for v2
> - NA
>
>
On Wed, Mar 02, 2016 at 04:24:45PM +0530, Laxman Dewangan wrote:
> Add common DT property for regulator node to support of
> active discharge enable/disable configuration of regulator.
>
> Signed-off-by: Laxman Dewangan
> ---
> Changes from V1:
> None
>
> Documentation/devicetree/bindings/regu
On Wed, Mar 02, 2016 at 03:34:58AM +0100, Andreas Färber wrote:
> Use "amlogic,meson-gxbb" compatible string.
>
> Signed-off-by: Andreas Färber
> ---
> v1 -> v2: unchanged
>
> Documentation/devicetree/bindings/arm/amlogic.txt | 4
> 1 file changed, 4 insertions(+)
Acked-by: Rob Herring
On Wed, Mar 02, 2016 at 12:25:35AM +0300, Sergei Ianovich wrote:
> The patch adds support for 3 additional LP-8x4x built-in serial
> ports.
>
> The device can also host up to 8 extension cards with 4 serial ports
> on each card for a total of 35 ports. However, I don't have
> the hardware to test
On Wed, Mar 02, 2016 at 03:35:00AM +0100, Andreas Färber wrote:
> Use "tronsmart,vega-s95" as well as
> "tronsmart,vega-s95-pro",
> "tronsmart,vega-s95-meta" and
> "tronsmart,vega-s95-telos" compatible strings.
>
> Signed-off-by: Andreas Färber
> ---
> v1 -> v2: unchanged
>
> Docu
On Thu, Mar 03, 2016 at 09:38:38AM +0900, Simon Horman wrote:
> In the case of Renesas R-Car hardware we know that there are generations of
> SoCs, e.g. Gen 2 and Gen 3. But beyond that its not clear what the
> relationship between IP blocks might be. For example, I believe that
> r8a7790 is older
On Wed, Mar 02, 2016 at 10:01:33PM -0500, David Rivshin (Allworx) wrote:
> From: David Rivshin
>
> This adds a binding description for the is31fl3236/35/18/16 I2C LED
> controllers.
>
> Signed-off-by: David Rivshin
> ---
>
> Rob,
> I went with the 1-based 'reg' property here. I inferred that
On Thu, Mar 03, 2016 at 09:33:37AM +0800, Guodong Xu wrote:
> Add resets property to synopsys-dw-mshc bindings. It is intended to
> represent the hardware reset signal present internally in some host
> controller IC designs.
>
> See Documentation/devicetree/bindings/reset/reset.txt for details.
>
On Thu, Mar 03, 2016 at 09:38:37AM +0900, Simon Horman wrote:
> In the case of Renesas R-Car hardware we know that there are generations of
> SoCs, e.g. Gen 2 and Gen 3. But beyond that its not clear what the
> relationship between IP blocks might be. For example, I believe that
> r8a7790 is older
On Wed, Mar 02, 2016 at 10:01:32PM -0500, David Rivshin (Allworx) wrote:
> From: David Rivshin
>
> ISSI is the stock ticker Integrated Silicon Solutions Inc.
> Company website: http://www.issi.com
>
> Signed-off-by: David Rivshin
> ---
>
> Changes from RFC:
> none
>
> Documentation/devicetr
On Thu, Mar 03, 2016 at 04:02:15PM +0100, Philipp Zabel wrote:
> Am Donnerstag, den 03.03.2016, 12:39 +0100 schrieb Neil Armstrong:
> > Add PLX Technology vendor prefix.
> >
> > Signed-off-by: Neil Armstrong
> > ---
> > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> > 1 file chan
On Fri, Mar 04, 2016 at 03:57:53PM +0530, Laxman Dewangan wrote:
> The driver MAX8973 supports the driver for Maxim MAX77621.
> MAX77621 supports the junction temp warning at 120 degC and
> 140 degC which is configurable. It generates alert signal when
> junction temperature crosses these threshold
On Fri, Mar 04, 2016 at 06:31:54PM +0800, Sugar Zhang wrote:
> this patch add compatible for rk3366/rk3368/rk3399 spdif,
> these three spdifs share the same type.
>
> Signed-off-by: Sugar Zhang
> ---
>
> Documentation/devicetree/bindings/sound/rockchip-spdif.txt | 8 ++--
> sound/soc/rockc
2016-03-04 20:02 GMT+09:00 Sylwester Nawrocki :
> On 03/04/2016 02:02 AM, Krzysztof Kozlowski wrote:
>> The MFD_SYSCON depends on HAS_IOMEM so when selecting
>> it avoid unmet direct dependencies.
>
>> diff --git a/drivers/media/platform/exynos4-is/Kconfig
>> b/drivers/media/platform/exynos4-is/Kco
On Thu, Mar 03, 2016 at 06:41:41AM -0500, Yendapally Reddy Dhananjaya Reddy
wrote:
> Device tree binding documentation for Broadcom NS2 IOMUX
>
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy
>
> ---
> .../bindings/pinctrl/brcm,ns2-pinmux.txt | 102
> +
> 1 fi
On Wed, Mar 02, 2016 at 10:01:35PM -0500, David Rivshin (Allworx) wrote:
> From: David Rivshin
>
> Si-En Technology was acquired by ISSI in 2011, and it appears that
> the IS31FL3218/IS31FL3216 are just rebranded SN3218/SN3216 devices.
> As the IS31FL32XX driver already handles the *3218 devices,
On Thu, Mar 03, 2016 at 09:02:38PM +0100, John Crispin wrote:
> This adds the binding documentation for the MediaTek Ethernet
> controller.
>
> Signed-off-by: John Crispin
> Cc: devicet...@vger.kernel.org
> ---
> .../devicetree/bindings/net/mediatek-net.txt | 77
>
>
On Thu, Mar 03, 2016 at 12:40:09PM +0100, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring
On Thu, Mar 03, 2016 at 05:39:14PM +0300, Alexey Brodkin wrote:
> This add DT bindings documentation for ARC PGU display controller.
>
> Signed-off-by: Alexey Brodkin
> Cc: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian Campbell
> Cc: Kumar Gala
> Cc: devicet...@vger.kernel.org
>
On Fri, Mar 04, 2016 at 07:14:41PM +0530, Purna Chandra Mandal wrote:
> Signed-off-by: Purna Chandra Mandal
>
> ---
>
> Changes in v2:
> - fix indentation
> - add space after comma
> - moved 'cs-gpios' section under 'required' properties.
>
> .../bindings/spi/microchip,spi-pic32.txt
On Fri, Mar 04, 2016 at 04:58:04PM +0100, Alexandre TORGUE wrote:
> Signed-off-by: Alexandre TORGUE
>
> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
> b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
> new file mode 100644
> index 000..fd3566f
> --- /dev/null
> +
On Fri, Mar 04, 2016 at 05:19:33PM +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> Extend the binding to cover the set of feature found in Tegra210.
>
> Signed-off-by: Thierry Reding
> ---
> .../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 327
> +
> 1 file cha
On Fri, Mar 04, 2016 at 05:19:31PM +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a
> set of lanes that are used for PCIe, SATA and USB.
>
> Signed-off-by: Thierry Reding
> ---
> Changes in v10:
> - clarify that the
On Fri, Mar 04, 2016 at 05:19:32PM +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> This is an old version of the binding that isn't flexible enough to
> describe all aspects of the XUSB pad controller. Specifically with the
> addition of XUSB support (for SuperSpeed USB) the existing bind
On Thu, Feb 25, 2016 at 05:25:07PM -0600, Alan Tull wrote:
> Add bindings documentation for Altera SOCFPGA bridges:
> * fpga2sdram
> * fpga2hps
> * hps2fpga
> * lwhps2fpga
>
> Signed-off-by: Alan Tull
> Signed-off-by: Matthew Gerlach
> Signed-off-by: Dinh Nguyen
> ---
> v2: separate into 2
2016-03-05 5:20 GMT+09:00 Javier Martinez Canillas :
> Hello,
>
> This series have two trivial fixes for issues that I noticed while
> reading as a reference the driver's functions that parse the graph
> port and endpoints nodes.
>
> It was only compile tested because I don't have access to a Exyno
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-
> ow...@vger.kernel.org] On Behalf Of Luis R. Rodriguez
> Sent: Friday, March 04, 2016 4:45 PM
> Subject: [PATCH v2] x86: PAT: Documentation: rewrite "MTRR effects on
> PAT / non-PAT systems"
...
> +MMIO a
Hi,
On Wednesday 02 March 2016 11:23 PM, Rob Herring wrote:
> On Thu, Feb 25, 2016 at 02:03:37PM +0530, Pankaj Dubey wrote:
>> This patch adds exynos-srom binding information for SROM Controller
>> driver on Exynos SoCs.
>>
>> CC: Rob Herring
>> CC: Mark Rutland
>> CC: Ian Campbell
>> CC: devic
Hi,
On Wednesday 02 March 2016 11:27 PM, Rob Herring wrote:
> On Thu, Feb 25, 2016 at 02:03:41PM +0530, Pankaj Dubey wrote:
>> From: Pavel Fedin
>>
>> Add documentation for new subnode properties, allowing bank configuration.
>> Based on u-boot implementation, but heavily reworked.
>>
>> Also, fi
On Fri, 4 Mar 2016 22:14:27 +0100 (CET)
Stefan Wahren wrote:
> Hi David,
>
> > "David Rivshin (Allworx)" hat am 3. März 2016
> > um
> > 04:01 geschrieben:
> >
> >
> > From: David Rivshin
> >
> > Si-En Technology was acquired by ISSI in 2011, and it appears that
> > the IS31FL3218/IS31FL3216 a
Kernel style prefers "unsigned int " over "unsigned "
and "signed int " over "signed ".
Emit a warning for these simple signed/unsigned declarations.
Fix it too if desired.
Signed-off-by: Joe Perches
---
scripts/checkpatch.pl | 20
1 file changed, 20 insertions(+)
diff --
On Tue, Sep 22, 2015 at 04:34:36PM +0200, Christophe Leroy wrote:
> +/*
> + * computes the checksum of a memory block at buff, length len,
> + * and adds in "sum" (32-bit)
> + *
> + * returns a 32-bit number suitable for feeding into itself
> + * or csum_tcpudp_magic
> + *
> + * this function must
On Fri, 4 Mar 2016 22:39:06 +0100
Jacek Anaszewski wrote:
> On 03/04/2016 08:02 PM, David Rivshin (Allworx) wrote:
> > On Fri, 04 Mar 2016 17:01:52 +0100
> > Jacek Anaszewski wrote:
> >
> >> On 03/04/2016 04:05 PM, David Rivshin (Allworx) wrote:
> >>> On Fri, 04 Mar 2016 08:54:02 +0100
> >>>
On Thu, 03 Mar 2016 15:51:36 +0100
Jacek Anaszewski wrote:
> Hi David,
>
> I'll wait for Tested-by from Stefan before applying this patch.
> If Stefan will have managed to test your driver with his hardware
> by the end of this cycle, it will suffice for this patch to contain
> only leds-is31fl3
It will always be passed if the soc is tested the loopback cases. This
patch will fix this bug.
Signed-off-by: Kejian Yan
---
change log:
PATCH v2:
- This patch fixes the comments provided by Andy Shevchenko
PATCH v1:
- first submit
Link: https://lkml.org/lkml/2016/3/3/266
---
drivers/net/
On Fri, 04 Mar 2016 16:38:01 +0100
Jacek Anaszewski wrote:
> On 03/04/2016 03:27 PM, David Rivshin (Allworx) wrote:
> > (Stefan, sorry for the duplicate, I just realized that I originally
> > replied only to you by accident).
> >
> > On Thu, 3 Mar 2016 19:13:03 +0100 (CET)
> > Stefan Wahren wrot
Hi
On Wednesday 02 March 2016 11:23 PM, Rob Herring wrote:
> On Thu, Feb 25, 2016 at 02:03:37PM +0530, Pankaj Dubey wrote:
>> This patch adds exynos-srom binding information for SROM Controller
>> driver on Exynos SoCs.
>>
>> CC: Rob Herring
>> CC: Mark Rutland
>> CC: Ian Campbell
>> CC: device
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