On Fri, Mar 04, 2016 at 05:19:31PM +0100, Thierry Reding wrote: > From: Thierry Reding <[email protected]> > > The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a > set of lanes that are used for PCIe, SATA and USB. > > Signed-off-by: Thierry Reding <[email protected]> > --- > Changes in v10: > - clarify that the hardware documentation means something different when > referring to a "port" (intra-SoC connectivity) > > Changes in v9: > - rename UTMI -> USB2 to match hardware documentation > - reword according to suggestions by Stephen Warren > - make Tegra132 compatible string list consistent > - remove mailbox support > > .../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 376 > +++++++++++++++++++++ > .../pinctrl/nvidia,tegra124-xusb-padctl.txt | 5 + > 2 files changed, 381 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
Without really understanding the h/w here, looks okay to me. Acked-by: Rob Herring <[email protected]> > +SoC include: > + > + padctl@0,7009f000 { Drop the comma. Commas should only be used if there are distinct fields. If I get my dtc patch done, these are going to start warning, so you might want to go fix dts files (assuming that's where this is coming from). Rob
