On 10/29/2015 02:17 AM, Alexander Yarygin wrote:
Hemant Kumar writes:
Hi David,
On 10/07/2015 09:41 PM, David Ahern wrote:
On 10/6/15 8:25 PM, Hemant Kumar wrote:
@@ -358,7 +357,12 @@ static bool handle_end_event(struct
perf_kvm_stat *kvm,
time_diff = sample->time - time_begin;
From: "Steven Rostedt (Red Hat)"
My tests found that if a task is running but not filtered when set_event_pid
is modified, then it can still be traced.
Call on_each_cpu() to check if the current running task should be filtered
and update the per cpu flags of tr->data appropriately.
Signed-off-b
From: "Steven Rostedt (Red Hat)"
Create a tracing directory called set_event_pid, which currently has no
function, but will be used to filter all events for the tracing instance or
the pids that are added to the file.
The reason no functionality is added with this commit is that this commit
focu
From: "Steven Rostedt (Red Hat)"
In order to guarantee that a probe will be called before other probes that
are attached to a tracepoint, there needs to be a mechanism to provide
priority of one probe over the others.
Adding a prio field to the struct tracepoint_func, which lets the probes be
so
From: "Steven Rostedt (Red Hat)"
p_start() and p_stop() are seq_file functions that match. Teach sparse to
know that rcu_read_lock_sched() that is taken by p_start() is released by
p_stop.
Reported-by: kbuild test robot
Signed-off-by: Steven Rostedt
---
kernel/trace/trace_events.c | 2 ++
1 f
From: "Steven Rostedt (Red Hat)"
Add the necessary hooks to use the pids loaded in set_event_pid to filter
all the events enabled in the tracing instance that match the pids listed.
Two probes are added to both sched_switch and sched_wakeup tracepoints to be
called before other probes are called
Allowing for fork and exit to modify this list will have to wait til
4.5, as that code is much more complex and needs a release cycle to
go in. I at least want to have the pid file added for trace-cmd to
use (and modify itself). The static updates are not that complex.
And 4.4 is a LTS kernel (wink
On Thu, Oct 29, 2015 at 5:50 AM, Jeff Moyer wrote:
> Dan Williams writes:
>
>> If an application wants exclusive access to all of the persistent memory
>> provided by an NVDIMM namespace it can use this raw-block-dax facility
>> to forgo establishing a filesystem. This capability is targeted
>>
This series patchs are working for RK3368 on Rockchip platform.
@Heiko,
The PATCH [5/6] is working based on big/littel cluster cpufreq
added. Anyway, the PATCH [5/6] also work for next kernel.
@Eduardo,
This patchset are based on linus master branch.
Note: Need add the following thermal p
This patchset attempts to new compatible for thermal founding
on RK3368 SoCs.
Signed-off-by: Caesar Wang
---
Changes in v1:
- %s/thermal/rockchip-thermal in subject.
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --
The current driver is default to register the two thermal sensors
in probe since some SoCs maybe only have one sensor for thermal.
In some cases, the channel 0 is not always the cpu or gpu sensor.
So add the channel can be configured for sensors.
Signed-off-by: Caesar Wang
---
Changes in v1:
-
This patchset add the thermal for RK3368 dts,
Since the two CPU clusters, with four CPU core for each cluster,
One cluster is optimized for high-performance(big cluster) and the othe
is optimized for low power(little cluster).
This patch adds the second order for thermal throttle, and the critical
This patch add the thermal needed info on RK3368.
Meanwhile, support the trips to throttle for thermal.
Signed-off-by: Caesar Wang
---
Changes in v1:
- support the opt gpio pinctrl state
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 36
1 file changed, 36 inserti
The RK3368 SoCs support to 2 channel TS-ADC, the temperature criteria
of each channel can be configurable.
The system has two Temperature Sensors, channel 0 is for CPU,
and channel 1 is for GPU.
Signed-off-by: Caesar Wang
---
Changes in v1:
- As Dmitry comment, make the conversion table in as
This patch enable the TS-ADC.
When a thermal temperature is invoked use the CRU to reset the chip
on R88 board. TSHUT is low active on this board.
Signed-off-by: Caesar Wang
---
Changes in v1: None
arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 6 ++
1 file changed, 6 insertions(+)
diff
streamzap uses 'struct timeval' to store the start time of a signal for
gap tracking. struct timeval uses a 32-bit seconds representation which
will overflow in year 2038 and beyond. Replace struct timeval with ktime_t
which uses a 64-bit seconds representation and is 2038 safe. This patch
uses kt
'struct timeval' uses 32-bit representation for seconds which will
overflow in year 2038 and beyond. mISDN/clock.c needs to compute and
store elapsed time in intervals of 125 microseconds. This patch replaces
the usage of 'struct timeval' with 64-bit ktime_t which is y2038 safe.
The patch also repl
On Wed, Oct 28, 2015 at 09:51:26AM +0100, Johan Hovold wrote:
> On Tue, Oct 27, 2015 at 04:53:34PM -0500, Konstantin Shkolnyy wrote:
> > cp2108 GET_LINE_CTL returns the 16-bit value with the 2 bytes swapped.
> > However, SET_LINE_CTL functions properly. When the driver tries to modify
> > the regis
replace GFP_KERNEL with GFP_ATOMIC while spinlock is held,
as code while holding a spinlock should be atomic.
GFP_KERNEL may sleep and can cause deadlock,
where as GFP_ATOMIC may fail but certainly avoids deadlock
Signed-off-by: Saurabh Sengar
---
arch/um/drivers/net_kern.c | 31
Hi Robert,
On Thu, 29 Oct 2015 07:32:33 +0100
Robert Jarzmik wrote:
> Marek Vasut writes:
>
> >> Isn't there the case of a single NAND controller with 2 identical chips,
> >> each a 8 bit NAND chip, and the controller aggregating them to offer the
> >> OS a single 16-bit NAND chip ?
Honestly,
Otherwise get_maintainer.pl will fall back to git history and CC
more people than needed.
Signed-off-by: Wolfram Sang
Acked-by: Lee Jones
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2f23aab10398bb..c3f01dc36b26b4 100644
--- a/MAINTAINERS
+
Hi Michael,
[auto build test ERROR on input/next -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/Michael-Welling/Input-tsc2005-Add-support-for-tsc2004/20151029-081504
config: x86_64-randconf
replace GFP_KERNEL with GFP_ATOMIC while spinlock is held,
as code while holding a spinlock should be atomic.
GFP_KERNEL may sleep and can cause deadlock,
where as GFP_ATOMIC may fail but certainly avoids deadlock
Signed-off-by: Saurabh Sengar
---
v2: correcting the subject
arch/um/drivers/net_
Hi Nicolas,
On Wed, 2015-10-28 at 19:32 -0400, Nicolas Pitre wrote:
> On Thu, 29 Oct 2015, Alexey Brodkin wrote:
>
> > Fortunately we already have much better __div64_32() for 32-bit ARM.
> > There in case of division by constant preprocessor calculates so-called
> > "magic number" which is later
On 10/29/2015 08:41 AM, Dongsheng Yang wrote:
On 10/28/2015 08:30 AM, Matias Bjørling wrote:
The implementation for Open-Channel SSDs is divided into media
[...]
+lun->reserved_blocks = 2; /* for GC only */
+lun->vlun.id = i;
+lun->vlun.lun_id = i % dev->luns_per_chnl;
On 2015/10/27 22:03, Mark Rutland wrote:
On Tue, Oct 27, 2015 at 09:21:13PM +0800, Yang Yingliang wrote:
In multi-core system, if the clock is not sync perfectly, it
will make cycle_last that recorded by CPU-A is a little more
than cycle_now that read by CPU-B.
If that is happening, that soun
Hi Tina,
[auto build test ERROR on asm-generic/master -- if it's inappropriate base,
please suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/Tina-Ruchandani/isdn-Use-ktime_t-instead-of-struct-timeval/20151029-151936
config: x86_64-randc
Hello Krzysztof,
On 10/29/2015 11:24 AM, Krzysztof Kozlowski wrote:
On 29.10.2015 13:58, Alim Akhtar wrote:
RTC found in s2mps15 is almost same as one found on s2mps14/13
with few differences in RTC_UPDATE register fields, like
bit fields are changed for WUDR and AUDR.
This patch add required c
Hi Gang,
thanks for pointing to explanation of the feature.
What I am curious about is ... what were the real cases that you came
across prompted this change and how this change would help in that case.
Thanks,
--Srini
On 10/28/2015 09:44 PM, Gang He wrote:
Hello Srini,
There is a doc abo
On 10/29/2015 11:27 AM, Krzysztof Kozlowski wrote:
On 29.10.2015 13:58, Alim Akhtar wrote:
From: Thomas Abraham
Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device
is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators.
Cc: devicet...@vger.kernel.org
Any CFLAGS or LDFLAGS set by the user need to be passed to the feature build
command. This many include for example -I or -L to point to libraries and
include files in custom paths.
In most of the test-*.bin rules in build/feature/Makefile, we use the BUILD
macro which always sends in CFLAGS and
Even if --symfs is used to point to the debug binaries, we send in the
non-debug filenames to libunwind, which leads to libunwind not finding
the debug frame. Fix this by preferring the file in --symfs, if it is
available.
Signed-off-by: Rabin Vincent
---
v2: fall back to ->name if ->symsrc_file
It's easy to cross-compile a minimal perf binary without any external
libraries (other than a C library of course). But many useful features
depend on external libraries, so to get them one needs to either
cross-compile a bunch of libraries manually and send in the correct
paths or integrate the p
On Fri, Oct 16, 2015 at 09:04:58AM -0700, Tim Chen wrote:
> On Wed, 2015-10-14 at 21:15 +0200, LABBE Corentin wrote:
> > The sha x86 crypto code use two define for the same thing:
> > NUM_SHA1_DIGEST_WORDS and SHA1_DIGEST_LENGTH
> > Replace them by SHA1_DIGEST_SIZE/4
>
> Thanks. Acked-by: Tim Che
On 10/27/2015 05:04 PM, Linus Walleij wrote:
> On Fri, Oct 23, 2015 at 6:25 PM, Soren Brinkmann
> wrote:
>
>> GPIO can be used as interrupt-controller. Add the missing properties to
>> the GPIO node.
>>
>> Signed-off-by: Soren Brinkmann
>
> Acked-by: Linus Walleij
Applied to zynq/dt.
Thanks,
On Thu, Oct 29, 2015 at 02:25:24AM +0200, Kirill A. Shutemov wrote:
> On Thu, Oct 22, 2015 at 06:00:51PM +0900, Minchan Kim wrote:
> > On Thu, Oct 22, 2015 at 10:21:36AM +0900, Minchan Kim wrote:
> > > Hello Hugh,
> > >
> > > On Wed, Oct 21, 2015 at 05:59:59PM -0700, Hugh Dickins wrote:
> > > > On
Hi Linus, please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm libnvdimm-fixes
...to receive a small fixlet for 4.3.
The new memremap() api introduced in the 4.3 cycle to unify/replace
ioremap_cache() and ioremap_wt() is mishandling the highmem case. This
patch has re
Dne 29.10.2015 v 07:34 Peter Chen napsal(a):
> On Wed, Oct 28, 2015 at 02:25:41PM +0100, Michal Marek wrote:
>> From: Michal Marek
>>
>> This allows to write
>>
>> drm-$(CONFIG_AGP) += drm_agpsupport.o
>>
>> without having to handle CONFIG_AGP=y vs. CONFIG_AGP=m. Only support
>> this syntax for
On Thu, 29 Oct 2015, Alim Akhtar wrote:
> From: Thomas Abraham
>
> Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
> PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz
> clock outputs and battery charger. This patch adds initial support for
> LDO
On Thu, 29 Oct 2015, Alim Akhtar wrote:
> From: Thomas Abraham
>
> The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
> 27 LDO and 10 Buck regulators and allows programming these regulators via a
> I2C interface. This patch adds initial support for LDO/Buck regulators o
On Thu, Oct 29, 2015 at 09:05:55AM +0100, Michal Marek wrote:
> Dne 29.10.2015 v 07:34 Peter Chen napsal(a):
> > On Wed, Oct 28, 2015 at 02:25:41PM +0100, Michal Marek wrote:
> >> From: Michal Marek
> >>
> >> This allows to write
> >>
> >> drm-$(CONFIG_AGP) += drm_agpsupport.o
> >>
> >> without
On Thu, Oct 15, 2015 at 08:54:59AM +0200, LABBE Corentin wrote:
> Building linux with W=1 on arm give me this warning;
> In file included from ../include/linux/nodemask.h:92:0,
> from ../include/linux/mmzone.h:16,
> from ../include/linux/gfp.h:5,
>
On 29.10.2015 17:08, Lee Jones wrote:
> On Thu, 29 Oct 2015, Alim Akhtar wrote:
>
>> From: Thomas Abraham
>>
>> The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
>> 27 LDO and 10 Buck regulators and allows programming these regulators via a
>> I2C interface. This patch
cros_ec_cmd_xfer_spi and cros_ec_pkt_xfer_spi generally work like
this:
- Pull CS down (active), wait a bit, then send a command
- Wait for response (multiple requests)
- Wait a while, pull CS up (inactive)
These operations, individually, lock the SPI bus, but there is
nothing preventing the SP
Signed-off-by: Jens Wiklander
---
Documentation/00-INDEX | 2 +
Documentation/tee.txt | 117 +
MAINTAINERS| 1 +
3 files changed, 120 insertions(+)
create mode 100644 Documentation/tee.txt
diff --git a/Documentation/00-INDEX b/Doc
Hi,
This patch set introduces a generic TEE subsystem. The TEE subsystem will
contain drivers for various TEE implementations. A TEE (Trusted Execution
Environment) is a trusted OS running in some secure environment, for
example, TrustZone on ARM CPUs, or a separate secure co-processor etc.
Regar
This patch series adds the support for TI BQ24261 charger driver.
TI BQ24261 charger driver relies on extcon notifications to get the
charger cable type and based on that it will set the charging parameters.
Ramakrishna Pallala (2):
dt: power: Add support for BQ24261 charger
power: Add suppor
This patch adds the device tree documentation for TI BQ24261 charger.
Signed-off-by: Ramakrishna Pallala
Signed-off-by: Jennt TC
---
.../devicetree/bindings/power/bq24261.txt | 34
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bind
Introduces optee prefix and adds bindings for ARM TrustZone based OP-TEE
implementation.
Signed-off-by: Jens Wiklander
---
.../bindings/arm/firmware/optee,optee-tz.txt | 29 ++
.../devicetree/bindings/vendor-prefixes.txt| 1 +
2 files changed, 30 insertions(+)
Add new charger driver support for TI BQ24261 charger IC.
TI BQ24261 charger driver relies on extcon notifications to get the
charger cable type and based on that it will set the charging parameters.
Signed-off-by: Ramakrishna Pallala
Signed-off-by: Jennt TC
---
drivers/power/Kconfig
On Wed, Oct 28, 2015 at 04:11:41PM +0100, Linus Walleij wrote:
> On Tue, Oct 27, 2015 at 5:51 PM, Mika Westerberg
> wrote:
> > On Tue, Oct 27, 2015 at 05:42:23PM +0100, Linus Walleij wrote:
> >> On Tue, Oct 27, 2015 at 3:23 PM, Mika Westerberg
> >> wrote:
> >> > On Tue, Oct 27, 2015 at 11:06:58AM
Initial patch for generic TEE subsystem.
This subsystem provides:
* Registration/un-registration of TEE drivers.
* Shared memory between normal world and secure world.
* Ioctl interface for interaction with user space.
* Sysfs implementation_id of TEE driver
A TEE (Trusted Execution Environment) d
Adds a OP-TEE driver which also can be compiled as a loadable module.
* Targets ARM and ARM64
* Supports using reserved memory from OP-TEE as shared memory
* Probes OP-TEE version using SMCs
* Accepts requests on privileged and unprivileged device
* Uses OPTEE message protocol version 2 to communi
This patch adds the device tree documentation for TI BQ24261 charger.
Signed-off-by: Ramakrishna Pallala
Signed-off-by: Jenny TC
---
.../devicetree/bindings/power/bq24261.txt | 34
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bind
On Tue, Oct 06, 2015 at 06:23:53PM +0300, Kirill A. Shutemov wrote:
...
> diff --git a/mm/migrate.c b/mm/migrate.c
> index 0268013cce63..45fadab47c53 100644
> --- a/mm/migrate.c
> +++ b/mm/migrate.c
> @@ -165,7 +165,7 @@ static int remove_migration_pte(struct page *new, struct
> vm_area_struct *vm
From: Thierry Reding
Boot consoles are typically replaced by proper consoles during the boot
process. This can be problematic if the boot console data is part of the
init section that is reclaimed late during boot. If the proper console
does not register before this point in time, the boot consol
Add new charger driver support for TI BQ24261 charger IC.
TI BQ24261 charger driver relies on extcon notifications to get the
charger cable type and based on that it will set the charging parameters.
Signed-off-by: Ramakrishna Pallala
Signed-off-by: Jenny TC
---
drivers/power/Kconfig
Hello Srini,
The real cases are that we try to fix some independent issues without turning
the file system off-line (error=continue was introduced).
You know, the online file check feature is used for fixing some independent or
light meta-data block corruption, e.g. inode block, file extent bloc
This patch series adds the support for TI BQ24261 charger driver.
TI BQ24261 charger driver relies on extcon notifications to get the
charger cable type and based on that it will set the charging parameters.
Ramakrishna Pallala (2):
dt: power: Add support for BQ24261 charger
power: Add suppor
Switch to use a generic interface for issuing SMC/HVC based on ARM SMC
Calling Convention. Removes now the now unused psci-call.S.
Signed-off-by: Jens Wiklander
---
arch/arm/kernel/Makefile | 1 -
arch/arm/kernel/psci-call.S | 31 ---
arch/arm64/kernel/Makefil
Adds helpers to do SMC and HVC based on ARM SMC Calling Convention.
CONFIG_HAVE_SMCCC is enabled for architectures that may support
the SMC or HVC instruction. It's the responsibility of the caller
to know if the SMC instruction is supported by the platform.
Signed-off-by: Jens Wiklander
---
arc
Hi,
This series depends on the eDMA work I have done, which has been now applied:
https://lkml.org/lkml/2015/10/16/64
DRA7 family of chips have both sDMA and eDMA. Currently only sDMA can be used
becasue the old driver stack for eDMA did not allowed integration w/o hacks.
Due to the nature of eD
Allow the crossbar driver to be used with the eDMA node with non legacy
binding.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/ti-dma-crossbar.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/dma/ti-dma-crossbar.c b/drivers/dma/ti-dma-crossbar.c
index 1a41f75a4d1f..b7b21a243e37
In eDMA the events are directly mapped to a DMA channel (for example DMA
event 14 can only be handled by DMA channel 14). If the memcpy is enabled
on the eDMA, there is a possibility that the crossbar driver would assign
DMA event number already allocated in eDMA for memcpy. Furthermore the
eDMA ca
The use of idr was nice, but it was a bit heavy and we did not need the
features it provides. Using simple bitmap to track allocated DMA channels
is adequate here and it will be easier to add support for reserving
channels later on.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/ti-dma-crossbar.c
Hi
On 10/29/2015 01:36 PM, Lee Jones wrote:
On Thu, 29 Oct 2015, Alim Akhtar wrote:
From: Thomas Abraham
Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz
clock outputs and battery charger. Thi
Hi Tom,
On Thu, Oct 22, 2015 at 01:14:12PM -0500, Tom Zanussi wrote:
> Add tracing_map, a special-purpose lock-free map for tracing.
>
> tracing_map is designed to aggregate or 'sum' one or more values
> associated with a specific object of type tracing_map_elt, which
> is associated by the map t
Hi Igal,
[auto build test ERROR on net/master -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/igal-liberman-freescale-com/Freescale-DPAA-FMan/20151028-205843
config: arm-allmodconfig (attached as .config)
32-bit ioctl uses these rather than the regular FS_IOC_* versions. They can
be handled in btrfs using the same code. Without this, 32-bit {ch,ls}attr
fail.
Signed-off-by: Luke Dashjr
Cc: sta...@vger.kernel.org
---
fs/btrfs/ctree.h | 1 +
fs/btrfs/file.c | 2 +-
fs/btrfs/inode.c | 2 +-
fs/bt
On Friday, May 15, 2015 11:19:22 AM David Sterba wrote:
> On Thu, May 14, 2015 at 04:27:54PM +, Luke Dashjr wrote:
> > On Thursday, May 14, 2015 2:06:17 PM David Sterba wrote:
> > > On Wed, May 13, 2015 at 05:15:26PM +, Luke Dashjr wrote:
> > > > 32-bit ioctl uses these rather than the regu
On 2015/10/29 15:36, Yang Yingliang wrote:
On 2015/10/27 22:03, Mark Rutland wrote:
On Tue, Oct 27, 2015 at 09:21:13PM +0800, Yang Yingliang wrote:
In multi-core system, if the clock is not sync perfectly, it
will make cycle_last that recorded by CPU-A is a little more
than cycle_now that rea
From: Thierry Reding
Add a helper to check if an object (given an address and a size) is part
of a section (given beginning and end addresses). For convenience, also
provide a helper that performs this check for __init data using the
__init_begin and __init_end limits.
Signed-off-by: Thierry Red
On Wed, Oct 28, 2015 at 11:32:29PM -0500, Rob Herring wrote:
> On Fri, Oct 9, 2015 at 9:20 AM, Leo Yan wrote:
> > On Fri, Oct 09, 2015 at 08:50:13AM -0500, Rob Herring wrote:
> >> On Fri, Oct 9, 2015 at 8:30 AM, Mark Rutland wrote:
> >> > On Fri, Oct 09, 2015 at 08:17:16AM -0500, Rob Herring wrot
Hi,
On 10/29/2015 01:43 PM, Krzysztof Kozlowski wrote:
On 29.10.2015 17:08, Lee Jones wrote:
On Thu, 29 Oct 2015, Alim Akhtar wrote:
From: Thomas Abraham
The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
27 LDO and 10 Buck regulators and allows programming these r
Thanks.
On 2015/10/28 19:42, Philipp Zabel wrote:
> Am Dienstag, den 27.10.2015, 17:51 +0800 schrieb Chen Feng:
>> reset: add driver for hi6220 reset controller
>>
>> Signed-off-by: Chen Feng
>> ---
>> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++
>> 1 file changed, 7 insertions(+)
>>
>
Am Donnerstag, 29. Oktober 2015, 09:12:21 schrieb Yakir Yang:
> Hi Heiko,
>
> On 10/29/2015 04:02 AM, Heiko Stuebner wrote:
> > Hi Yakir,
> >
> > Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Yakir Yang:
> >> diff --git
> >> a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> >>
On Wed, Oct 28, 2015 at 08:41:41AM -0500, Nathan Sullivan wrote:
> The USB OTG support currently depends on power management
> (CONFIG_PM) being enabled, but does not actually need it enabled.
> Remove this dependency.
>
> Remove the unneeded "default n" from USB_OTG as well, the default is
> alre
On 2015年10月29日 14:58, Alexander Duyck wrote:
>
> Your code was having to do a bunch of shuffling in order to get things
> set up so that you could bring the interface back up. I would argue
> that it may actually be faster at least on the bring-up to just drop the
> old rings and start over since
This path introduces a helper which can give a hint for whether or not
there's a work queued in the work list.
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 7 +++
drivers/vhost/vhost.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.
This patch tries to poll for new added tx buffer for a while at the
end of tx processing. The maximum time spent on polling were limited
through a module parameter. To avoid block rx, the loop will end it
there's new other works queued on vhost so in fact socket receive
queue is also be polled.
Si
Hi all:
This series tries to add basic busy polling for vhost net. The idea is
simple: at the end of tx processing, busy polling for new tx added
descriptor and rx receive socket for a while. The maximum number of
time (in us) could be spent on busy polling was specified through
module parameter.
Am 29.10.2015 um 08:27 schrieb Saurabh Sengar:
> replace GFP_KERNEL with GFP_ATOMIC while spinlock is held,
> as code while holding a spinlock should be atomic.
> GFP_KERNEL may sleep and can cause deadlock,
> where as GFP_ATOMIC may fail but certainly avoids deadlock
As UML does not support SMP n
On 10/21/2015 12:10 PM, Sudeep Holla wrote:
> Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
> check for/support the legacy "gpio-key,wakeup" boolean property to
> enable gpio buttons as wakeup source, "wakeup-source" is the new
> standard binding.
>
> This patch replaces
On Wed, Oct 28, 2015 at 03:51:58PM -0700, Andy Lutomirski wrote:
> On Wed, Oct 28, 2015 at 9:12 AM, Michael S. Tsirkin wrote:
> > On Wed, Oct 28, 2015 at 11:32:34PM +0900, David Woodhouse wrote:
> >> > I don't have a problem with extending DMA API to address
> >> > more usecases.
> >>
> >> No, thi
Hi Linus,
On 10/23/2015 07:44 AM, Sören Brinkmann wrote:
> On Fri, 2015-10-23 at 07:31AM +0200, Mike Looijmans wrote:
>> On 22-10-15 18:07, Sören Brinkmann wrote:
>>> Hi Mike,
>>>
>>> On Thu, 2015-10-22 at 01:30PM +0200, Mike Looijmans wrote:
Supplying pinmux configuration for e.g. gpio pins
ENOSYS is reserved to report invalid syscalls to userspace.
Consistently return ENOTSUPP to indicate that the driver doesn't support
the functionality or the reset framework is not enabled at all.
Signed-off-by: Philipp Zabel
---
drivers/reset/core.c | 8
include/linux/reset.h | 8
Since this array is static const, it should be marked as __initconst.
Signed-off-by: Philipp Zabel
---
drivers/reset/reset-sunxi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
index df58e71..58ddb26 100644
--- a/dri
Hi Igal,
[auto build test ERROR on net/master -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/igal-liberman-freescale-com/Freescale-DPAA-FMan/20151028-205843
config: arm-allmodconfig (attached as .config)
On Thu, Oct 22, 2015 at 01:14:13PM -0500, Tom Zanussi wrote:
> 'hist' triggers allow users to continually aggregate trace events,
> which can then be viewed afterwards by simply reading a 'hist' file
> containing the aggregation in a human-readable format.
>
> The basic idea is very simple and boi
Eddie Huang writes:
> Hi Kevin,
>
> On Mon, 2015-10-26 at 17:06 +0900, Kevin Hilman wrote:
>> On Mon, Oct 26, 2015 at 4:15 PM, Yingjoe Chen
>> wrote:
>> > On Mon, 2015-10-26 at 09:56 +0900, Kevin Hilman wrote:
>> >> Hello,
>> >>
>> >> On Sat, Oct 3, 2015 at 12:19 AM, Yingjoe Chen
>> >> wrote:
This just fixes a checkpatch warning, no functional change.
Signed-off-by: Philipp Zabel
---
drivers/reset/sti/reset-syscfg.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/reset/sti/reset-syscfg.c b/drivers/reset/sti/reset-syscfg.c
index a78e09c..1600cc7 100644
-
Hi Philipp,
On 10/29/2015 10:12 AM, Philipp Zabel wrote:
This just fixes a checkpatch warning, no functional change.
Signed-off-by: Philipp Zabel
---
drivers/reset/sti/reset-syscfg.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Acked-by: Maxime Coquelin
Thanks,
Maxime
--
To
replace GFP_KERNEL with GFP_ATOMIC while spinlock is held,
as code while holding a spinlock should be atomic.
GFP_KERNEL may sleep and can cause deadlock,
where as GFP_ATOMIC may fail but certainly avoids deadlock
Signed-off-by: Saurabh Sengar
---
v3: removed the atomic variable, as per Richard c
On Wed, 28 Oct 2015, Joe Perches wrote:
> On Wed, 2015-10-28 at 17:49 +, Lee Jones wrote:
> > On Wed, 28 Oct 2015, Joe Perches wrote:
> > > On Wed, 2015-10-28 at 17:22 +, Lee Jones wrote:
> > > > On Wed, 28 Oct 2015, Joe Perches wrote:
> > > > > > Acked-by: Lee Jones
> > > > > It'd be be
rename_rev.pl is a script to strip away the mechanical changes that we
often see in staging patches and leave just the interesting changes for
manual review.
There are two new features in this version of rename_rev.pl. The
-r option let's you use some pre-written recipes. There are
two recipes
From: gabriele paoloni
dw_pcie_host_init() creates the PCI host bridge with pci_common_init_dev(),
an ARM-specific function that supplies the ARM-specific pci_sys_data
structure as the PCI "sysdata". To use dw_pcie_host_init() on other
architectures, we will copy the internals of pci_common_init
From: gabriele paoloni
Commit f4c55c5a3f7f ("PCI: designware: Program ATU with untranslated
address") added the calculation of PCI BUS addresses in designware,
storing them in new fields added in "struct pcie_port". This
calculation is done for every designware user even if is only
applicable to
This patch uses the new of_pci_get_host_bridge_resources
API in place of the PCI OF DT parser
For reference see previous suggestions from Gabriele[1]
[1] http://www.spinics.net/lists/linux-pci/msg42194.html
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Tested-by: James Morse
Tested
This patchset adds PCIe host support for HiSilicon SoC Hip05. The PCIe hosts
use PCIe IP core from Synopsys, So this driver is based on designware PCIe
driver.
Hip05 is an ARMv8 architecture SoC. It should be able to use ARM64 PCIe API in
designware PCIe driver. So this patch also adds ARM64 supp
This patch adds PCIe host support for HiSilicon SoC Hip05, related DT binding
document and maintainer update.
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: liudongdong
Acked-by: Rob Herring
---
.../bindings/arm/hisilicon/hisilicon.txt | 17 ++
.../devicetr
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