On Tue, 26 Dec 2000, Joe deBlaquiere wrote:
> > Read the ISA manual; sc will fail if the LL-bit in c0_status is cleared
> > which will be cleared when the interrupt returns using the eret instruction.
>
> I tried to find a MIPSIII manual from mips.com but all I could find was
> mips32 and mips6
On Tue, 26 Dec 2000, Ralf Baechle wrote:
> The semantics of this syscall were previously defined by Risc/OS and later
> on continued to be used by IRIX.
Ralf, could you please provide me a copy of a man page for the call? I
don't have access to either of the systems and a search of the Net
ret
Hi!
> > Not having swap doesn't mean you're safe. Think of any kind of previously
> > unmapped page.
> >
>
> Is there a reason why it doesn't just force that page to be mapped
> first?
You can map it in... But background daemon can map it out in the
meantime :-). You'd have to map in and page
Ralf, firstly, thank you for the answers :)
Ralf Baechle wrote:
>
> Ok, but since the kernel disables MIPS III you're limited to MIPS II anyway ...
>
This makes sense...
>
>
> Read the ISA manual; sc will fail if the LL-bit in c0_status is cleared
> which will be cleared when the interrupt
On Mon, Dec 25, 2000 at 01:18:48AM -0600, Joe deBlaquiere wrote:
> I'm working with a vr4181 target and started digging into the atomic
> test and set stuff in the kernel and glibc. The first problem I had was
> that the glibc code assumes that all mips III targets implement the mips
> III ISA
I'm working with a vr4181 target and started digging into the atomic
test and set stuff in the kernel and glibc. The first problem I had was
that the glibc code assumes that all mips III targets implement the mips
III ISA (funny assumption, no?) but the vr4181 doesn't include the
miltiprocesso
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