Re: [PATCH] MIPS: Fix exception entry when CONFIG_EVA enabled

2017-11-15 Thread Maciej W. Rozycki
Hi Matt, On Wed, 15 Nov 2017, Maciej W. Rozycki wrote: > Can you send me .i output from the offending source along with GCC > options used to make .o output (use `V=1' with `make' if needed)? I'll > check if my hypothesis is right or find the actual cause otherwise. Thanks for the pieces re

Re: [PATCH] MIPS: Fix exception entry when CONFIG_EVA enabled

2017-11-15 Thread Maciej W. Rozycki
On Wed, 15 Nov 2017, Matt Redfearn wrote: > I like the change you propose, however I can't coax GAS to reorder the > instructions appropriately. With this patch on top of 4.14: > > --- a/arch/mips/include/asm/stackframe.h > +++ b/arch/mips/include/asm/stackframe.h > @@ -195,14 +195,16 @@ >

Re: [PATCH] MIPS: Fix exception entry when CONFIG_EVA enabled

2017-11-15 Thread Matt Redfearn
On 13/11/17 10:47, Maciej W. Rozycki wrote: On Tue, 31 Oct 2017, James Hogan wrote: I looked this over pretty carefully and it looks correct to me.  It makes no difference in the instructions generated by the non-EVA case.  I shouldn't have missed this :(. Reviewed-by: Corey Minyard Yeh,

Re: [PATCH] MIPS: Fix exception entry when CONFIG_EVA enabled

2017-11-13 Thread Maciej W. Rozycki
On Tue, 31 Oct 2017, James Hogan wrote: > > I looked this over pretty carefully and it looks correct to me.  It > > makes no difference > > in the instructions generated by the non-EVA case.  I shouldn't have > > missed this :(. > > > > Reviewed-by: Corey Minyard > > Yeh, having stared at it

Re: [PATCH] MIPS: Fix exception entry when CONFIG_EVA enabled

2017-10-31 Thread James Hogan
On Wed, Oct 11, 2017 at 08:12:31AM -0500, Corey Minyard wrote: > On 10/11/2017 03:59 AM, Matt Redfearn wrote: > > Commit 9fef68686317b ("MIPS: Make SAVE_SOME more standard") made several > > changes to the order in which registers are saved in the SAVE_SOME > > macro, used by exception handlers to

Re: [PATCH] MIPS: Fix exception entry when CONFIG_EVA enabled

2017-10-18 Thread Maciej W. Rozycki
On Wed, 11 Oct 2017, Matt Redfearn wrote: > diff --git a/arch/mips/include/asm/stackframe.h > b/arch/mips/include/asm/stackframe.h > index 5d3563c55e0c..2161357cc68f 100644 > --- a/arch/mips/include/asm/stackframe.h > +++ b/arch/mips/include/asm/stackframe.h > @@ -199,6 +199,10 @@ >

Re: [PATCH] MIPS: Fix exception entry when CONFIG_EVA enabled

2017-10-11 Thread Corey Minyard
On 10/11/2017 03:59 AM, Matt Redfearn wrote: Commit 9fef68686317b ("MIPS: Make SAVE_SOME more standard") made several changes to the order in which registers are saved in the SAVE_SOME macro, used by exception handlers to save the processor state. In particular, it removed the move k1, sp in th