On Tue, Mar 01, 2016 at 07:04:40PM +0100, Jiri Olsa wrote:
> > That's the PERF_GLOBAL_CTRL, right? But it must have succeeded,
>
> yep, should be this one:
>
> static void __intel_pmu_enable_all(int added, bool pmi)
> {
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>
>
On Tue, Mar 01, 2016 at 06:17:22PM +0100, Jiri Olsa wrote:
> I tried what Andy suggested below (not sure what he meant by Merom,
> I took PEBS format0 instead), works for me
Model 15, see intel_pmu_init(). But you're actually running on a Penryn
I suspect, since we disabled PEBS for Merom.
There'
On Tue, Mar 01, 2016 at 06:49:03PM +0100, Peter Zijlstra wrote:
> On Tue, Mar 01, 2016 at 06:17:22PM +0100, Jiri Olsa wrote:
>
> > [ 125.982977] [] ?
> > __intel_pmu_enable_all.isra.11+0x4b/0xd0^M
> > [ 125.982977] [] ?
> > __intel_pmu_enable_all.isra.11+0x4b/0xd0^M
> > [ 125.982977] [] ?
On Tue, Mar 01, 2016 at 06:17:22PM +0100, Jiri Olsa wrote:
> [ 125.982977] [] ?
> __intel_pmu_enable_all.isra.11+0x4b/0xd0^M
> [ 125.982977] [] ?
> __intel_pmu_enable_all.isra.11+0x4b/0xd0^M
> [ 125.982977] [] ?
> __intel_pmu_enable_all.isra.11+0x4b/0xd0^M
> [ 125.982977] <> [] intel_p
> I tried what Andy suggested below (not sure what he meant by Merom,
> I took PEBS format0 instead), works for me
Thanks Jiri. Patch looks good to me.
Reviewed-by: Andi Kleen
We may want to make this buffer size a configurable anyways because
with multi-record PEBS it can make sense to use muc
On Tue, Mar 01, 2016 at 03:59:09PM +0100, Peter Zijlstra wrote:
> On Tue, Mar 01, 2016 at 03:51:05PM +0100, Andi Kleen wrote:
> > > im on it.. also the patch that makes this happen just
> > > enlarge the buffer for PEBS:
> > >
> > > 156174999dd1 perf/intel/x86: Enlarge the PEBS buffer
> > >
> >
On Tue, Mar 01, 2016 at 03:51:05PM +0100, Andi Kleen wrote:
> > im on it.. also the patch that makes this happen just
> > enlarge the buffer for PEBS:
> >
> > 156174999dd1 perf/intel/x86: Enlarge the PEBS buffer
> >
> > but I did not find anyaPEBS buffer lenght limitations in SDM
>
> May be th
> im on it.. also the patch that makes this happen just
> enlarge the buffer for PEBS:
>
> 156174999dd1 perf/intel/x86: Enlarge the PEBS buffer
>
> but I did not find anyaPEBS buffer lenght limitations in SDM
May be the easiest would be to just keep the old buffer size
on Merom.
-Andi
On Tue, Mar 01, 2016 at 12:06:51PM +0100, Jiri Olsa wrote:
> >
> > [ Jiri, can you disable that stupid panic on hard lockup and let it run
> > for a while, see if all the lockup msgs hit the same IP? Also, can you
> > look where exactly that IP lives in the code? ]
>
> im on it..
Thanks!
> als
On Tue, Mar 01, 2016 at 10:17:03AM +0100, Peter Zijlstra wrote:
> On Mon, Feb 29, 2016 at 10:12:08PM +, Liang, Kan wrote:
>
> > In SDM "18.4.4.4 Re-configuring PEBS Facilities" it mentioned that
> > a quiescent period is needed between stopping the prior event counting and
> > setting up a new
On Mon, Feb 29, 2016 at 10:12:08PM +, Liang, Kan wrote:
> In SDM "18.4.4.4 Re-configuring PEBS Facilities" it mentioned that
> a quiescent period is needed between stopping the prior event counting and
> setting up a new PEBS event when software needs to reconfigure PEBS
> facilities.
> The q
On Mon, Feb 29, 2016 at 10:12:08PM +, Liang, Kan wrote:
>
>
> >
> > I can't find what's special about Core2 CPU PEBS setup, it seems that oher
> > CPUs are ok (tried on ivb/snb/hsw).
> >
> > reverting the 156174999dd1 fixed the issue for me
> >
> > ideas? thanks,
>
> I think we may just d
>
> I can't find what's special about Core2 CPU PEBS setup, it seems that oher
> CPUs are ok (tried on ivb/snb/hsw).
>
> reverting the 156174999dd1 fixed the issue for me
>
> ideas? thanks,
I think we may just disable the multiple pebs support for core2
as the patch below.
In SDM "18.4.4.4 R
> I can't find what's special about Core2 CPU PEBS setup,
> it seems that oher CPUs are ok (tried on ivb/snb/hsw).
>
> reverting the 156174999dd1 fixed the issue for me
Ok multi-record PEbS was never tested on Core 2. I suppose we
can enable it only on Nehalem+
-Andi
--
a...@linux.intel.com -
On Sat, Feb 27, 2016 at 01:37:01PM +0100, Jiri Olsa wrote:
> we are getting hard lockups on Core2 cpus (model 23)
> I can't find what's special about Core2 CPU PEBS setup,
> it seems that oher CPUs are ok (tried on ivb/snb/hsw).
>
> reverting the 156174999dd1 fixed the issue for me
>
> ideas? th
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