>
> I can't find what's special about Core2 CPU PEBS setup, it seems that oher
> CPUs are ok (tried on ivb/snb/hsw).
>
> reverting the 156174999dd1 fixed the issue for me
>
> ideas? thanks,
I think we may just disable the multiple pebs support for core2
as the patch below.
In SDM "18.4.4.4 Re-configuring PEBS Facilities" it mentioned that
a quiescent period is needed between stopping the prior event counting and
setting up a new PEBS event when software needs to reconfigure PEBS facilities.
The quiescent period is to allow any latent residual PEBS records to complete
its capture at their previously specified buffer address
That requirement only can be found in Core Microarchitecture.
I think it may implies that there is some observed delay in writing PEBS buffer.
So if perf record precise hw event with very small period, the slow PEBS writing
may lockup the CPU. If so, I think disabling the multiple pebs should be a good
way.
---
arch/x86/events/intel/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 8fddb02..a56230f 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2577,8 +2577,8 @@ static int intel_pmu_hw_config(struct perf_event *event)
if (event->attr.precise_ip) {
if (!event->attr.freq) {
event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
- if (!(event->attr.sample_type &
- ~intel_pmu_free_running_flags(event)))
+ if ((x86_pmu.intel_cap.pebs_format > 0) &&
+ !(event->attr.sample_type &
~intel_pmu_free_running_flags(event)))
event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
}
if (x86_pmu.pebs_aliases)
--
2.5.0
Thanks,
Kan
