Re: [PATCH v5 4/7] dmaengine: xilinx_dma: program hardware supported buffer length

2018-10-07 Thread Andrea Merello
On Tue, Oct 2, 2018 at 4:56 PM Vinod wrote: > > On 28-09-18, 08:53, Andrea Merello wrote: > > On Tue, Sep 18, 2018 at 6:25 PM Vinod wrote: > > > > > @@ -964,7 +968,7 @@ static int xilinx_dma_calc_copysize(struct > > > > xilinx_dma_chan *chan, > > > > int size, i

Re: [PATCH v5 4/7] dmaengine: xilinx_dma: program hardware supported buffer length

2018-10-02 Thread Vinod
On 28-09-18, 08:53, Andrea Merello wrote: > On Tue, Sep 18, 2018 at 6:25 PM Vinod wrote: > > > @@ -964,7 +968,7 @@ static int xilinx_dma_calc_copysize(struct > > > xilinx_dma_chan *chan, > > > int size, int done) > > > { > > > size_t copy = min_t(size_t,

Re: [PATCH v5 4/7] dmaengine: xilinx_dma: program hardware supported buffer length

2018-09-27 Thread Andrea Merello
On Tue, Sep 18, 2018 at 6:25 PM Vinod wrote: > > On 07-09-18, 08:24, Andrea Merello wrote: > > From: Radhey Shyam Pandey > > > > AXI-DMA IP supports configurable (c_sg_length_width) buffer length > > register width, hence read buffer length (xlnx,sg-length-width) DT > > property and ensure that d

Re: [PATCH v5 4/7] dmaengine: xilinx_dma: program hardware supported buffer length

2018-09-18 Thread Vinod
On 07-09-18, 08:24, Andrea Merello wrote: > From: Radhey Shyam Pandey > > AXI-DMA IP supports configurable (c_sg_length_width) buffer length > register width, hence read buffer length (xlnx,sg-length-width) DT > property and ensure that driver doesn't program buffer length > exceeding the support

[PATCH v5 4/7] dmaengine: xilinx_dma: program hardware supported buffer length

2018-09-06 Thread Andrea Merello
From: Radhey Shyam Pandey AXI-DMA IP supports configurable (c_sg_length_width) buffer length register width, hence read buffer length (xlnx,sg-length-width) DT property and ensure that driver doesn't program buffer length exceeding the supported limit. For VDMA and CDMA there is no change. Cc: R