Re: [PATCH v3 13/13] spi: atmel-quadspi: add support for sam9x60 qspi controller

2019-02-02 Thread Boris Brezillon
On Sat, 2 Feb 2019 08:58:25 + wrote: > >> @@ -117,6 +120,7 @@ > >> #define QSPI_IFR_CRMBIT(14) > >> #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16) > >> #define QSPI_IFR_NBDUM(n) (((n) << 16) & > >> QSPI_IFR_NBDUM_MASK) > >> +#define QSPI_IFR_APBT

Re: [PATCH v3 13/13] spi: atmel-quadspi: add support for sam9x60 qspi controller

2019-02-02 Thread Tudor.Ambarus
On 02/02/2019 09:29 AM, Boris Brezillon wrote: > On Sat, 2 Feb 2019 04:07:46 + > wrote: > >> From: Tudor Ambarus >> >> The sam9x60 qspi controller uses 2 clocks, one for the peripheral register >> access, the other for the qspi core and phy. Both are mandatory. It uses >> different transfe

Re: [PATCH v3 13/13] spi: atmel-quadspi: add support for sam9x60 qspi controller

2019-02-01 Thread Boris Brezillon
On Sat, 2 Feb 2019 04:07:46 + wrote: > From: Tudor Ambarus > > The sam9x60 qspi controller uses 2 clocks, one for the peripheral register > access, the other for the qspi core and phy. Both are mandatory. It uses > different transfer type bits in IFR register. It has dedicated registers > t

[PATCH v3 13/13] spi: atmel-quadspi: add support for sam9x60 qspi controller

2019-02-01 Thread Tudor.Ambarus
From: Tudor Ambarus The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. It uses different transfer type bits in IFR register. It has dedicated registers to specify a read or a write instruction: Read Instructi