> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = ,
> > +,
> > +,
> > +;
>
> No, this is completely wrong. The timer is always level triggered, and you're
> missing the affinity bits
> On Fri, Sep 09, 2016 at 06:55:30AM +, S.H. Xie wrote:
> > > On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote:
> > > > On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh@gmail.com wrote:
> > > > > + cpus {
> > > > > + #address-cells = <1>;
> > > > > + #si
> On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote:
> > On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh@gmail.com wrote:
> > > + cpus {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + cpu0: cpu@0 {
> > > + device_type =
On Fri, Sep 09, 2016 at 06:55:30AM +, S.H. Xie wrote:
> > On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote:
> > > On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh@gmail.com wrote:
> > > > + cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cel
rm.com;
> will.dea...@arm.com; linux-kernel@vger.kernel.org; Mihai Emilian Bantea
> ; C.H. Zhao ; a...@arndb.de;
> S.H. Xie ; Z.Q. Hou ; M.H. Lian
> ; Vincent Hu ; Horia Geanta
> Neag ; Q.Y. Gong
> Subject: Re: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support
>
>
> > + pmu {
> > + compatible = "arm,armv8-pmuv3";
> > + interrupts = ,
> > +,
> > +,
> > +;
> > + interrupt-affinity = <&cpu0>,
> > +<&cpu1>,
> > +
On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote:
> On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh@gmail.com wrote:
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
On 05/09/16 11:01, shh@gmail.com wrote:
> From: Mingkai Hu
>
> LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks
> are similar to LS1043A which also complies to Freescale Chassis 2.1
> spec.
>
> Created LS1046A SoC DTSI file to be included by board level DTS
> files.
>
> Sig
On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh@gmail.com wrote:
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> +
On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh@gmail.com wrote:
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clockgen: clocking@1ee1000 {
> + compa
From: Mingkai Hu
LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks
are similar to LS1043A which also complies to Freescale Chassis 2.1
spec.
Created LS1046A SoC DTSI file to be included by board level DTS
files.
Signed-off-by: Horia Geant?
Signed-off-by: Mihai Bantea
Signed-of
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