On 22/04/16 08:53, Minghuan Lian wrote:
> Hi Marc,
>
> Please see the link:
> https://patchwork.kernel.org/patch/8649241/
>
> Rob Herring has given the ACK.
>
> I have submitted the v6 patch: https://patchwork.kernel.org/patch/8649251/
> Please apply the latest the patch after you review.
Than
o Li
> ; Rob Herring ; Mark Rutland
>
> Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller
> support
>
> On 22/04/16 06:33, Leo Li wrote:
> > On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier
> wrote:
> >> On Mon, 7 Mar 2016 11:36:22 +0800
> &
On 22/04/16 06:33, Leo Li wrote:
> On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier wrote:
>> On Mon, 7 Mar 2016 11:36:22 +0800
>> Minghuan Lian wrote:
>>
>>> Some kind of NXP Layerscape SoC provides a MSI
>>> implementation which uses two SCFG registers MSIIR and
>>> MSIR to support 32 MSI interrupt
On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier wrote:
> On Mon, 7 Mar 2016 11:36:22 +0800
> Minghuan Lian wrote:
>
>> Some kind of NXP Layerscape SoC provides a MSI
>> implementation which uses two SCFG registers MSIIR and
>> MSIR to support 32 MSI interrupts for each PCIe controller.
>> The patch
On 23/03/16 11:19, Alexander Stein wrote:
> On Wednesday 23 March 2016 11:08:04, Marc Zyngier wrote:
>>> Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit
>>> strange though:
grep eth3 /proc/interrupts
63: 49 0 MSI 134742016 Edge
On Wednesday 23 March 2016 11:08:04, Marc Zyngier wrote:
> > Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit
> > strange though:
> >> grep eth3 /proc/interrupts
> >>
> >> 63: 49 0 MSI 134742016 Edge eth3-rx-0
> >> 64: 3 0
On 23/03/16 09:18, Alexander Stein wrote:
> On Monday 07 March 2016 11:36:22, Minghuan Lian wrote:
>> Some kind of NXP Layerscape SoC provides a MSI
>> implementation which uses two SCFG registers MSIIR and
>> MSIR to support 32 MSI interrupts for each PCIe controller.
>> The patch is to support it
vger.kernel.org
> Cc: Minghuan Lian ;
> linux-arm-ker...@lists.infradead.org; Marc Zyngier ;
> Thomas Gleixner ; Jason Cooper
> ; Roy Zang ; Mingkai Hu
> ; Stuart Yoder ; Yang-Leo Li
>
> Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller
> support
>
&
On Monday 07 March 2016 11:36:22, Minghuan Lian wrote:
> Some kind of NXP Layerscape SoC provides a MSI
> implementation which uses two SCFG registers MSIIR and
> MSIR to support 32 MSI interrupts for each PCIe controller.
> The patch is to support it.
>
> Signed-off-by: Minghuan Lian
Tested-by:
On Mon, 7 Mar 2016 11:36:22 +0800
Minghuan Lian wrote:
> Some kind of NXP Layerscape SoC provides a MSI
> implementation which uses two SCFG registers MSIIR and
> MSIR to support 32 MSI interrupts for each PCIe controller.
> The patch is to support it.
>
> Signed-off-by: Minghuan Lian
Acked-by
Some kind of NXP Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.
Signed-off-by: Minghuan Lian
---
Change log
v5:
1. drop nr_irqs from struct ls_scfg_msi
v4:
1. do not reg
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