On Mon, 7 Mar 2016 11:36:22 +0800 Minghuan Lian <minghuan.l...@nxp.com> wrote:
> Some kind of NXP Layerscape SoC provides a MSI
> implementation which uses two SCFG registers MSIIR and
> MSIR to support 32 MSI interrupts for each PCIe controller.
> The patch is to support it.
>
> Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
Acked-by: Marc Zyngier <marc.zyng...@arm.com>
The DT binding still needs an Ack from the DT maintainers though (cc'd).
M.
--
Jazz is not dead. It just smells funny.
