On Wed, 18 Nov 2020, Wu, Hao wrote:
On Tue, 17 Nov 2020, Wu, Hao wrote:
[...]
Open discussion
===
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index b1b157b41942..5418e8bf2496 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -27,6 +27,13 @@
On Tue, Nov 17, 2020 at 11:41:32AM -0800, matthew.gerl...@linux.intel.com wrote:
>
>
> On Tue, 17 Nov 2020, Xu Yilun wrote:
>
> >On Mon, Nov 16, 2020 at 05:25:52PM -0800, matthew.gerl...@linux.intel.com
> >wrote:
> >>From: Matthew Gerlach
> >>
> >>A DFL may not begin at offset 0 of BAR 0. A P
> On Tue, 17 Nov 2020, Wu, Hao wrote:
[...]
> >> Open discussion
> >> ===
> >> diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> >> index b1b157b41942..5418e8bf2496 100644
> >> --- a/drivers/fpga/dfl-pci.c
> >> +++ b/drivers/fpga/dfl-pci.c
> >> @@ -27,6 +27,13 @@
> >>
>> Is this really an either/or ?
>>
>> Could there be a base functionality on bar0 and a skew functionality on
>> vendor bars?
>
> For simplicity I think either or is better. If skew functionality is in
> vendor bars, why not just use the vendor bars all the time.
>
>>
>> If vendor is going to
On Tue, 17 Nov 2020, Tom Rix wrote:
On 11/16/20 5:25 PM, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Signed-off-by: Matthew Gerlach
---
Do
On 11/16/20 5:25 PM, matthew.gerl...@linux.intel.com wrote:
> From: Matthew Gerlach
>
> A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
> specific capability can be used to specify the start of a
> number of DFLs.
>
> Signed-off-by: Matthew Gerlach
> ---
> Documentation/fpga/dfl.rst |
On Tue, 17 Nov 2020, Wu, Hao wrote:
Subject: [PATCH 2/2] fpga: dfl: look for vendor specific capability
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Signed-off-by: Matthew Gerlach
On Tue, 17 Nov 2020, Xu Yilun wrote:
On Mon, Nov 16, 2020 at 05:25:52PM -0800, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Signed-off-by: Mat
Hi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linux/master]
[also build test WARNING on linus/master v5.10-rc4 next-20201117]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as d
> > +
> > + start = pci_resource_start(pcidev, bar) + offset;
> > + len -= offset;
>
> With these code, I have the following assumption:
>
> 1. There is only one DFL in one bar, multiple DFLs requires multiple
> bars.
>
> 2. The DFL region is from the "offset" to the end of t
> Subject: [PATCH 2/2] fpga: dfl: look for vendor specific capability
>
> From: Matthew Gerlach
>
> A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
> specific capability can be used to specify the start of a
> number of DFLs.
>
> Signed-off-by: Matthew Gerl
On Mon, Nov 16, 2020 at 05:25:52PM -0800, matthew.gerl...@linux.intel.com wrote:
> From: Matthew Gerlach
>
> A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
> specific capability can be used to specify the start of a
> number of DFLs.
>
> Signed-off-by: Matthew Gerlach
> ---
> Documen
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Signed-off-by: Matthew Gerlach
---
Documentation/fpga/dfl.rst | 10 +
drivers/fpga/dfl-pci.c | 88 +++
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