[Unchanged since last posted - except to add Boris' Acked-by
since after further discussion his nitpick didn't warrant a
change. Ready for x86/mce branch ... and if possible to
move to Linus in this merge window]
This patch series adds a workaround for some strange
asymmetry between how machine
This patch series adds a workaround for some strange
asymmetry between how machine checks are reported for
data and instruction fetches. For instruction fetch
error the processor does not set the EIPV bit in the
MCG_STATUS register on the affected processor, leading
us to believe that the cs/ip val
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