This patch series adds a workaround for some strange
asymmetry between how machine checks are reported for
data and instruction fetches. For instruction fetch
error the processor does not set the EIPV bit in the
MCG_STATUS register on the affected processor, leading
us to believe that the cs/ip values saved on the stack
are not associated with the machine check ... which in
turn makes us unable to determine whether the machine
check was taken in kernel or user mode. The workaround
is to fake the presence of the EIPV bit for this error
on this processor model. Not pretty, but avoids having
to make special cases later in the code.
Tony Luck (2):
x86/mce: Move MCACOD defines from mce-severity.c to <asm/mce.h>
x86/mce: Add quirk for instruction recovery on Sandy Bridge
processors
arch/x86/include/asm/mce.h | 8 ++++++
arch/x86/kernel/cpu/mcheck/mce-severity.c | 7 -----
arch/x86/kernel/cpu/mcheck/mce.c | 43 ++++++++++++++++++++++++++++---
3 files changed, 48 insertions(+), 10 deletions(-)
--
1.7.10.2.552.gaa3bb87
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