On 06/20/2013 02:46 PM, Luck, Tony wrote:
From: Chen Gong
Update some SRAR severity conditions check to make it clearer
according to latest Intel SDM Vol 3B (June 2013), table 15-20.
Signed-off-by: Chen Gong
Signed-off-by: Tony Luck
---
Chen Gong wrote:
If this patch is OK, would you pleas
On Wed, Jun 26, 2013 at 11:10:52PM +0200, Borislav Petkov wrote:
> Date: Wed, 26 Jun 2013 23:10:52 +0200
> From: Borislav Petkov
> To: "Luck, Tony"
> Cc: "linux-kernel@vger.kernel.org" , Chen
> Gong , "Naveen N. Rao"
>
> Subject: Re: [PATCH]
On Wed, Jun 26, 2013 at 09:00:10PM +, Luck, Tony wrote:
> > And this obviously is the case for the hardware too, I assume, not only
> > the SDM?
>
> Yes - we have a magic process which reconfigures all deployed silicon whenever
> a new SDM is published :-)
Haha, I wouldn't wonder if your sili
> And this obviously is the case for the hardware too, I assume, not only
> the SDM?
Yes - we have a magic process which reconfigures all deployed silicon whenever
a new SDM is published :-)
Actually the SDM had been collecting new features for each generation ... each
time just bolting on a new
On Wed, Jun 26, 2013 at 08:23:47PM +, Luck, Tony wrote:
> MCESEV(
> > - KEEP, "HT thread notices Action required: data load error",
> > - SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD,
> > MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
> > - MCGMASK(MCG_STATUS_EIP
MCESEV(
> - KEEP, "HT thread notices Action required: data load error",
> - SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD,
> MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
> - MCGMASK(MCG_STATUS_EIPV, 0)
> + KEEP, "Action required but unaffected th
On Thu, Jun 20, 2013 at 05:16:12AM -0400, Luck, Tony wrote:
> From: Chen Gong
>
> Update some SRAR severity conditions check to make it clearer
> according to latest Intel SDM Vol 3B (June 2013), table 15-20.
>
> Signed-off-by: Chen Gong
> Signed-off-by: Tony Luck
> ---
>
> Chen Gong wrote:
>
On Tue, Jun 25, 2013 at 04:31:23PM +, Luck, Tony wrote:
> Date: Tue, 25 Jun 2013 16:31:23 +
> From: "Luck, Tony"
> To: "Naveen N. Rao" , Chen Gong
>
> CC: "b...@alien8.de" , "linux-kernel@vger.kernel.org"
>
> Subject: RE: [P
On 06/25/2013 10:01 PM, Luck, Tony wrote:
The SDM talks about "non-affected" logical processors, but perhaps we
can call this an "unaffected" thread?
"unaffected" sounds a bit more natural (but close enough to the wording in
the SDM that people should see the connection).
Yup - "unnatural" is
> The SDM talks about "non-affected" logical processors, but perhaps we
> can call this an "unaffected" thread?
"unaffected" sounds a bit more natural (but close enough to the wording in
the SDM that people should see the connection).
-Tony
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On 2013/06/20 05:16AM, Chen Gong wrote:
> Update some SRAR severity conditions check to make it clearer,
> according to latest Intel SDM Vol 3(June 2013), table 15-20.
>
> Signed-off-by: Chen Gong
> ---
> arch/x86/kernel/cpu/mcheck/mce-severity.c | 15 +--
> 1 file changed, 5 inser
On Thu, Jun 20, 2013 at 11:41:52AM +0200, Borislav Petkov wrote:
> Date: Thu, 20 Jun 2013 11:41:52 +0200
> From: Borislav Petkov
> To: Chen Gong
> Cc: tony.l...@intel.com, linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] x86/MCE: Update MCE severity condition check
> User-
On Thu, Jun 20, 2013 at 05:16:12AM -0400, Chen Gong wrote:
> Update some SRAR severity conditions check to make it clearer,
> according to latest Intel SDM Vol 3(June 2013), table 15-20.
>
> Signed-off-by: Chen Gong
> ---
> arch/x86/kernel/cpu/mcheck/mce-severity.c | 15 +--
> 1 fi
Update some SRAR severity conditions check to make it clearer,
according to latest Intel SDM Vol 3(June 2013), table 15-20.
Signed-off-by: Chen Gong
---
arch/x86/kernel/cpu/mcheck/mce-severity.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kerne
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