On 2013/06/20 05:16AM, Chen Gong wrote:
> Update some SRAR severity conditions check to make it clearer,
> according to latest Intel SDM Vol 3(June 2013), table 15-20.
>
> Signed-off-by: Chen Gong <gong.c...@linux.intel.com>
> ---
> arch/x86/kernel/cpu/mcheck/mce-severity.c | 15 +++++----------
> 1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c
> b/arch/x86/kernel/cpu/mcheck/mce-severity.c
> index beb1f16..1fa12ea 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
> @@ -110,22 +110,17 @@ static struct severity {
> /* known AR MCACODs: */
> #ifdef CONFIG_MEMORY_FAILURE
> MCESEV(
> - KEEP, "HT thread notices Action required: data load error",
> - SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD,
> MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
> - MCGMASK(MCG_STATUS_EIPV, 0)
> + KEEP, "Action required but non-affected thread is continuable",
The SDM talks about "non-affected" logical processors, but perhaps we
can call this an "unaffected" thread?
- Naveen
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