On Thu, Aug 08, 2019 at 02:33:24PM -0600, Jerry Hoemann wrote:
> On Fri, Aug 02, 2019 at 06:33:28PM +0200, Peter Zijlstra wrote:
> > On Fri, Aug 02, 2019 at 06:20:15PM +0200, Peter Zijlstra wrote:
> > > On Fri, Aug 02, 2019 at 02:33:41PM +, Lendacky, Thomas wrote:
> >
> > > > Talking to the ha
On Fri, Aug 02, 2019 at 06:33:28PM +0200, Peter Zijlstra wrote:
> On Fri, Aug 02, 2019 at 06:20:15PM +0200, Peter Zijlstra wrote:
> > On Fri, Aug 02, 2019 at 02:33:41PM +, Lendacky, Thomas wrote:
>
> > > Talking to the hardware folks, they say setting CR8 is a serializing
> > > instruction and
On Fri, Aug 02, 2019 at 06:20:15PM +0200, Peter Zijlstra wrote:
> On Fri, Aug 02, 2019 at 02:33:41PM +, Lendacky, Thomas wrote:
> > Talking to the hardware folks, they say setting CR8 is a serializing
> > instruction and has to communicate out to the APIC, so it's better to
> > use CLI/STI.
>
On Fri, Aug 02, 2019 at 02:33:41PM +, Lendacky, Thomas wrote:
> On 8/1/19 4:59 PM, Thomas Gleixner wrote:
> > On Thu, 1 Aug 2019, Peter Zijlstra wrote:
> >> On Thu, Aug 01, 2019 at 11:34:23PM +0200, Thomas Gleixner wrote:
> >>> Avoid the whole NMI mess, make the PMC interrupt a proper vector in
On 8/1/19 4:59 PM, Thomas Gleixner wrote:
> On Thu, 1 Aug 2019, Peter Zijlstra wrote:
>> On Thu, Aug 01, 2019 at 11:34:23PM +0200, Thomas Gleixner wrote:
>>> Avoid the whole NMI mess, make the PMC interrupt a proper vector in the
>>> highest prio bucket and instead of using CLI/STI use CR8. That wo
On Thu, 1 Aug 2019, Peter Zijlstra wrote:
> On Thu, Aug 01, 2019 at 11:34:23PM +0200, Thomas Gleixner wrote:
> > Avoid the whole NMI mess, make the PMC interrupt a proper vector in the
> > highest prio bucket and instead of using CLI/STI use CR8. That would have
> > the additional advantage that we
On Thu, Aug 01, 2019 at 11:34:23PM +0200, Thomas Gleixner wrote:
> On Thu, 1 Aug 2019, Lendacky, Thomas wrote:
> > On 8/1/19 4:16 PM, Peter Zijlstra wrote:
> > > On Thu, Aug 01, 2019 at 06:57:41PM +, Lendacky, Thomas wrote:
> > >> From: Tom Lendacky
> > >>
> > >> It turns out that the NMI late
On Thu, 1 Aug 2019, Lendacky, Thomas wrote:
> On 8/1/19 4:16 PM, Peter Zijlstra wrote:
> > On Thu, Aug 01, 2019 at 06:57:41PM +, Lendacky, Thomas wrote:
> >> From: Tom Lendacky
> >>
> >> It turns out that the NMI latency workaround from commit 6d3edaae16c6
> >> ("x86/perf/amd: Resolve NMI late
On 8/1/19 4:16 PM, Peter Zijlstra wrote:
> On Thu, Aug 01, 2019 at 06:57:41PM +, Lendacky, Thomas wrote:
>> From: Tom Lendacky
>>
>> It turns out that the NMI latency workaround from commit 6d3edaae16c6
>> ("x86/perf/amd: Resolve NMI latency issues for active PMCs") ends up
>> being too conser
On Thu, Aug 01, 2019 at 06:57:41PM +, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> It turns out that the NMI latency workaround from commit 6d3edaae16c6
> ("x86/perf/amd: Resolve NMI latency issues for active PMCs") ends up
> being too conservative and results in the perf NMI handler clai
From: Tom Lendacky
It turns out that the NMI latency workaround from commit 6d3edaae16c6
("x86/perf/amd: Resolve NMI latency issues for active PMCs") ends up
being too conservative and results in the perf NMI handler claiming NMIs
to easily on AMD hardware when the NMI watchdog is active.
This h
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